Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80435?usp=email )
Change subject: crossgcc: Add buildgcc support for Apple M1/M2 devices
......................................................................
crossgcc: Add buildgcc support for Apple M1/M2 devices
GMP and IASL don't compile with the default compiler and linker flags:
- GMP's check for the MacOS architecture hard coded x86_64 but it also
needs to know about arm64.
- iasl does some trickery on pointer alignment to save space(?), so we
need to tell clang about it.
Change-Id: If4cca9d3e55051a6121d992e5320bee1df17af9f
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80435
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M util/crossgcc/buildgcc
1 file changed, 4 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Felix Singer: Looks good to me, approved
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index b294da5..2919376 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -847,10 +847,11 @@
cd ../$IASL_DIR/generate/unix || exit 1
CFLAGS="$HOSTCFLAGS"
HOST="_LINUX"
- test "$UNAME" = "Darwin" && HOST="_APPLE"
+ test "$UNAME" = "Darwin" && HOST="_APPLE" && OPT_LDFLAGS="-Wl,-no_fixup_chains"
test "$UNAME" = "FreeBSD" && HOST="_FreeBSD"
test "$UNAME" = "Cygwin" && HOST="_CYGWIN"
HOST="$HOST" CFLAGS="$CFLAGS" \
+ OPT_LDFLAGS="$OPT_LDFLAGS" \
OPT_CFLAGS="-O -D_FORTIFY_SOURCE=2 -D COREBOOT_TOOLCHAIN_VERSION='\"coreboot toolchain v$CROSSGCC_VERSION\"' " \
$MAKE $JOBS CC="$(hostcc host)" iasl acpibin acpidump acpiexec acpihelp acpisrc acpixtract
mkdir -p "$DESTDIR$TARGETDIR/bin/"
@@ -1143,6 +1144,8 @@
# so we're setting the ABI explicitly here.
if [ "$(sysctl -n hw.optional.x86_64 2>/dev/null)" -eq 1 ] 2>/dev/null; then
OPTIONS="ABI=64"
+ elif [ "$(sysctl -n hw.optional.arm64 2>/dev/null)" -eq 1 ] 2>/dev/null; then
+ OPTIONS="ABI=64"
else
OPTIONS="ABI=32"
fi
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Change subject: crossgcc: Add buildgcc support for Apple M1/M2 devices
......................................................................
Patch Set 5: Code-Review+2
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Change subject: crossgcc: Add buildgcc support for Apple M1/M2 devices
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS4:
> I tried to reproduce the issue locally with coreboot-sdk and Arch Linux. Both succeeded. […]
Done
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Change subject: crossgcc: Add buildgcc support for Apple M1/M2 devices
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS4:
> Rebased just to be sure, since the coreboot-toolchain builder wasn't happy with patchset 2. […]
I tried to reproduce the issue locally with coreboot-sdk and Arch Linux. Both succeeded. Maybe the failure was related to the hardware issue. I rebased. Let's see if it vanished.
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Change subject: util/crossgcc/buildgcc: Compile RISC-V GCC with medany
......................................................................
Patch Set 3:
(1 comment)
File util/crossgcc/buildgcc:
https://review.coreboot.org/c/coreboot/+/80139/comment/d481e0e9_6118b140 :
PS1, Line 779: CFLAGS_FOR_TARGET_EXTRA
> No idea why you'd want to drop libgcc?
I was under the misapprehension that we currently only use it in RISCV because I could only find the `print-libgcc-file-name` stuff in the RISCV makefiles. Seeing now that we link to it everywhere I withdraw my statement. But I also said that I want to see if it makes sense to remove it and not that I want to remove it.
> (like 64-bit operations when compiling for 32-bit)
Not sure why we need libgcc for that? It doesn't seem to be depending too much on the compiler considering that we use the same library for clang.
Thanks for the clang comment. I didn't see that before.
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Change subject: device/azalia: Separate codec checking and initialization
......................................................................
Patch Set 9: Code-Review+1
(2 comments)
Patchset:
PS9:
Awesome!
File src/device/azalia_device.c:
https://review.coreboot.org/c/coreboot/+/80332/comment/bab64d18_71ce6223 :
PS5, Line 249: u32
> Yes, I agree this should be `size_t`. […]
Yeah, please do that in a separate patch.
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Hello Arthur Heymans, Felix Held, Felix Singer, Martin L Roth, Nico Huber, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80139?usp=email
to look at the new patch set (#3).
Change subject: util/crossgcc/buildgcc: Compile RISC-V GCC with medany
......................................................................
util/crossgcc/buildgcc: Compile RISC-V GCC with medany
currently the HiFive Unmatched mainboard produces the following error:
```
util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/rv64imafdc/lp64d/libgcc.a
(_clzsi2.o): in function `__clzdi2':
util/crossgcc/gcc-13.2.0/libgcc/libgcc2.c:690:(.text+0x1e): relocation
truncated to fit: R_RISCV_HI20 against symbol `__clz_tab' defined in
.rodata section in util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/
rv64imafdc/lp64d/libgcc.a(_clz.o)
```
This is due to the fact that the libgcc.a library is compiled with the
medlow code model but the mainboards are compiled with the medany code
model.
Changing the code model of the GCC libraries to the medany code model
fixes the issue.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: If5f07ce034686dd7fec160ea76838507c0ba7fa0
---
M util/crossgcc/buildgcc
1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/80139/3
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Change subject: device/pciexp_device: Use 'PCI_BASE_ADDRESS_x' macros
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Nice find!
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Change subject: device/pciexp_device: Use 'PCI_BASE_ADDRESS_x' macros
......................................................................
Patch Set 1: Code-Review+2
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