coreboot-gerrit February 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: Makefile.mk: Include build/dsdt.d at the same time as DEPENDENCIES
by Nico Huber (Code Review) 11 Feb '24

11 Feb '24

Attention is currently required from: Nicholas Chin. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80383?usp=email ) Change subject: Makefile.mk: Include build/dsdt.d at the same time as DEPENDENCIES ...................................................................... Patch Set 6: Code-Review+1 (1 comment) Patchset: PS6: The commit message doesn't seem to provide a reason. I'd argue that it's cleaner this way. -- To view, visit https://review.coreboot.org/c/coreboot/+/80383?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8271d1e172395917f2859c8bbfd2041ddc572ca Gerrit-Change-Number: 80383 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 11 Feb 2024 18:15:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
by Felix Singer (Code Review) 11 Feb '24

11 Feb '24

Attention is currently required from: Alexander Couzens, Nicholas Chin, Nicholas Sudsgaard, Nico Huber, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80343?usp=email ) Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake) ...................................................................... Patch Set 8: (14 comments) File src/mainboard/lenovo/thinkcentre_m710s/Kconfig: https://review.coreboot.org/c/coreboot/+/80343/comment/ee2ec00b_5230e6db : PS8, Line 7: select BOARD_ROMSIZE_KB_8192 : select SOC_INTEL_KABYLAKE : select SKYLAKE_SOC_PCH_H : select HAVE_ACPI_TABLES : select HAVE_ACPI_RESUME : select INTEL_GMA_HAVE_VBT : select MAINBOARD_HAS_LIBGFXINIT : select SOC_INTEL_COMMON_BLOCK_HDA_VERB : select SUPERIO_ITE_IT8629E : select MAINBOARD_HAS_TPM2 : s Sort alphabetically: ``` select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_TPM2 select MEMORY_MAPPED_TPM select SKYLAKE_SOC_PCH_H select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_KABYLAKE select SUPERIO_ITE_IT8629E ``` File src/mainboard/lenovo/thinkcentre_m710s/bootblock.c: https://review.coreboot.org/c/coreboot/+/80343/comment/7cd0955b_55c8c1f0 : PS8, Line 21: gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); FSP might reconfigure some GPIOs. So we only do necessary GPIO configuration in early stages and do the whole configuration in ramstage after FSP ran. See the Clevo mainboards for example. File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80343/comment/fba82b85_f49df147 : PS8, Line 2: # Model: IB250MH What does that mean? https://review.coreboot.org/c/coreboot/+/80343/comment/35374b1d_ef75c755 : PS8, Line 19: register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # USB30A : register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB30B : register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # F_USB30_1A : register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # F_USB30_1B : register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # F_USB30_2A : register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # F_USB30_2B : register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth : register "usb2_ports[7]" = "USB2_PORT_MID(OC5)" # USB_LANA : register "usb2_ports[8]" = "USB2_PORT_MID(OC5)" # USB_LANB : register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # F_USB1 (Pins 5, 7) : register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # F_USB1 (Pins 6, 8) : # Used by the SD/MMC reader. : Please use: ``` register "usb2_ports" = "{ [0] = ... # Comment }" ``` https://review.coreboot.org/c/coreboot/+/80343/comment/331b41b7_0ec6df2e : PS8, Line 33: register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB30A Same here https://review.coreboot.org/c/coreboot/+/80343/comment/bebc5679_6199074e : PS8, Line 45: register "SataPortsEnable[0]" = "true" # SATA1 Same here https://review.coreboot.org/c/coreboot/+/80343/comment/41b5c960_fddabc07 : PS8, Line 48: register "SataPortsEnable[3]" = "false" # SATA4 (not mounted) Did you test if it works? If not, please remove. https://review.coreboot.org/c/coreboot/+/80343/comment/1ea68353_13ed3a04 : PS8, Line 58: device ref pcie_rp6 off end # PCI (not mounted) Did you test if it works? If not, please remove. File src/mainboard/lenovo/thinkcentre_m710s/gpio.h: https://review.coreboot.org/c/coreboot/+/80343/comment/f348e8f8_546f1e3b : PS8, Line 27: PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), Nit: Missing description https://review.coreboot.org/c/coreboot/+/80343/comment/d4a9b719_839b4d81 : PS8, Line 50: PAD_CFG_GPO(GPP_B11, 0, DEEP), Nit: Missing description https://review.coreboot.org/c/coreboot/+/80343/comment/df99ba3c_4e92d8fd : PS8, Line 88: PAD_NC(GPP_C21, NONE), // UART2_TXD Does it have pads or headers for UART? Is RXD accessible as well? https://review.coreboot.org/c/coreboot/+/80343/comment/d0e57814_34a96d9c : PS8, Line 189: PAD_CFG_NF(GPP_H3, NONE, PLTRST, NF1), Nit: Missing description. https://review.coreboot.org/c/coreboot/+/80343/comment/3a9e5c8f_c1c3f41b : PS8, Line 208: PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI), Nit: Missing description File src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c: https://review.coreboot.org/c/coreboot/+/80343/comment/2a6e0420_5057d500 : PS8, Line 20: AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), Does it not have a pin config for a display port? -- To view, visit https://review.coreboot.org/c/coreboot/+/80343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Gerrit-Change-Number: 80343 Gerrit-PatchSet: 8 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 11 Feb 2024 17:38:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Makefile.mk: Include build/dsdt.d at the same time as DEPENDENCIES
by Nicholas Chin (Code Review) 11 Feb '24

11 Feb '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80383?usp=email to look at the new patch set (#6). Change subject: Makefile.mk: Include build/dsdt.d at the same time as DEPENDENCIES ...................................................................... Makefile.mk: Include build/dsdt.d at the same time as DEPENDENCIES Instead of including the dependency file generated in asl_template when the template is evaluated, add it to the DEPENDENCIES variable so that it is included at the same time as the rest of the .d files in the top level Makefile. This should be safe since asl_template is evaluated while calling includemakefiles, which is occurs before the files in DEPENDENCIES are included. TEST: 1. Build dell/e6400 2. Run `touch src/mainboard/dell/e6400/dsdt.asl` (defined as a prerequisite of build/dsdt.aml in build/dsdt.d) 3. Run `make --debug=b` 4. Verify that dsdt.aml was rebuilt due dsdt.asl being newer than target Change-Id: Ie8271d1e172395917f2859c8bbfd2041ddc572ca Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/80383/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/80383?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8271d1e172395917f2859c8bbfd2041ddc572ca Gerrit-Change-Number: 80383 Gerrit-PatchSet: 6 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
by Nicholas Sudsgaard (Code Review) 11 Feb '24

11 Feb '24

Attention is currently required from: Alexander Couzens, Nicholas Chin, Nico Huber, Paul Menzel. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80343?usp=email ) Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake) ...................................................................... Patch Set 8: (1 comment) File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80343/comment/b6e2417e_67aecae7 : PS5, Line 14: register "PcieRpClkSrcNumber[0]" = "0" > Sounds fine. But please leave a comment in the dt that we use the PcieRp* settings […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Gerrit-Change-Number: 80343 Gerrit-PatchSet: 8 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 11 Feb 2024 12:08:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: Documentation/mainboard/lenovo: Add ThinkCentre M710s
by Nicholas Sudsgaard (Code Review) 11 Feb '24

11 Feb '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80411?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s ...................................................................... Documentation/mainboard/lenovo: Add ThinkCentre M710s Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/ch341a_pinout.jpg A Documentation/mainboard/lenovo/thinkcentre_m710s.md A Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg 4 files changed, 209 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/80411/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/80411?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc Gerrit-Change-Number: 80411 Gerrit-PatchSet: 7 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
by Nicholas Sudsgaard (Code Review) 11 Feb '24

11 Feb '24

Attention is currently required from: Alexander Couzens, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel. Hello Alexander Couzens, Nico Huber, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80343?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake) ...................................................................... mainboard/lenovo: Add ThinkCentre M710s (Skylake) Working: - Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads: - SeaBIOS - TianoCore EDK 2 - Internal flashing - PEG - PCIe - SATA - M.2 SSD - M.2 WLAN (+ Bluetooth) - LAN - USB - Memory card reader - CPU fan - VGA (DP bridge) - Display ports - Audio (output) - COM1 - TPM Not Working: - SATA ACPI error - SuperIO related things - Power button LED - PCIe clock related things and AER issues (LiveCD) - Some drm issue when using EDK 2 and libgfxinit (LiveCD) - ME cleaner Untested: - Audio (input) Won't Test: - COM2 header - LPT header - PS/2 keyboard and mouse Thanks to Nico Huber and everyone else on the IRC for helping me write my first port! Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- A src/mainboard/lenovo/thinkcentre_m710s/Kconfig A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c A src/mainboard/lenovo/thinkcentre_m710s/data.vbt A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m710s/gpio.h A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c A src/mainboard/lenovo/thinkcentre_m710s/romstage.c 14 files changed, 604 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/80343/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/80343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Gerrit-Change-Number: 80343 Gerrit-PatchSet: 8 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
by Nico Huber (Code Review) 11 Feb '24

11 Feb '24

Attention is currently required from: Alexander Couzens, Nicholas Chin, Nicholas Sudsgaard, Paul Menzel. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80343?usp=email ) Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake) ...................................................................... Patch Set 7: (3 comments) File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80343/comment/037c66ce_4eb7cfa3 : PS5, Line 14: register "PcieRpClkSrcNumber[0]" = "0" > Since I don't have a x16 device, I tested it with a x1 device and it worked. […] Sounds fine. But please leave a comment in the dt that we use the PcieRp* settings because there is no equivalent for the PEG. https://review.coreboot.org/c/coreboot/+/80343/comment/c780ebfd_581e6d58 : PS5, Line 51: register "PcieRpClkReqSupport[4]" = "false" > If I remember correctly you suggested to disable it on the IRC when I was having issues with PCI err […] Acknowledged https://review.coreboot.org/c/coreboot/+/80343/comment/948b79cb_01649bef : PS5, Line 112: # Vendor values dumped using util/superiotool. > I was able to get better results figuring out which LDN was which if I looked at 7h of each LDN inst […] Actually, I don't get it. 7h is where pnp_set_logical_device() stores the number... Something probably went off in the dumping code. If this code works it works :) -- To view, visit https://review.coreboot.org/c/coreboot/+/80343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Gerrit-Change-Number: 80343 Gerrit-PatchSet: 7 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 11 Feb 2024 10:45:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
by Nicholas Sudsgaard (Code Review) 11 Feb '24

11 Feb '24

Attention is currently required from: Alexander Couzens, Nicholas Chin, Nico Huber, Paul Menzel. Hello Alexander Couzens, Nico Huber, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80343?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake) ...................................................................... mainboard/lenovo: Add ThinkCentre M710s (Skylake) Working: - Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads: - SeaBIOS - TianoCore EDK 2 - Internal flashing - PCIe - SATA - M.2 SSD - M.2 WLAN (+ Bluetooth) - LAN - USB - Memory card reader - CPU fan - VGA (DP bridge) - Display ports - Audio (output) - COM1 - TPM Not Working: - SATA ACPI error - SuperIO related things - Power button LED - PCIe clock related things and AER issues (LiveCD) - Some drm issue when using EDK 2 and libgfxinit (LiveCD) - ME cleaner Untested: - Audio (input) Won't Test: - COM2 header - LPT header - PS/2 keyboard and mouse Thanks to Nico Huber and everyone else on the IRC for helping me write my first port! Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- A src/mainboard/lenovo/thinkcentre_m710s/Kconfig A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c A src/mainboard/lenovo/thinkcentre_m710s/data.vbt A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads A src/mainboard/lenovo/thinkcentre_m710s/gpio.h A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c A src/mainboard/lenovo/thinkcentre_m710s/romstage.c 14 files changed, 601 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/80343/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/80343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Gerrit-Change-Number: 80343 Gerrit-PatchSet: 7 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: superio/ite: Add IT8629E
by Nicholas Sudsgaard (Code Review) 11 Feb '24

11 Feb '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80344?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: superio/ite: Add IT8629E ...................................................................... superio/ite: Add IT8629E Currently this is a copy-paste of IT8728F with an extra LDN (0x08). Change-Id: I44d0377da11f0e118017caa4357012df9373b322 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/superio/ite/Makefile.mk A src/superio/ite/it8629e/Kconfig A src/superio/ite/it8629e/Makefile.mk A src/superio/ite/it8629e/chip.h A src/superio/ite/it8629e/it8629e.h A src/superio/ite/it8629e/superio.c 6 files changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/80344/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/80344?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44d0377da11f0e118017caa4357012df9373b322 Gerrit-Change-Number: 80344 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: include/device/azalia.h: Correct values in AzaliaPinCfgLocationGross
by Nicholas Sudsgaard (Code Review) 11 Feb '24

11 Feb '24

Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80420?usp=email ) Change subject: include/device/azalia.h: Correct values in AzaliaPinCfgLocationGross ...................................................................... include/device/azalia.h: Correct values in AzaliaPinCfgLocationGross Change-Id: If1c458a678d1d165f1a25b94c016c0afdfde08d4 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M src/include/device/azalia.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/80420/1 diff --git a/src/include/device/azalia.h b/src/include/device/azalia.h index 24f91d9..67f69f3 100644 --- a/src/include/device/azalia.h +++ b/src/include/device/azalia.h @@ -19,10 +19,10 @@ }; enum AzaliaPinCfgLocationGross { - AZALIA_PINCFG_LOCATION_EXTERNAL = 0x00, - AZALIA_PINCFG_LOCATION_INTERNAL = 0x10, - AZALIA_PINCFG_LOCATION_EXT_CHASSIS = 0x20, - AZALIA_PINCFG_LOCATION_OTHER = 0x30, + AZALIA_PINCFG_LOCATION_EXTERNAL = 0x0, + AZALIA_PINCFG_LOCATION_INTERNAL = 0x1, + AZALIA_PINCFG_LOCATION_EXT_CHASSIS = 0x2, + AZALIA_PINCFG_LOCATION_OTHER = 0x3, }; enum AzaliaPinCfgLocationFine { -- To view, visit https://review.coreboot.org/c/coreboot/+/80420?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1c458a678d1d165f1a25b94c016c0afdfde08d4 Gerrit-Change-Number: 80420 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: newchange

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