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Change subject: arch/riscv/Makefile.inc: Fix OpenSBI compilation
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
need rebase
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79951?usp=email )
Change subject: drivers/uart/sifive.c: Fix divisor calculation
......................................................................
drivers/uart/sifive.c: Fix divisor calculation
The divisor is calculated using the following formula:
div = (frequency / baudrate) - 1;
The current implementation however essentially calculates:
div = (frequency / baudrate);
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I8a0898ce9016a70c0f91dc8a99fc1cf9e46d20c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79951
Reviewed-by: ron minnich <rminnich(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/drivers/uart/sifive.c
1 file changed, 10 insertions(+), 3 deletions(-)
Approvals:
ron minnich: Looks good to me, approved
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c
index d1b89dc..815a0cf 100644
--- a/src/drivers/uart/sifive.c
+++ b/src/drivers/uart/sifive.c
@@ -47,9 +47,16 @@
void uart_init(unsigned int idx)
{
- unsigned int div;
- div = uart_baudrate_divisor(get_uart_baudrate(),
- uart_platform_refclk(), uart_input_clock_divider());
+ /*
+ * according to FU540/FU740 manual:
+ * f_baud = f_in / (div + 1)
+ * <=>
+ * div = (f_in / f_baud) - 1
+ */
+ unsigned int div = uart_baudrate_divisor(get_uart_baudrate(), uart_platform_refclk(),
+ uart_input_clock_divider());
+ div -= 1;
+
sifive_uart_init(uart_platform_baseptr(idx), div);
}
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79949?usp=email )
Change subject: arch/riscv/boot.c: Comment OpenSBI Supervisor mode switch
......................................................................
arch/riscv/boot.c: Comment OpenSBI Supervisor mode switch
It simply adds a comment to indicate to the reader that the
RISCV_PAYLOAD_MODE_S parameter causes OpenSBI to switch to Supervisor
mode. Otherwise it could be interpreted that coreboot switches to
Supervisor mode before starting OpenSBI (which is not the case)
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: Ib62be0c2ff59361200df4c65f9aca5f7456a0ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79949
Reviewed-by: ron minnich <rminnich(a)gmail.com>
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---
M src/arch/riscv/boot.c
1 file changed, 4 insertions(+), 2 deletions(-)
Approvals:
ron minnich: Looks good to me, approved
Philipp Hug: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
index a59f9d1..6f744d3 100644
--- a/src/arch/riscv/boot.c
+++ b/src/arch/riscv/boot.c
@@ -31,10 +31,12 @@
fdt = prog_entry_arg(prog);
if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) {
- if (CONFIG(RISCV_OPENSBI))
+ if (CONFIG(RISCV_OPENSBI)) {
+ // tell OpenSBI to switch to Supervisor mode before jumping to payload
run_payload_opensbi(prog, fdt, args->opensbi, RISCV_PAYLOAD_MODE_S);
- else
+ } else {
run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S);
+ }
} else {
void (*doit)(int hart_id, void *fdt, void *arg) = prog_entry(prog);
doit(hart_id, fdt, prog_entry_arg(prog));
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Change subject: util/crossgcc/buildgcc: Compile RISC-V GCC with medany
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Fixed my build problem and let me build working image for unmatched.
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Change subject: arch/riscv/Makefile.inc: Fix OpenSBI compilation
......................................................................
Patch Set 3: Code-Review+2
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Change subject: drivers/uart/sifive.c: Fix divisor calculation
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS3:
nice catch.
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Change subject: arch/riscv/boot.c: Comment OpenSBI Supervisor mode switch
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/alderlake: Leverage IA common code for range calculations
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Patch Set 8: Code-Review+2
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