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Change subject: soc/amd/picasso: Use pcie_gpp_dxio_update_clk_req_config
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80413/comment/f3800c47_5bc65c79 :
PS2, Line 11: inline
in line
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Change subject: vc/amd/fsp/picasso: Bring picasso inline with other AMD SoC
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/80412/comment/a3d09a84_31872350 :
PS1, Line 59: CLK_ENABLE = 0xff,
> no, it exists to be used as a test for an invalid value in pcie_gpp_dxio_update_clk_req_config()
ok. from what i saw on the fsp side of things, this also seems to not cause any trouble, since the code does have a check for a maximum clock request line number which is lower than CLK_ENABLE
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Change subject: mb/google/brya/var/xol: Update DTT policy
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80410/comment/774fa299_ca9baa34 :
PS2, Line 9: Update initial DTT policy for Xol.
What is the source for the initial policy?
https://review.coreboot.org/c/coreboot/+/80410/comment/fc9e45f0_c765c52e :
PS2, Line 11: - Critical CPU temparature: 99
: - TCC offset: 94
Could be two commits:
1. Decrease critical CPU temperature from 105 to 99 °C
2. …
https://review.coreboot.org/c/coreboot/+/80410/comment/638dd86d_e48e2a4c :
PS2, Line 12: - TCC offset: 94
What is the default?
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Change subject: mb/amd/birman: Add Birmanplus board support for PHX1 SOC
......................................................................
Patch Set 2:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80353/comment/8225cbd7_0160882f :
PS2, Line 7: PHX1
What does the 1 refer to?
https://review.coreboot.org/c/coreboot/+/80353/comment/bbc6e82f_921a71f3 :
PS2, Line 7: Birmanplus
What is the official spelling?
https://review.coreboot.org/c/coreboot/+/80353/comment/84d23c29_0e670130 :
PS2, Line 9: 1)Initial commit for upstreaming Birmanplus mainboard changes.
What does the *plus* mean?
https://review.coreboot.org/c/coreboot/+/80353/comment/f756f8d0_72ff91d3 :
PS2, Line 9: 1)Initial commit for upstreaming Birmanplus mainboard changes.
: 2)Add the DXIO descriptors for Birmanplus mainboard.
Please add a space after the item “bullet”. Though reading the items, it’s not really an enumeration.
Patchset:
PS2:
t
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Change subject: mb/google/brox: Initialize TCHSCR_RST_L to 0
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80300/comment/00effadb_4ce058a4 :
PS4, Line 13:
> I do not understand what you are referring to. […]
Resolving for now. Will follow up if receive a response.
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Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
Patch Set 10:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80277/comment/8da6d2a2_ddade3ba :
PS2, Line 42:
> I am using this patch internally with internal platform and it boot fine. […]
Done
Patchset:
PS9:
I working on getting those patches verified on more platforms.
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/80277/comment/4654a154_ef0f4660 :
PS2, Line 62: Starting with FSP specification 2.4 they can be 64-bits.
> `they can be 64-bits` does not mean they cannot be 32-bits […]
Any feedback ? Does this still need clarification in your opinion ?
File src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h:
https://review.coreboot.org/c/coreboot/+/80277/comment/de50ae4f_658254cf :
PS2, Line 13: #include <efi/efi_datatype.h>
> Unfortunately, the order matter as soc_binding is in charge of defining EFIAPI appropriately. […]
Any feedback on the latest ?
File src/drivers/intel/fsp2_0/include/fsp/util.h:
https://review.coreboot.org/c/coreboot/+/80277/comment/05dbc9a4_346a280b :
PS9, Line 122: /* Helper function to print a message concatenated with the a FSP return status. */
> Can we print 64bits status for both 32bit and 64bit mode to simplify code? […]
Done
File src/drivers/intel/fsp2_0/memory_init.c:
https://review.coreboot.org/c/coreboot/+/80277/comment/266f61d3_0af997a4 :
PS7, Line 42:
> I also think we can simplify 16 byte align for both cases.
Done
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Hello Andrey Petrov, Martin L Roth, Ronak Kanabar, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: drivers/intel/fsp2_0: Default to 64-bits for FSP 2.4
......................................................................
drivers/intel/fsp2_0: Default to 64-bits for FSP 2.4
Sets`PLATFORM_USES_FSP2_X86_32' to `n' by default if FSP 2.4 is
enabled as 64-bits FSP should be norm moving forward.
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec98
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/fsp2_0/Kconfig
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/80323/7
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Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, Wonkyu Kim, build bot (Jenkins),
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Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
drivers/intel/fsp2_0: Support FSP 2.4 64-bits
FSP 2.4 brings FSP 64-bits support which requires some adjustments in
coreboot:
- Stack alignment:
1. FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
2. The FSP stack buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
- The EDK2 EFIAPI macro definition relies on compiler flags such as
__GNUC__ which is not working well when included by coreboot. While it
has no side-effect on i386 because the C calling convention used by
coreboot and FSP are the same, it breaks on x86_64 because FSP/UEFI
uses the Microsoft x64 calling convention while coreboot uses the
System V AMD64 ABI.
Fortunately, EDK2 header allows to override the EFIAPI
definition.
This appropriate attribute has to be set to all functions calling or
called by the FSP.
- Add fsp print helper macros to print `efi_return_status_t' with the
appropriate format
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/fsp2_0/debug.c
M src/drivers/intel/fsp2_0/fsp_debug_event.c
M src/drivers/intel/fsp2_0/include/fsp/debug.h
M src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/ppi/mp_service1.c
M src/drivers/intel/fsp2_0/ppi/mp_service2.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/util.c
M src/include/efi/efi_datatype.h
M src/soc/amd/common/fsp/fsp_reset.c
M src/soc/intel/common/fsp_reset.c
15 files changed, 93 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/80277/10
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