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Change subject: soc/amd/picasso: Use pcie_gpp_dxio_update_clk_req_config
......................................................................
soc/amd/picasso: Use pcie_gpp_dxio_update_clk_req_config
This function turns off gpp_clk for the devices which are disabled, and
adds the code to fix up the clock configuration depending on dxio
descriptors. Also this brings picasso inline with cezanne, mendocino
and phoenix. This also prepares picasso to use the common function
gpp_clk_setup_common.
Change-Id: Ice2e3a5a78359da9a438434c7d4aa1eca878d396
Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com>
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fch.c
3 files changed, 7 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/80413/2
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Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Varshit Pandya.
Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins),
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Code-Review+1 by Felix Held, Code-Review+1 by Fred Reitberger, Verified+1 by build bot (Jenkins)
Change subject: vc/amd/fsp/picasso: Bring picasso inline with other AMD SoC
......................................................................
vc/amd/fsp/picasso: Bring picasso inline with other AMD SoC
In preparation to using gpp_clk_setup_common for picasso, bring enum
defined in picasso more inline with other AMD SoC.
Change-Id: I9753acdff15921c84516ec873c925f36afdd2aa3
Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com>
---
M src/vendorcode/amd/fsp/picasso/platform_descriptors.h
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/80412/2
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd: Factor out gpp_clk_setup function
......................................................................
soc/amd: Factor out gpp_clk_setup function
gpp_clk_setup code in most AMD SoC is similar and it can moved to common
code. The only thing which is SoC dependent in this function is the SoC
config, hence keep it in SoC code and move everything else in new
gpp_clk_setup_common function which is in soc/amd/common. Picasso and
Glinda don't have pcie_gpp_dxio_update_clk_req_config fixup function so
they are addressed in later patches.
Change-Id: I7d7da4bfe079f07e31212247dbf3acd14daa6447
Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com>
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/fch.c
M src/soc/amd/cezanne/include/soc/southbridge.h
A src/soc/amd/common/block/gpp_clk/Kconfig
A src/soc/amd/common/block/gpp_clk/Makefile.mk
A src/soc/amd/common/block/gpp_clk/gpp_clk.c
M src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
M src/soc/amd/mendocino/Kconfig
M src/soc/amd/mendocino/fch.c
M src/soc/amd/mendocino/include/soc/southbridge.h
M src/soc/amd/phoenix/Kconfig
M src/soc/amd/phoenix/fch.c
M src/soc/amd/phoenix/include/soc/southbridge.h
13 files changed, 80 insertions(+), 160 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/80285/6
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80093?usp=email )
Change subject: soc/intel/xeon_sp: Locate PCU by PCI device ID
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/xeon_sp/skx/soc_util.c:
https://review.coreboot.org/c/coreboot/+/80093/comment/d25773f9_b07a3cf4 :
PS11, Line 115: #if ENV_RAMSTAGE
> Since xeon_sp/skx should be dropped anyway (see CB:80172) I don't want to invest to much time for th […]
ok, i'm fine with that then
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Change subject: cpu/x86/(sipi|smm): Pass on CR3 from ramstage
......................................................................
Patch Set 4:
(1 comment)
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/80335/comment/e66526a5_1be98944 :
PS4, Line 366: sp->cr3 = read_cr3();
> > i wonder if this is really needed to only be run depending on ENV_X86_64. […]
for consistency reasons i'd also read it in 32 bit mode and populate the struct element
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Hello build bot (Jenkins),
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Change subject: mb/google/brox: Update Verbtable for beep functionality
......................................................................
mb/google/brox: Update Verbtable for beep functionality
For boot beep functionality, relevant register values are
required to be updated.
BUG=b:324528901
BRANCH=None
TEST=Build Brox image
Change-Id: If236c8ac173a279db676af412377fa4e4122c1cd
Signed-off-by: poornima tom <poornima.tom(a)intel.com>
---
M src/mainboard/google/brox/hda_verb.c
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/80416/2
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Change subject: lint: Make lint work on Darwin
......................................................................
Patch Set 1: Code-Review+2
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Change subject: crossgcc: Add buildgcc support for Apple M1/M2 devices
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Patch Set 3: Code-Review+2
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