Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80316?usp=email )
Change subject: mb/google/nissa: Skip GPP_F15 GPIO locking to avoid IRQ storm
......................................................................
mb/google/nissa: Skip GPP_F15 GPIO locking to avoid IRQ storm
There is an existing issue for nissa where wake up from RTC wake is not working during suspend_stress_test.
The phenomenon of the issue is that after pulling out the stylus, can see an interrupt storm occurs, checking through:
"cat /proc/interrupts | grep acpi".
When the counter of interrupt is greater than a certain value, "Disabling IRQ #9" will occur, so RTC wake is not working.
Reference: https://review.coreboot.org/c/coreboot/+/65086
This patch skips the locking for GPP_F15 to allow kernel to
configure it later. The interrupt storm of acpi disappears.
BUG=b:321348117
TEST=1. cat /proc/interrupts | grep acpi
there isn't interrupt storm of acpi when pulling out stylus.
2. The stylus tools panel will pop up when pulling out it.
3. Inserts stylus can wakeup DUT after powerd_dbus_suspend.
4. Passed:
suspend_stress_test -c 2500 --suspend_min=15 --suspend_max=20
Change-Id: Ie143c43e0555d17d8a290f17637b537fba806144
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80316
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Kapil Porwal: Looks good to me, approved
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
index 5d83e7a..7f74256 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
@@ -238,7 +238,7 @@
/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT),
/* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */
- PAD_CFG_GPI_SCI_HIGH_LOCK(GPP_F15, NONE, EDGE_SINGLE, LOCK_CONFIG),
+ PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, PLTRST, EDGE_SINGLE),
/* F16 : NC */
PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
--
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Gerrit-Change-Number: 80316
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80259?usp=email )
Change subject: mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
......................................................................
mb/google/nissa/var/anraggar: Config DP AUX BIAS according to fw_config
EVT mini-build changes redriver IC from PS8745 to ANX7493, the ANX7493 not support DP AUX BIAS, so connects DP AUX BIAS of DB to SOC directly. Add DB_AUX_BIAS bit field to fw_config for compatibility.
BUG=b:320235566
TEST=DP function of MB and DB workable
Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80259
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/anraggar/overridetree.cb
M src/mainboard/google/brya/variants/anraggar/variant.c
2 files changed, 34 insertions(+), 15 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kapil Porwal: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
index 9646f29..0c584ee 100644
--- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb
@@ -10,6 +10,10 @@
option UF_720P 2
option UF_1080P_WF 3
end
+ field DB_AUX_BIAS 3 4
+ option REDRIVER 0
+ option SOC 1
+ end
end
chip soc/intel/alderlake
@@ -60,21 +64,6 @@
# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
- # SOC Aux orientation override:
- # This is a bitfield that corresponds to up to 4 TCSS ports.
- # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
- # TcssAuxOri = 0100b
- # Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
- # Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
- # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
- # motherboard to USBC connector
- register "tcss_aux_ori" = "4"
-
- register "typec_aux_bias_pads[0]" = "{
- .pad_auxp_dc = GPP_E22,
- .pad_auxn_dc = GPP_E23
- }"
-
# FIVR configurations for anraggar are disabled since the board doesn't have V1p05 and Vnn
# bypass rails implemented.
register "ext_fivr_settings" = "{
diff --git a/src/mainboard/google/brya/variants/anraggar/variant.c b/src/mainboard/google/brya/variants/anraggar/variant.c
index 4221a5b..0615618 100644
--- a/src/mainboard/google/brya/variants/anraggar/variant.c
+++ b/src/mainboard/google/brya/variants/anraggar/variant.c
@@ -1,9 +1,39 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <baseboard/variants.h>
+#include <chip.h>
#include <fw_config.h>
#include <sar.h>
+#include <soc/gpio_soc_defs.h>
const char *get_wifi_sar_cbfs_filename(void)
{
return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
}
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+ /*
+ * SOC Aux orientation override:
+ * This is a bitfield that corresponds to up to 4 TCSS ports.
+ * Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
+ * Bit0, Bit2 set to "0" indicates has retimer on TCSS Port.
+ * Bit0, Bit2 set to "1" indicates no retimer on TCSS Port.
+ * Bit1, Bit3 set to "0" indicates Aux lines are not swapped on TCSS Port.
+ * Bit1, Bit3 set to "1" indicates Aux lines are swapped on TCSS Port.
+ */
+
+ if (fw_config_probe(FW_CONFIG(DB_AUX_BIAS, SOC))) {
+ printk(BIOS_INFO, "DB DP AUX BIAS connect to SOC.\n");
+ config->tcss_aux_ori = 5;
+ config->typec_aux_bias_pads[0].pad_auxp_dc = GPP_A19;
+ config->typec_aux_bias_pads[0].pad_auxn_dc = GPP_A20;
+ config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_E22;
+ config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_E23;
+ } else {
+ printk(BIOS_INFO, "DB DP AUX BIAS connect to redriver IC.\n");
+ config->tcss_aux_ori = 4;
+ config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_E22;
+ config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_E23;
+ }
+}
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80374?usp=email )
Change subject: drivers/qemu: Drop redundant vga_io addition to ramstage
......................................................................
drivers/qemu: Drop redundant vga_io addition to ramstage
While introducing driver support for QEMU Cirrus display device, commit
7905f9254ebc ("qemu: cirrus native video init") also explicitly adds
VGA I/O functions into ramstage class when Bochs display driver support
is enabled.
Later, commit db7d04d1b753 ("qemu: Support textmode gfx init.") makes
the related config option select CONFIG_VGA, which also adds the same
file into ramstage class (among other things) in another Makefile.
Doing this twice is unnecessary. Remove the addition based on the Bochs
display driver's config option. Adding it based on CONFIG_VGA is
clearer, and future patches will try to support a Bochs display without
legacy VGA support on non-x86 architectures.
Change-Id: Ib31344e242689682d74d8a83c97b6e8027641926
Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80374
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/drivers/emulation/qemu/Makefile.mk
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, but someone else must approve
Arthur Heymans: Looks good to me, approved
diff --git a/src/drivers/emulation/qemu/Makefile.mk b/src/drivers/emulation/qemu/Makefile.mk
index 6f5ff3a..c9d94bd 100644
--- a/src/drivers/emulation/qemu/Makefile.mk
+++ b/src/drivers/emulation/qemu/Makefile.mk
@@ -7,4 +7,3 @@
ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += bochs.c
ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += cirrus.c
-ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += ../../pc80/vga/vga_io.c
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Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Michał Żygowski, Nico Huber.
Hello Angel Pons, Arthur Heymans, Felix Held, Kyösti Mälkki, Nico Huber, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/77338?usp=email
to look at the new patch set (#18).
The following approvals got outdated and were removed:
Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins)
Change subject: device/pciexp_device.c: Fix setting Max Payload Size
......................................................................
device/pciexp_device.c: Fix setting Max Payload Size
Current implementation assumes that the endpoint device is connected
directly to the PCIe Root Port, which does not always have to be true.
In a case where there is a PCIe switch between the endpoint and the
root port, the Max Payload Size capability may differ across the
devices in the chain and coreboot will not set a correct Max Payload
Size. This results in a PCIe device malfunction in pre-OS environment,
e.g. if the Ethernet NICs are connected behind a PCIe switch, the iPXE
fails to obtain the DHCP configuration.
Fix this by traversing the topology and programming the highest common
Max Payload Size in the given PCIe device chain during enumeration.
Once finished, the root port has the highest common Max Payload Size
supported by all the devices in the chain. So at the end of root port
bus scan, propagate the root port's Max Payload Size to all downstream
devices to keep Max Payload Size in sync within the whole chain.
TEST=Perform successful dhcp command in iPXE on the NIC connected to
the PCIe root port via ASMedia ASM1806 PCIe switch and again on the
NIC connected directly to the PCIe root port.
Change-Id: I24386dc208363b7d94fea46dec25c231a3968225
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/device/pciexp_device.c
1 file changed, 129 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77338/18
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Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80432?usp=email )
Change subject: util/ifdtool.c: Fix long_options platform has argument
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80432/comment/fc56d8a8_31ab4dd4 :
PS1, Line 9: Currently there is different behavior between using short and long
: option. Long option causes Segmentation fault.
:
I think it is safe just to say the flag `has_arg` was mistakingly set to `0` while the option apparently takes an argument (`:` in optstring and also the help text says so) and this patch fixes the undefined behaviour.
The exact behaviour could differ as the pointer to the argument might AFAIK become undefined when `has_arg` is set to `0`. Hence the segfaults.
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Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/80405?usp=email )
Change subject: soc/intel/cmn/graphics: Use DSM size for calculating GTT offset
......................................................................
Abandoned
just realize that overriding plane_surf from coreboot is causing blank display during AP FW boot. hence, we need to do this as late possible during boot. May be payloadd
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80328?usp=email )
Change subject: drivers/intel/fsp2_0: Add FSP_DOES_NOT_NEED_TEMP_RAM
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80328/comment/cf1fb22b_74f8d6fa :
PS1, Line 9: FSP allocates temporary ram in its reserved memory ranges
: instead of requesting coreboot to do the allocation. This
: is supported by some FSP implementations for Xeon SP.
> Are you sure that is what is going on? It's just using the default settings which avoid this heap be […]
I second this. If we used the defaults, we would still have to assert that
they are in a range compatible to the current coreboot state. Otherwise, we
would risk bugs when something in coreboot changes (within limits of the FSP
spec). Writing such checks is probably more work then setting correct values
in the first place. But I would have to see the memory map first to be able
to tell.
Patchset:
PS3:
I hope we are not stuck here. Shuo, if you could draw a small temp-ram memory
map that would be incredibly helpful. Doesn't have to be fancy, some ascii-art
in the style of [1] would be perfect. It could live in the Kconfig help text,
for instance. We need to get all in sync about what is going on to find a suitable
solution.
[1] soc/intel/common/block/systemagent/memmap.c
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