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Hello Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Tarun, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80275?usp=email
to look at the new patch set (#9).
The following approvals got outdated and were removed:
Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins)
Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
......................................................................
drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
Intel Firmware Support Package 2.4 specification (document 736809)
brings some significant changes compared to version 2.3 (document
644852):
1. It supports FSP-M multi-phase init. Some fields have been added to
the FSP header data structure for this purpose.
2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.
3. It support 64-bits FSP but 64-bits support will be provided by
subsequent patch.
Note that similarly to what is done for silicon initialization,
timestamps and post-codes are used during the memory initialization
multi-phase. However, since post-codes are in short supply, memory and
silicon multi-phase init share the same post-codes.
[736809]
https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf
[644852]
https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-…
TEST=verified on Lunar Lake RVP board (lnlrvp)
Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/upd_display.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/meteorlake/fsp_params.c
M src/soc/intel/tigerlake/fsp_params.c
M util/cbfstool/eventlog.c
13 files changed, 124 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80275/9
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80335?usp=email )
Change subject: cpu/x86/(sipi|smm): Pass on CR3 from ramstage
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/80335/comment/3a19fcbb_664ebc52 :
PS4, Line 366: sp->cr3 = read_cr3();
> for consistency reasons i'd also read it in 32 bit mode and populate the struct element
True, page tables can be used for other purposes, such as NX. But then the assembly code should also unconditionally set the CR3 register.
Currently, the code seems consistent with itself, but I don't have a strong preference here. Maybe it makes sense to always program the same CR3 onto the APs as the BSP.
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Change subject: soc/amd/picasso: Use pcie_gpp_dxio_update_clk_req_config
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/amd: Factor out gpp_clk_setup function
......................................................................
Patch Set 6: Code-Review+2
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Change subject: vc/amd/fsp/picasso: Bring picasso inline with other AMD SoC
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/80412/comment/f0ac2c36_4e14688e :
PS1, Line 59: CLK_ENABLE = 0xff,
> does the fsp support this value as input?
no, it exists to be used as a test for an invalid value in pcie_gpp_dxio_update_clk_req_config()
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Change subject: vc/amd/fsp/picasso: Bring picasso inline with other AMD SoC
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Patch Set 2: Code-Review+1
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Change subject: soc/amd/picasso: Use pcie_gpp_dxio_update_clk_req_config
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80413/comment/f9c89305_90a89350 :
PS1, Line 10: Also this brings picasso inline with cezanne, mendocino and phoenix.
> would be god to mention that this adds the code to fix up the clock configuration depending on the d […]
Done
https://review.coreboot.org/c/coreboot/+/80413/comment/de602003_da513b05 :
PS1, Line 12: coomon
> common
Done
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Change subject: vc/amd/fsp/picasso: Bring picasso inline with other AMD SoC
......................................................................
Patch Set 2:
(1 comment)
File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/80412/comment/1b420da5_1a56a6a6 :
PS1, Line 47: enum cpm_clk_req{
> nit: space before '{'
Done
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Change subject: soc/amd: Factor out gpp_clk_setup function
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80285/comment/913c2945_6d7ccc0a :
PS5, Line 10: code. The only thing which is SoC dependent in this function is the SoC
> maybe also mention that picasso and glinda don't have the call to the pcie_gpp_dxio_update_clk_req_c […]
Done
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Change subject: lint: Make lint work on Darwin
......................................................................
Patch Set 1:
(2 comments)
File util/lint/lint:
https://review.coreboot.org/c/coreboot/+/80436/comment/69330bd4_d1b02e79 :
PS1, Line 25: # Look if we have getopt. If not, build it.
Could you move these lines below junit_write()? Then the functions stay in line.
https://review.coreboot.org/c/coreboot/+/80436/comment/d40a95b5_318f91df :
PS1, Line 29: --
This seems wrong here. The double dash is still present below.
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