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Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80343/comment/b26ddf8a_841331f6 :
PS5, Line 112: # Vendor values dumped using util/superiotool.
> Did you push a superiotool patch yet? I'm still a little concerned about […]
I was able to get better results figuring out which LDN was which if I looked at 7h of each LDN instead of the `PNP_DEV()` value. I'm 95% sure these values are correct.
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Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
Patch Set 6:
(9 comments)
File src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/80343/comment/c43080ef_8af0c00a :
PS5, Line 6: ramstage-y += early_init.c
> This is not needed in ramstage.
Done
File src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80343/comment/a9928e55_3294707b :
PS5, Line 5: # FSP Configuration
> This is a remnant from times where we configured a lot of FSP directly at […]
Done
https://review.coreboot.org/c/coreboot/+/80343/comment/b42126bf_6b1f70e2 :
PS5, Line 14: register "PcieRpClkSrcNumber[0]" = "0"
> Did you test the x16 slot? Please mention that one explicitly in the […]
Since I don't have a x16 device, I tested it with a x1 device and it worked. I'm not sure about the `PcieRP*` settings I just saw something similar in `asrock/h110m`.
https://review.coreboot.org/c/coreboot/+/80343/comment/869eb793_55543ac8 :
PS5, Line 51: register "PcieRpClkReqSupport[4]" = "false"
> In the schematics it seems connected as CLKREQ_LAN#. If it's not working […]
If I remember correctly you suggested to disable it on the IRC when I was having issues with PCI errors when booting Ubuntu's LiveCD (doesn't seem to be an issue on "actual" systems).
Anyway, (I'm not sure how to test it but) it's not showing any issues in `dmesg` and seems to work fine with it enabled.
https://review.coreboot.org/c/coreboot/+/80343/comment/a7cb81e3_ae4b0054 :
PS5, Line 54: end
> I see a PCIe-PCI bridge in the schematics on `pcie_rp6`. […]
There's a spot allocated for that on the board but nothing is mounted.
You can see that on the image of the board in the documentation: https://review.coreboot.org/c/coreboot/+/80411/4/Documentation/mainboard/le….
I added it to make it easier for someone to port to another IB250MH board in the future.
File src/mainboard/lenovo/thinkcentre_m710s/early_init.c:
PS5:
> Please join this with `bootblock.c`. We usually have either one of them.
Done
File src/mainboard/lenovo/thinkcentre_m710s/gpio.h:
https://review.coreboot.org/c/coreboot/+/80343/comment/94439c46_70799efe :
PS5, Line 14: _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
> Technically the _-prefixed macros are reserved for internal use in […]
I updated it to the values `inteltool -iiii` generates. I also added the names of the GPIOs from the schematics.
File src/mainboard/lenovo/thinkcentre_m710s/romstage.c:
https://review.coreboot.org/c/coreboot/+/80343/comment/ba8b7cc3_8f10fad9 :
PS5, Line 11: 50
> First should be 60, for the 4 DIMM configuration.
Done
https://review.coreboot.org/c/coreboot/+/80343/comment/b84fe6ab_2d717f5b :
PS5, Line 32:
> No space after the casts, please.
Done
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Change subject: Documentation/mainboard/lenovo: Add ThinkCentre M710s
......................................................................
Documentation/mainboard/lenovo: Add ThinkCentre M710s
Change-Id: I90311257a28bd463712c4d43f8b83baa745509cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M Documentation/mainboard/index.md
A Documentation/mainboard/lenovo/ch341a_pinout.jpg
A Documentation/mainboard/lenovo/thinkcentre_m710s.md
A Documentation/mainboard/lenovo/thinkcentre_m710s_spi_location.jpg
4 files changed, 208 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/80411/5
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Hello Alexander Couzens, Nico Huber, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mainboard/lenovo: Add ThinkCentre M710s (Skylake)
......................................................................
mainboard/lenovo: Add ThinkCentre M710s (Skylake)
Working:
- Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads:
- SeaBIOS
- TianoCore EDK 2
- Internal flashing
- PCIe
- SATA
- M.2 SSD
- M.2 WLAN (+ Bluetooth)
- LAN
- USB
- Memory card reader
- CPU fan
- VGA (DP bridge)
- Display ports
- Audio (output)
- COM1
- TPM
Not Working:
- SATA ACPI error
- SuperIO related things
- Power button LED
- PCIe clock related things and AER issues (LiveCD)
- Some drm issue when using EDK 2 and libgfxinit (LiveCD)
- ME cleaner
Untested:
- Audio (input)
Won't Test:
- COM2 header
- LPT header
- PS/2 keyboard and mouse
Thanks to Nico Huber and everyone else on the IRC for helping me write
my first port!
Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig
A src/mainboard/lenovo/thinkcentre_m710s/Kconfig.name
A src/mainboard/lenovo/thinkcentre_m710s/Makefile.mk
A src/mainboard/lenovo/thinkcentre_m710s/acpi/ec.asl
A src/mainboard/lenovo/thinkcentre_m710s/acpi/superio.asl
A src/mainboard/lenovo/thinkcentre_m710s/board_info.txt
A src/mainboard/lenovo/thinkcentre_m710s/bootblock.c
A src/mainboard/lenovo/thinkcentre_m710s/data.vbt
A src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb
A src/mainboard/lenovo/thinkcentre_m710s/dsdt.asl
A src/mainboard/lenovo/thinkcentre_m710s/gma-mainboard.ads
A src/mainboard/lenovo/thinkcentre_m710s/gpio.h
A src/mainboard/lenovo/thinkcentre_m710s/hda_verb.c
A src/mainboard/lenovo/thinkcentre_m710s/romstage.c
14 files changed, 601 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/80343/6
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Change subject: util/intelmetool: Add Intel Union Point support
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS1:
> Running the program multiple times there are a few "hiccups". Sometimes it timeouts, sometimes […]
Looks good to me. Thanks!
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Change subject: ec/lenovo/h8/acpi: Support pulsing LEDLOGO on Haswell ThinkPads
......................................................................
Patch Set 5: Code-Review+2
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Change subject: util/crossgcc/buildgcc: Compile RISC-V GCC with medany
......................................................................
Patch Set 1:
(1 comment)
File util/crossgcc/buildgcc:
https://review.coreboot.org/c/coreboot/+/80139/comment/342bcb9a_7119e14b :
PS1, Line 779: CFLAGS_FOR_TARGET_EXTRA
Does this need to be restricted to GCC, or does something need to be done for CLANG?
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Change subject: [RFC] region: Introduce region_create() functions
......................................................................
Patch Set 6:
(1 comment)
File util/cbfstool/cbfstool.c:
https://review.coreboot.org/c/coreboot/+/79905/comment/701b9692_270a27e2 :
PS1, Line 334: if (region_create_untrusted(
> > They're parsed via `strtol()` so they already cannot overflow a `size_t`. […]
Was a bit too focused on the types with that answer. And sorry for
going grumpy.
We should also check the sum of those numbers Which isn't the case
at the moment, AFAICS?
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Change subject: ec/lenovo/h8/acpi: Support pulsing LEDLOGO on Haswell ThinkPads
......................................................................
Patch Set 5: Code-Review+2
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Change subject: mb/asus/p8z77-m: Support AC97 front audio panel
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/79734/comment/392de0e1_26b08335 :
PS2, Line 45: /*
: * The verbs above are for a HD Audio front panel.
: * With vendor firmware, if audio front panel type is set as AC97, line out 2
: * (0x1b) and mic 2 (0x19) pins of ALC887 are configured differently.
: *
: * The differences are all in the "Misc" fields of configuration defaults (in byte 2)
: * as shown below. ALC887 datasheet did not offer details on what those bits
: * (listed as reserved in HDA spec) are, so we'll have to take their word for it.
: *
: * Pin | 0x19 | 0x1b
: * -----+------+-----
: * HDA | 1100 | 1100
: * AC97 | 1001 | 0001
: */
I tried to see if there was anything in the Linux kernel that revealed what those reserved bits were being used for but couldn't find anything.
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