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Change subject: [UNTESTED]nb/intel/gm45: Use ssdt PCI root bridge generator
......................................................................
Patch Set 3:
(1 comment)
File src/northbridge/intel/gm45/northbridge.c:
https://review.coreboot.org/c/coreboot/+/80465/comment/c1449864_35bfa8aa :
PS3, Line 111: struct resource *upper_pci = find_resource(dev, IOINDEX_SUBTRACTIVE(2, 0));
: if (upper_pci)
: upper_pci->base = touud;
:
: struct resource *lower_pci = find_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
: if (lower_pci)
: lower_pci->base = tolud;
> +1
i'd also prefer to just report the correct resources.
unrelated to this patch, but the IOINDEX_SUBTRACTIVE macros should probably also have the link argument dropped
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Change subject: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
......................................................................
Patch Set 1:
(1 comment)
File src/acpi/Kconfig:
https://review.coreboot.org/c/coreboot/+/80464/comment/7eb17434_610eb7d8 :
PS1, Line 101: ACPI_PCI_ROOT_RESOURCE_PRODUCER
> hmm, it's probably not needed. […]
done. let's see if jenkins likes this new version; build-tested a mandolin and a x230 build to have at least both cases tested, so i guess that jenkins won't dislike this
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Hello Arthur Heymans, Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Patrick Rudolph, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80464?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins)
Change subject: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
......................................................................
soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
Even though it has an 'amd_' prefix, the amd_pci_domain_fill_ssdt
implementation doesn't contain any AMD-specific code and can also be
used by other SoCs. So factor it out, move the implementation to
src/acpi/acpigen_pci_root_resource_producer.c, and rename it to
pci_domain_fill_ssdt. When a SoC now assigns pci_domain_fill_ssdt to its
domain operation's acpi_fill_ssdt function pointer, the PCI domain
resource producer information will be added to the SSDT.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99
---
M src/acpi/Makefile.mk
A src/acpi/acpigen_pci_root_resource_producer.c
M src/include/acpi/acpigen_pci.h
M src/soc/amd/cezanne/chip.c
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/common/block/include/amdblocks/data_fabric.h
M src/soc/amd/genoa_poc/domain.c
M src/soc/amd/glinda/chip.c
M src/soc/amd/mendocino/chip.c
M src/soc/amd/phoenix/chip.c
M src/soc/amd/picasso/chip.c
11 files changed, 121 insertions(+), 107 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/80464/2
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Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80455?usp=email )
Change subject: drivers/pc80/tpm: Disable device if TPM not present
......................................................................
drivers/pc80/tpm: Disable device if TPM not present
If the TPM is not detected in the system it may mean it is inactive
due to enabled ME with active PTT. In such case, the chipset will route
the TPM traffic to PTT CRB TPM on Intel systems.
If TPM is not probed, disable the PC80 TPM device driver, so that
coreboot will not generate improper SSDT ACPI table.
Change-Id: I05972ad74a36abaafa2f17a16f09710550a3a3f3
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/drivers/pc80/tpm/tis.c
1 file changed, 8 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/80455/1
diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c
index 6b3bad3..0f0afbb 100644
--- a/src/drivers/pc80/tpm/tis.c
+++ b/src/drivers/pc80/tpm/tis.c
@@ -887,22 +887,20 @@
#endif
};
-static struct device_operations noop_tpm_ops = {
- .read_resources = noop_read_resources,
- .set_resources = noop_set_resources,
-};
-
static struct pnp_info pnp_dev_info[] = {
{ .flags = PNP_IRQ0 }
};
static void enable_dev(struct device *dev)
{
- if (CONFIG(TPM))
- pnp_enable_devices(dev, &lpc_tpm_ops,
- ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
- else
- pnp_enable_devices(dev, &noop_tpm_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+ enum tpm_family family;
+
+ if (pc80_tis_probe(&family) == NULL) {
+ dev->enabled = 0;
+ return;
+ }
+
+ pnp_enable_devices(dev, &lpc_tpm_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations drivers_pc80_tpm_ops = {
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Change subject: drivers/crb: Disable device if CRB TPM not present
......................................................................
drivers/crb: Disable device if CRB TPM not present
If CRB TPM is not detected in the system it may mean it is inactive
due to disabled or neutered ME. In such case, the chipset will route
the TPM traffic to LPC/SPI on Intel systems.
If CRB TPM is not probed, disable the CRB TPM device driver, so that
coreboot will not generate improper SMBIOS/SSDT ACPI tables.
Change-Id: Ie0928536d9042b1f680d585e1ca9ad2cadf0c8ef
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/drivers/crb/tis.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/80454/1
diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c
index 2176cc6..23cd55e 100644
--- a/src/drivers/crb/tis.c
+++ b/src/drivers/crb/tis.c
@@ -208,6 +208,13 @@
static void enable_dev(struct device *dev)
{
+ enum tpm_family family;
+
+ if (crb_tis_probe(&family) == NULL) {
+ dev->enabled = 0;
+ return;
+ }
+
#if !DEVTREE_EARLY
dev->ops = &crb_ops;
#endif
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Change subject: drivers/crb: Check for PTT before attempting to initialize CRB TPM
......................................................................
drivers/crb: Check for PTT before attempting to initialize CRB TPM
We can assume that platforms, which select HAVE_INTEL_PTT, will not
have any other CRB TPM than PTT. Check whether PTT is available before
forcefully initializing the TPM and selecting the CRB interface in the
TPM configuration registers.
Change-Id: If0ec6217b0e321b7d7a9410b70defde3c3195fc3
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/drivers/crb/tis.c
1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80453/1
diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c
index 32216b4..2176cc6 100644
--- a/src/drivers/crb/tis.c
+++ b/src/drivers/crb/tis.c
@@ -50,6 +50,14 @@
{
struct tpm2_info info;
+ if (CONFIG(HAVE_INTEL_PTT)) {
+ if (!ptt_active()) {
+ printk(BIOS_ERR, "%s: Intel PTT is not active.\n", __func__);
+ return NULL;
+ }
+ printk(BIOS_DEBUG, "%s: Intel PTT is active.\n", __func__);
+ }
+
/* Wake TPM up (if necessary) */
if (tpm2_init())
return NULL;
@@ -62,14 +70,6 @@
printk(BIOS_INFO, "Initialized TPM device %s revision %d\n", tis_get_dev_name(&info),
info.revision);
- if (CONFIG(HAVE_INTEL_PTT)) {
- if (!ptt_active()) {
- printk(BIOS_ERR, "%s: Intel PTT is not active.\n", __func__);
- return NULL;
- }
- printk(BIOS_DEBUG, "%s: Intel PTT is active.\n", __func__);
- }
-
return &crb_tpm_sendrecv;
}
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Change subject: soc/amd: move common pci_domain_fill_ssdt implementation to acpi/
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> I had a look at Intel client .asl code if that could be replaced with this code. […]
i think the oprom area didn't need to be a resource producer when i tested. but might be that that just worked fine on AMD silicon, since it uses the VFCT when using the iGPU. i don't think that adding the oprom area would break anything for the AMD code, so that could probably just be added. when you add that, please add me as a reviewer and i'll run a test on mandolin to make sure that this won't cause a regression. windows tends to be really picky about this
File src/acpi/Kconfig:
https://review.coreboot.org/c/coreboot/+/80464/comment/45feee21_f192b84b :
PS1, Line 101: ACPI_PCI_ROOT_RESOURCE_PRODUCER
> How about "acpi(gen)_domain_resources"?
hmm, it's probably not needed. let me push an updated version that adds this to the build unconditionally; the makefile already makes sure that it's only added for x86
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Change subject: security/tpm: resolve conflicts in TSS implementations
......................................................................
Patch Set 30:
(1 comment)
File src/security/tpm/tss/tss.c:
https://review.coreboot.org/c/coreboot/+/69160/comment/be507d9f_4ad9117f :
PS30, Line 17: tpm_result_t tlcl_lib_init(void)
This function could potentially be called multiple times (by tlcl_get_family) and cause to probe all TPM drivers.
I would add a static variable to ensure the TPM will be probed once per stage, e.g.:
```
tis_sendrecv_fn tlcl_tis_sendrecv;
+static int init_done = 0;
+
/* Probe for TPM device and choose implementation based on the returned TPM family. */
tpm_result_t tlcl_lib_init(void)
{
tis_probe_fn *tis_probe;
+ if (init_done)
+ return tlcl_tpm_family == TPM_UNKNOWN ? TPM_CB_NO_DEVICE : TPM_SUCCESS;
+
if (tlcl_tpm_family != TPM_UNKNOWN)
return TPM_SUCCESS;
@@ -28,8 +33,11 @@ tpm_result_t tlcl_lib_init(void)
break;
}
+ init_done = 1;
+
if (tlcl_tis_sendrecv == NULL) {
printk(BIOS_ERR, "%s: tis_probe failed\n", __func__);
+ tlcl_tpm_family = TPM_UNKNOWN;
return TPM_CB_NO_DEVICE;
}
```
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Change subject: device/pci_device.c: Avoid adding invalid resources
......................................................................
Patch Set 1: Code-Review+2
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Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
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Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Comment-Date: Tue, 13 Feb 2024 14:45:23 +0000
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