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Hello Boris Mittelberg, Caveh Jalali, Kapil Porwal, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: ec/google/chromeec: Add indexed IO support
......................................................................
ec/google/chromeec: Add indexed IO support
Add support for indexed IO for ec communication, Indexed I/O allows
memory access using a single I/O port base address usually called an
index register and another port address called a data register.
BUG=b:379224648
TEST= able to build nissa/trulo.
Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/ec/google/chromeec/Kconfig
M src/ec/google/chromeec/ec_lpc.c
2 files changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85449/6
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85712?usp=email )
Change subject: soc/intel/pantherlake: Add ACPI name for GSPI2
......................................................................
soc/intel/pantherlake: Add ACPI name for GSPI2
This change adds the ACPI name "SPI2" for the GSPI2 device
in the Panther Lake SOC.
Replace space with tab for PCI_DEVFN_GSPI2 macro.
w/o this patch:
[ERROR] Missing ACPI Name for PCI: 00:12.6
[ERROR] Missing ACPI Name for PCI: 00:12.6
w/ this patch:
No error
Change-Id: I404ddb893b82836e06d0f52a6d6f2aff2273d8c6
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/pantherlake/chip.c
M src/soc/intel/pantherlake/include/soc/pci_devs.h
2 files changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/85712/1
diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c
index 2c79fe7..5fe2a37 100644
--- a/src/soc/intel/pantherlake/chip.c
+++ b/src/soc/intel/pantherlake/chip.c
@@ -86,6 +86,7 @@
case PCI_DEVFN_NPU: return "NPU";
case PCI_DEVFN_IPU: return "IPU0";
case PCI_DEVFN_ISH: return "ISHB";
+ case PCI_DEVFN_GSPI2: return "SPI2";
case PCI_DEVFN_XHCI: return "XHCI";
case PCI_DEVFN_SRAM: return "SRAM";
case PCI_DEVFN_I2C0: return "I2C0";
diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h
index bff5bd3..5c74b6d 100644
--- a/src/soc/intel/pantherlake/include/soc/pci_devs.h
+++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h
@@ -95,7 +95,7 @@
#define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0)
#define PCI_DEVFN_P2SB2 _PCI_DEVFN(ISH, 1)
#define PCI_DEVFN_IEH_1 _PCI_DEVFN(ISH, 3)
-#define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6)
+#define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6)
#define PCI_DEV_ISH _PCI_DEV(ISH, 0)
#define PCI_DEV_P2SB2 _PCI_DEV(ISH, 1)
#define PCI_DEV_IEH_1 _PCI_DEV(ISH, 3)
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Change subject: mb/starlabs/starfighter: Correct USB port index
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Change subject: mb/starlabs/byte: Update the VBT to 251
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Change subject: soc/intel/mtl: Enable all bits for IO decode register
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Change subject: AB recovery: AB recovery is exclusive with VBOOT and ChromeOS
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85664/comment/1ce9cedb_1cc678fb?us… :
PS2, Line 8:
Could you please describe, why they are exclusive.
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Change subject: AB recovery: AB recovery is exclusive with VBOOT and ChromeOS
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85664/comment/49261075_bda9695b?us… :
PS2, Line 7: AB recovery is exclusive with VBOOT and ChromeOS
Please make the statement about the action, and not a problem/issue description.
https://review.coreboot.org/c/coreboot/+/85664/comment/2f56c591_15f0b96b?us… :
PS2, Line 7: AB recovery
soc/amd/cezanne
File src/soc/amd/cezanne/Kconfig:
https://review.coreboot.org/c/coreboot/+/85664/comment/fbac3856_e4e346a5?us… :
PS2, Line 414: select CBFS_VERIFICATION
Why do you select this?
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Change subject: mb/starlabs/starlite: Add smart battery variant
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Change subject: ec/starlabs/merlin: Add the option to reduce the LED brightness
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Change subject: mb/starlabs/*: Add a CMOS option to disable the GNA
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