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Change subject: mb/starlabs/starfighter: Enable TBT GPIOs
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Change subject: mb/starlabs/starfighter: Disable EC SCI and SMI GPIOs
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Dinesh Gehlot has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/85622?usp=email )
Change subject: commonlib: Refactor CSE sync eventLog
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85622/comment/e502857e_ef7f818f?us… :
PS2, Line 24: Post RAM CSE Sync
> is this hand edited ? […]
This is not a hand editing, but exact output with patch update#1". Will update the output with patch update#2 in description
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Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85717?usp=email )
Change subject: mb/google/rauru: Add support for getting storage id
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Patch Set 1:
(6 comments)
File src/mainboard/google/rauru/boardid.c:
https://review.coreboot.org/c/coreboot/+/85717/comment/aaa92057_9341ddd1?us… :
PS1, Line 14: SKU IDs
Storage ID
https://review.coreboot.org/c/coreboot/+/85717/comment/a8f5bcd7_12c5d19f?us… :
PS1, Line 61: printk(BIOS_DEBUG, "Storage ID: %#02x\n", cached_panel_id);
insert the blank line on above
https://review.coreboot.org/c/coreboot/+/85717/comment/8963a858_88e8ad81?us… :
PS1, Line 62:
remove this blank line
File src/mainboard/google/rauru/mainboard.c:
https://review.coreboot.org/c/coreboot/+/85717/comment/59599bd4_251d14ef?us… :
PS1, Line 14: #include <soc/mt6363_sdmadc.h>
remove ?
https://review.coreboot.org/c/coreboot/+/85717/comment/37da7354_bb4a8726?us… :
PS1, Line 63: mt6363_get_vtref18_voltage();
Remove `mt6363_get_vtref18_voltage`. It is not needed.
https://review.coreboot.org/c/coreboot/+/85717/comment/c331e64d_01309fbb?us… :
PS1, Line 60: mt6363_init_pmif_arb();
: mt6363_enable_vtref18(true);
: mt6363_set_vtref18_voltage(1800000);
: mt6363_get_vtref18_voltage();
Move to `romstage`. We will determine _PCIe initialization_ (for NVMe storage) by `storage_id` right after jumping into `ramstage` (in `enable_soc_dev()`).
It will be too late to power on `vtref18`.
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Change subject: mb/google/rauru: Add support for getting storage id
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Patch Set 1:
This change is ready for review.
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Change subject: mb/google/rauru: Implement SKU ID
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Patch Set 9:
This change is ready for review.
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Change subject: mb/google/brya: Adjust EC memory map range to support indexed IO
......................................................................
Patch Set 7:
(2 comments)
File src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/85547/comment/072eda0c_c3ecbf9f?us… :
PS3, Line 11: # EC memory map range is 0x900-0x9ff and indexed access is through 0x380
> Updated, Can you confirm based on the range is the programmed value correct ? Thanks!
Acknowledged
File src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/85547/comment/a4da5599_64db77c6?us… :
PS6, Line 15: (0x00010001 | CONFIG(EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO_PO
> I guess this will cause issue, `EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO_PORT` is a hex value
Acknowledged
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Hello Boris Mittelberg, Caveh Jalali, Kapil Porwal, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85449?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: ec/google/chromeec: Add indexed IO support
......................................................................
ec/google/chromeec: Add indexed IO support
Add support for indexed IO for ec communication, Indexed I/O allows
memory access using a single I/O port base address usually called an
index register and another port address called a data register.
BUG=b:379224648
TEST= able to build nissa/trulo.
Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/ec/google/chromeec/Kconfig
M src/ec/google/chromeec/ec_lpc.c
2 files changed, 41 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85449/6
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