coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Add doc reference for thunderbolt port number
by Jérémy Compostella (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85820?usp=email ) Change subject: soc/intel/meteorlake: Add doc reference for thunderbolt port number ...................................................................... soc/intel/meteorlake: Add doc reference for thunderbolt port number Document #640228 Meteor Lake - U/H and U Type4 Processor - 2.3 Device IDs - Table 8 "Other Device ID" IDs - Table 8 "Other Device ID" specifies that the first Thunderbolt PCIe root port number is 16. Change-Id: Ic394aa6795105ff613f30e8aa0ffa45500c6332a Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/meteorlake/pcie_rp.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/85820/1 diff --git a/src/soc/intel/meteorlake/pcie_rp.c b/src/soc/intel/meteorlake/pcie_rp.c index 7cfe3ed..7c47e3e 100644 --- a/src/soc/intel/meteorlake/pcie_rp.c +++ b/src/soc/intel/meteorlake/pcie_rp.c @@ -6,9 +6,11 @@ #include <soc/soc_info.h> /* - * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe - * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's - * PCIe remapping logic can return correct index (0-based) + * Document #640228 Meteor Lake - U/H and U Type4 Processor - 2.3 Device IDs - Table 8 "Other + * Device ID" specifies that the first Thunderbolt PCIe root port number is 16. TBT's LCAP + * registers return port index which starts from 16 (usually for other PCIe root ports index + * starts from 1). Thus, keeping lcap_port_base 16 for TBT, so that coreboot's PCIe remapping + * logic can return a correct index (0-based). */ static const struct pcie_rp_group tbt_rp_groups[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/85820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic394aa6795105ff613f30e8aa0ffa45500c6332a Gerrit-Change-Number: 85820 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21
by Jérémy Compostella (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85781?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Kapil Porwal, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21 ...................................................................... soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21 Document #815002 Panther Lake H Processor - 2.3 Device IDs - Table 8 "Other Device ID" specifies that the first Thunderbolt PCIe root port number is 21. The previous offset of 0x10, inherited from Meteor Lake code, caused an issue that resulted in: - Temporary deactivation of Thunderbolt PCI devices during ramstage - Failure to generate critical ACPI SSDT power management data for the port This error led to instability in PCIe tunneling during power state transitions. Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/pantherlake/pcie_rp.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/85781/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Gerrit-Change-Number: 85781 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: vendorcode/amd/opensil/genoa_poc/ramstage.c: Fix log typos
by Nick Kochlowski (Code Review) 31 Dec '24

31 Dec '24

Nick Kochlowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85819?usp=email ) Change subject: vendorcode/amd/opensil/genoa_poc/ramstage.c: Fix log typos ...................................................................... vendorcode/amd/opensil/genoa_poc/ramstage.c: Fix log typos Fix the typo in the word "unknown", and add 1 to the timepoint enum to print out 1, 2 and 3 instead of 0, 1 and 2. Change-Id: I1308fd102490a89ff8b724509917180034d8d0c0 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/vendorcode/amd/opensil/genoa_poc/ramstage.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/85819/1 diff --git a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c index b1bbc07..bb3cad1 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c @@ -18,7 +18,7 @@ void SIL_STATUS_report(const char *function, const int status) { const int log_level = status == SilPass ? BIOS_DEBUG : BIOS_ERR; - const char *error_string = "Unkown error"; + const char *error_string = "Unknown error"; const struct error_string_entry { SIL_STATUS status; @@ -151,7 +151,7 @@ return; } char opensil_function[16]; - snprintf(opensil_function, sizeof(opensil_function), "InitializeSiTp%d", tp); + snprintf(opensil_function, sizeof(opensil_function), "InitializeSiTp%d", tp + 1); SIL_STATUS_report(opensil_function, ret); if (ret == SilResetRequestColdImm || ret == SilResetRequestColdDef) { printk(BIOS_INFO, "openSIL requested a cold reset"); -- To view, visit https://review.coreboot.org/c/coreboot/+/85819?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1308fd102490a89ff8b724509917180034d8d0c0 Gerrit-Change-Number: 85819 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com>

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[L] Change in coreboot[main]: \mb/starlabs/starfighter: Put options in CFR cbtable
by Sean Rhodes (Code Review) 31 Dec '24

31 Dec '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85709?usp=email ) Change subject: \mb/starlabs/starfighter: Put options in CFR cbtable ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85709?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e3b5448282aa81a89356f1d3145381d65e47aaa Gerrit-Change-Number: 85709 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Dec 2024 16:57:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/starlabs/byte_adl: Put options in CFR cbtable
by Sean Rhodes (Code Review) 31 Dec '24

31 Dec '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85710?usp=email ) Change subject: mb/starlabs/byte_adl: Put options in CFR cbtable ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85710?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11349397e41fb2c7a3f26ab172a2c4b30d24bc0a Gerrit-Change-Number: 85710 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Dec 2024 16:57:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Nicholas Chin (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Angel Pons, Riku Viitanen. Nicholas Chin has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email ) Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... Patch Set 11: (1 comment) File src/mainboard/asrock/z77_extreme4/mainboard.c: https://review.coreboot.org/c/coreboot/+/85772/comment/b8df2ca0_f0a73321?us… : PS10, Line 5: #include <southbridge/intel/bd82x6x/pch.h> > Done Still seems to be there? -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 11 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 31 Dec 2024 16:42:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Riku Viitanen <riku.viitanen(a)protonmail.com> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in coreboot[main]: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode
by Nick Kochlowski (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier, Varshit Pandya. Hello Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85632?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode ...................................................................... drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode Refactor vendorcode MPIO configuration functions to be invoked from the openSIL driver. Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/drivers/amd/opensil/Makefile.mk A src/drivers/amd/opensil/mpio/Makefile.mk A src/drivers/amd/opensil/mpio/chip.c R src/drivers/amd/opensil/mpio/chip.h M src/drivers/amd/opensil/opensil.h M src/drivers/amd/opensil/ramstage.c M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb M src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c M src/mainboard/amd/onyx_poc/devicetree.cb M src/soc/amd/genoa_poc/chipset.cb M src/soc/amd/phoenix/chipset_opensil.cb M src/vendorcode/amd/opensil/Kconfig M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h M src/vendorcode/amd/opensil/genoa_poc/ramstage.c M src/vendorcode/amd/opensil/opensil.h M src/vendorcode/amd/opensil/stub/mpio/chip.c M src/vendorcode/amd/opensil/stub/mpio/chip.h 18 files changed, 202 insertions(+), 163 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/85632/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Gerrit-Change-Number: 85632 Gerrit-PatchSet: 11 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/google/brya/baseboard/trulo: Disable GPIO dynamic clock gating
by Yuval Peress (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Yuval Peress has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85818?usp=email ) Change subject: mb/google/brya/baseboard/trulo: Disable GPIO dynamic clock gating ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85818?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e853f12a0c78d8d179faba0cef4c99128296f2f Gerrit-Change-Number: 85818 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Yuval Peress <peress(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 31 Dec 2024 16:18:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/common/cnvi: Add _PRW for CNVi device
by Sean Rhodes (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Sean Rhodes. Hello Nicholas Sudsgaard, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84993?usp=email to look at the new patch set (#3). Change subject: soc/intel/common/cnvi: Add _PRW for CNVi device ...................................................................... soc/intel/common/cnvi: Add _PRW for CNVi device Add a _PRW to indicate that the device can wake the system in S3. This is required for Windows to correctly initialise USB Bluetooth. Change-Id: I8b3dcdf7b6cdc32fb910e7a4783029076717beff Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/84993/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84993?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b3dcdf7b6cdc32fb910e7a4783029076717beff Gerrit-Change-Number: 84993 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[S] Change in coreboot[main]: soc/intel/alderlake: Correctly set I2C SDA and SCL pins
by Sean Rhodes (Code Review) 31 Dec '24

31 Dec '24

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/83542?usp=email ) Change subject: soc/intel/alderlake: Correctly set I2C SDA and SCL pins ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/83542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8936012c40351f7b9577187b80dcd3818049cb2b Gerrit-Change-Number: 83542 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit December 2024