Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85139?usp=email )
(
5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
......................................................................
soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
On 1st and 2nd gen Xeon-SP the VTD PCI device has different PCI IDs,
depending if it's on the CSTACK or PSTACK.
Make sure to handle all VTD device on all stacks the same.
For later SoCs this was already the case since the PCI devices have
the same PCI ID.
Change-Id: I0d726b5ae620282dd4c9036d536e5e51d19a0a0b
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85139
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/gnr/Kconfig
M src/soc/intel/xeon_sp/spr/Kconfig
M src/soc/intel/xeon_sp/uncore.c
M src/soc/intel/xeon_sp/uncore_acpi.c
4 files changed, 34 insertions(+), 36 deletions(-)
Approvals:
build bot (Jenkins): Verified
Shuo Liu: Looks good to me, approved
Angel Pons: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/xeon_sp/gnr/Kconfig b/src/soc/intel/xeon_sp/gnr/Kconfig
index bc703b7..4dee961 100644
--- a/src/soc/intel/xeon_sp/gnr/Kconfig
+++ b/src/soc/intel/xeon_sp/gnr/Kconfig
@@ -105,9 +105,6 @@
config SOC_INTEL_HAS_NCMEM
def_bool y
-config SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
- def_bool y
-
config SOC_INTEL_HAS_CXL
def_bool n
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 6fad812..d6c9832 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -107,9 +107,6 @@
config SOC_INTEL_HAS_NCMEM
def_bool y
-config SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
- def_bool y
-
config CPU_BCLK_MHZ
int
default 100
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 93677b9..85e45db 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -56,7 +56,8 @@
size_t vtd_probe_bar_size(struct device *dev)
{
uint32_t id = pci_read_config32(dev, PCI_VENDOR_ID);
- assert(id == (PCI_VID_INTEL | (MMAP_VTD_CFG_REG_DEVID << 16)));
+ assert((id == (PCI_VID_INTEL | (MMAP_VTD_CFG_REG_DEVID << 16))) ||
+ (id == (PCI_VID_INTEL | (MMAP_VTD_STACK_CFG_REG_DEVID << 16))));
uint32_t val = pci_read_config32(dev, VTD_BAR_CSR);
pci_write_config32(dev, VTD_BAR_CSR, (uint32_t)(-4 * KiB));
@@ -432,6 +433,7 @@
static const unsigned short mmapvtd_ids[] = {
MMAP_VTD_CFG_REG_DEVID, /* Memory Map/Intel® VT-d Configuration Registers */
+ MMAP_VTD_STACK_CFG_REG_DEVID,
0
};
@@ -441,29 +443,6 @@
.devices = mmapvtd_ids
};
-#if !CONFIG(SOC_INTEL_MMAPVTD_ONLY_FOR_DPR)
-static void vtd_read_resources(struct device *dev)
-{
- pci_dev_read_resources(dev);
-
- configure_dpr(dev);
-}
-
-static struct device_operations vtd_ops = {
- .read_resources = vtd_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .ops_pci = &soc_pci_ops,
-};
-
-/* VTD devices on other stacks */
-static const struct pci_driver vtd_driver __pci_driver = {
- .ops = &vtd_ops,
- .vendor = PCI_VID_INTEL,
- .device = MMAP_VTD_STACK_CFG_REG_DEVID,
-};
-#endif
-
static void dmi3_init(struct device *dev)
{
if (CONFIG(INTEL_TXT) && skip_intel_txt_lockdown())
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index b64271e..8651944 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -365,6 +365,7 @@
static unsigned long acpi_create_atsr(unsigned long current)
{
+ struct device *domain = NULL;
struct device *child, *dev;
struct resource *resource;
@@ -381,8 +382,14 @@
unsigned long tmp = current;
bool first = true;
- dev = NULL;
- while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_CFG_REG_DEVID, dev))) {
+ /* Early Xeon-SP have different PCI IDs for the VTD device on CSTACK vs PSTACK.
+ * Iterate over PCI domains and then look for the VTD PCI device. */
+ while ((domain = dev_find_path(domain, DEVICE_PATH_DOMAIN))) {
+ dev = pcidev_path_behind(domain->downstream,
+ PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM));
+ assert(dev);
+ if (!dev)
+ continue;
/* Only add devices for the current socket */
if (iio_pci_domain_socket_from_dev(dev) != socket)
continue;
@@ -429,10 +436,18 @@
static unsigned long acpi_create_rhsa(unsigned long current)
{
- struct device *dev = NULL;
+ struct device *domain = NULL;
struct resource *resource;
+ struct device *dev;
- while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_CFG_REG_DEVID, dev))) {
+ /* Early Xeon-SP have different PCI IDs for the VTD device on CSTACK vs PSTACK.
+ * Iterate over PCI domains and then look for the VTD PCI device. */
+ while ((domain = dev_find_path(domain, DEVICE_PATH_DOMAIN))) {
+ dev = pcidev_path_behind(domain->downstream,
+ PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM));
+ assert(dev);
+ if (!dev)
+ continue;
/* See if there is a resource with the appropriate index. */
resource = probe_resource(dev, VTD_BAR_CSR);
if (!resource)
@@ -515,15 +530,25 @@
const IIO_UDS *hob = get_iio_uds();
// DRHD - iommu0 must be the last DRHD entry.
- struct device *dev = NULL;
+ struct device *domain = NULL;
struct device *iommu0 = NULL;
- while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_CFG_REG_DEVID, dev))) {
+ struct device *dev;
+
+ /* Early Xeon-SP have different PCI IDs for the VTD device on CSTACK vs PSTACK.
+ * Iterate over PCI domains and then look for the VTD PCI device. */
+ while ((domain = dev_find_path(domain, DEVICE_PATH_DOMAIN))) {
+ dev = pcidev_path_behind(domain->downstream,
+ PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM));
+ assert(dev);
+ if (!dev)
+ continue;
if (is_dev_on_domain0(dev)) {
iommu0 = dev;
continue;
}
current = acpi_create_drhd(current, dev, hob);
}
+
assert(iommu0);
current = acpi_create_drhd(current, iommu0, hob);
--
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Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85126?usp=email )
Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support
......................................................................
Patch Set 14:
(1 comment)
File src/soc/mediatek/mt8196/include/soc/pmif.h:
https://review.coreboot.org/c/coreboot/+/85126/comment/f7bc1659_bd206597?us… :
PS14, Line 114: OFFSET4
Please use a meaningful name. What's in offset4?
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Change subject: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
......................................................................
Patch Set 18:
(2 comments)
File src/soc/mediatek/common/mt6363_sdmadc.c:
https://review.coreboot.org/c/coreboot/+/85128/comment/5d018552_f2d51903?us… :
PS17, Line 62: "Wrong array size for mt6363_sdmadc_chan_specs");
> > `code indent should use tabs where possible` […]
Done
https://review.coreboot.org/c/coreboot/+/85128/comment/4880d03e_95ad8e5d?us… :
PS17, Line 62: "Wrong array size for mt6363_sdmadc_chan_specs");
> > `please, no spaces at the start of a line` […]
Done
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Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85127?usp=email
to look at the new patch set (#17).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: soc/mediatek/mt8196: Add PMIC MT6363 driver
......................................................................
soc/mediatek/mt8196: Add PMIC MT6363 driver
1. Add MT6363 driver in SoC folder
2. Add vtref18 set/get api
3. Add MT6363 LDO/BUCK enable api
4. Add pmif_arb for MT6363
TEST=build pass
BUG=b:317009620
Change-Id: Iaf493b802522deba575d98c2ed69a93e94ce3d4e
Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com>
---
A src/soc/mediatek/common/include/soc/mt6363.h
A src/soc/mediatek/common/mt6363.c
M src/soc/mediatek/mt8196/Makefile.mk
A src/soc/mediatek/mt8196/mt6363.c
4 files changed, 783 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/85127/17
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Change subject: soc/mediatek/mt8196: Add PMIC MT6363 driver
......................................................................
Patch Set 16:
(5 comments)
File src/soc/mediatek/common/include/soc/mt6363.h:
https://review.coreboot.org/c/coreboot/+/85127/comment/182b42ef_0a0821c6?us… :
PS13, Line 114: pmic_lp_setting
> remove this if not implemented
Done
File src/soc/mediatek/common/mt6363.c:
https://review.coreboot.org/c/coreboot/+/85127/comment/e7f198f3_2d0ee267?us… :
PS13, Line 29: write
> `write8` (because there might be `write16` in the future)
Done
https://review.coreboot.org/c/coreboot/+/85127/comment/d391b3f8_484cd447?us… :
PS13, Line 29: u32
> `u8` (because the write function calls `pmif_send_cmd` with `len = 1` in src/soc/mediatek/common/pmi […]
Done
File src/soc/mediatek/mt8196/mt6363.c:
https://review.coreboot.org/c/coreboot/+/85127/comment/61923299_f23396d9?us… :
PS7, Line 13: 0
> I meant to remove the `shift` field from the `pmic_setting` struct in the header file.
Done
File src/soc/mediatek/mt8196/mt6363.c:
https://review.coreboot.org/c/coreboot/+/85127/comment/765bb9c1_88c401a6?us… :
PS13, Line 385: /* TODO: Disable unused modem power in a separate function and
> Wrong format. […]
Done
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