coreboot-gerrit December 2024

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[S] Change in coreboot[main]: soc/intel/xeon_sp/cpx: Add missing FADT fields
by Patrick Rudolph (Code Review) 05 Dec '24

05 Dec '24

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp/skx: Drop ACPI_FADT_8042
by Patrick Rudolph (Code Review) 05 Dec '24

05 Dec '24

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Use generate_p_state_entries
by Patrick Rudolph (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85506?usp=email ) Change subject: soc/intel/xeon_sp: Use generate_p_state_entries ...................................................................... soc/intel/xeon_sp: Use generate_p_state_entries Both CPX and SKX always enable EIST, thus the generic generate_p_state_entries() method can be used to generate _PSS. This also reduces code differences between skx and cpx and allows to merge both codebases into one. Change-Id: Ic7b03eef9498f2c442745119b24fb8b5c6169a08 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c 2 files changed, 4 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85506/1 diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 58e67fc..c7edb22 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -40,108 +40,7 @@ fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE); } -/* TODO: See if we can use the common generate_p_state_entries */ -void soc_power_states_generation(int core, int cores_per_package) +void soc_power_states_generation(int core_id, int cores_per_package) { - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; - if (num_entries > PSS_MAX_ENTRIES) { - ratio_step += 1; - num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /* MHz */ - power_max, /* mW */ - PSS_LATENCY_TRANSITION, /* lat1 */ - PSS_LATENCY_BUSMASTER, /* lat2 */ - ratio_turbo << 8, /* control */ - ratio_turbo << 8); /* status */ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /* MHz */ - power_max, /* mW */ - PSS_LATENCY_TRANSITION, /* lat1 */ - PSS_LATENCY_BUSMASTER, /* lat2 */ - ratio_max << 8, /* control */ - ratio_max << 8); /* status */ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - /* Calculate power at this ratio */ - power = common_calculate_power_ratio(power_max, ratio_max, ratio); - clock = ratio * CONFIG_CPU_BCLK_MHZ; - //clock = 1; - acpigen_write_PSS_package( - clock, /* MHz */ - power, /* mW */ - PSS_LATENCY_TRANSITION, /* lat1 */ - PSS_LATENCY_BUSMASTER, /* lat2 */ - ratio << 8, /* control */ - ratio << 8); /* status */ - } - - /* Fix package length */ - acpigen_pop_len(); + generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 541dd67..c9d867c 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -53,6 +53,7 @@ fill_fadt_extended_pm_io(fadt); } -void soc_power_states_generation(int core, int cores_per_package) +void soc_power_states_generation(int core_id, int cores_per_package) { + generate_p_state_entries(core_id, cores_per_package); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7b03eef9498f2c442745119b24fb8b5c6169a08 Gerrit-Change-Number: 85506 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Introduce early_pch_init
by Patrick Rudolph (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85505?usp=email ) Change subject: soc/intel/xeon_sp: Introduce early_pch_init ...................................................................... soc/intel/xeon_sp: Introduce early_pch_init Stop using platform_fsp_memory_init_params_cb() as SoC specific romstage hook and introduce early_pch_init() to do PCH init in romstage before FSP-M runs. Move PCH specific code into early_pch_init and call it from common code. Change-Id: Id31a2018f5820098e83782b19a1672d2e35bdb83 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/ebg/soc_pch.c M src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h M src/soc/intel/xeon_sp/ibl/soc_pch.c M src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/lbg/soc_pch.c M src/soc/intel/xeon_sp/romstage.c M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 10 files changed, 29 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85505/1 diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 82657f9..25dc4f6 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -10,7 +10,6 @@ #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/intel/common/smbios.h> -#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> #include <string.h> @@ -108,10 +107,6 @@ /* Adjust the "cold boot required" flag in CMOS. */ soc_set_mrc_cold_boot_flag(!mupd->FspmArchUpd.NvsBufferPtr); - - /* FSP has no UPD to disable HDA, so do it manually here... */ - if (!is_devfn_enabled(PCH_DEVFN_HDA)) - pch_disable_hda(); } uint32_t get_max_capacity_mib(void) diff --git a/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h index acb1785..2b5ed25 100644 --- a/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h @@ -3,7 +3,8 @@ #ifndef _SOC_SOC_PCH_H_ #define _SOC_SOC_PCH_H_ +void early_pch_init(void); + void pch_lock_dmictl(void); -void pch_disable_hda(void); #endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/ebg/soc_pch.c b/src/soc/intel/xeon_sp/ebg/soc_pch.c index a40af7a..3d50fc3 100644 --- a/src/soc/intel/xeon_sp/ebg/soc_pch.c +++ b/src/soc/intel/xeon_sp/ebg/soc_pch.c @@ -10,6 +10,7 @@ #include <soc/azalia_device.h> #include <soc/bootblock.h> #include <soc/soc_pch.h> +#include <soc/pch_pci_devs.h> #include <soc/pch.h> #include <soc/pmc.h> #include <console/console.h> @@ -67,7 +68,7 @@ #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) #define PSF3_HDA_BASE_ADDRESS 0x280 -void pch_disable_hda(void) +static void pch_disable_hda(void) { /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(PCH_DEV_HDA, PCI_COMMAND, ~(PCI_COMMAND_MASTER | @@ -82,3 +83,10 @@ printk(BIOS_INFO, "%s: Disabled HDA device 00:1f.3\n", __func__); } + +void early_pch_init(void) +{ + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); +} \ No newline at end of file diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h index acb1785..00f0a1b 100644 --- a/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h @@ -3,7 +3,7 @@ #ifndef _SOC_SOC_PCH_H_ #define _SOC_SOC_PCH_H_ +void early_pch_init(void); void pch_lock_dmictl(void); -void pch_disable_hda(void); #endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/ibl/soc_pch.c b/src/soc/intel/xeon_sp/ibl/soc_pch.c index 6bfa749..2bb247c 100644 --- a/src/soc/intel/xeon_sp/ibl/soc_pch.c +++ b/src/soc/intel/xeon_sp/ibl/soc_pch.c @@ -44,3 +44,7 @@ */ soc_config_acpibase(); } + +void early_pch_init(void) +{ +} \ No newline at end of file diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h index acb1785..2b5ed25 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h @@ -3,7 +3,8 @@ #ifndef _SOC_SOC_PCH_H_ #define _SOC_SOC_PCH_H_ +void early_pch_init(void); + void pch_lock_dmictl(void); -void pch_disable_hda(void); #endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/lbg/soc_pch.c b/src/soc/intel/xeon_sp/lbg/soc_pch.c index 8bc01f7..2eacb4f 100644 --- a/src/soc/intel/xeon_sp/lbg/soc_pch.c +++ b/src/soc/intel/xeon_sp/lbg/soc_pch.c @@ -64,7 +64,7 @@ #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) #define PSF3_HDA_BASE_ADDRESS 0x1800 -void pch_disable_hda(void) +static void pch_disable_hda(void) { /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(PCH_DEV_HDA, PCI_COMMAND, ~(PCI_COMMAND_MASTER | @@ -82,3 +82,10 @@ printk(BIOS_INFO, "%s: Disabled HDA device 00:1f.3\n", __func__); } + +void early_pch_init(void) +{ + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); +} \ No newline at end of file diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 30bbad7..024dfa5 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -8,11 +8,14 @@ #include <soc/ddr.h> #include <soc/intel/common/smbios.h> #include <soc/romstage.h> +#include <soc/soc_pch.h> #include <soc/util.h> #include <spd.h> void mainboard_romstage_entry(void) { + early_pch_init(); + rtc_init(); if (soc_get_rtc_failed()) mainboard_rtc_failed(); diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index 819fcc8..f5a4294 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -1,11 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/romstage.h> -#include <device/pci_def.h> #include <intelblocks/rtc.h> #include <soc/romstage.h> -#include <soc/pch_pci_devs.h> -#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> #include "chip.h" @@ -26,10 +23,6 @@ m_cfg->VTdConfig.VTdSupport = config->vtd_support; m_cfg->VTdConfig.CoherencySupport = config->coherency_support; m_cfg->VTdConfig.ATS = config->ats_support; - - /* FSP has no UPD to disable HDA, so do it manually here... */ - if (!is_devfn_enabled(PCH_DEVFN_HDA)) - pch_disable_hda(); } uint8_t get_error_correction_type(const uint8_t RasModesEnabled) diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 4438a59..43eb187 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -17,7 +17,6 @@ #include <soc/chip_common.h> #include <soc/romstage.h> #include <soc/pci_devs.h> -#include <soc/soc_pch.h> #include <static.h> #include <string.h> #include <soc/config.h> @@ -245,10 +244,6 @@ } if (CONFIG(MEM_POR_FREQ)) mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; - - /* SPR-FSP has no UPD to disable HDA, so do it manually here... */ - if (!is_devfn_enabled(PCH_DEVFN_HDA)) - pch_disable_hda(); } uint8_t get_error_correction_type(const uint8_t RasModesEnabled) -- To view, visit https://review.coreboot.org/c/coreboot/+/85505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id31a2018f5820098e83782b19a1672d2e35bdb83 Gerrit-Change-Number: 85505 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists
by Patrick Rudolph (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Angel Pons, Johnny Lin, Morgan Jang, Patrick Rudolph. Hello Angel Pons, Johnny Lin, Morgan Jang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85318?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+2 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists ...................................................................... mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists The board has 24 slots for DDR4 ECC RDIMMs and it has 2 CPU sockets, where each is connected to 12 DIMMs. Every socket supports up to 6 channels, thus every channel is connected to 2 DIMMs. Implement mainboard_dimm_slot_exists accordingly to advertise all slots as SMBIOS type 17. TEST: Found all installed DIMMs advertised through SMBIOS on ocp/tiogapass. Change-Id: I31cb4a89aa11258ac04eb69a0e9c86f258280484 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ocp/tiogapass/romstage.c 1 file changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/85318/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31cb4a89aa11258ac04eb69a0e9c86f258280484 Gerrit-Change-Number: 85318 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6363 driver
by Jarried Lin (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85127?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6363 driver ...................................................................... Patch Set 18: (2 comments) File src/soc/mediatek/common/include/soc/mt6363.h: https://review.coreboot.org/c/coreboot/+/85127/comment/3e451734_9463c46b?us… : PS17, Line 111: void mt6363_write_field(u32 reg, u32 val, u32 mask, u32 shift); > Move after write8. Done File src/soc/mediatek/common/mt6363.c: https://review.coreboot.org/c/coreboot/+/85127/comment/e0ee2a0b_263b4223?us… : PS17, Line 38: reg_val > data Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf493b802522deba575d98c2ed69a93e94ce3d4e Gerrit-Change-Number: 85127 Gerrit-PatchSet: 18 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 05 Dec 2024 07:48:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6363 driver
by Jarried Lin (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85127?usp=email to look at the new patch set (#18). Change subject: soc/mediatek/mt8196: Add PMIC MT6363 driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6363 driver 1. Add MT6363 driver in SoC folder 2. Add vtref18 set/get api 3. Add MT6363 LDO/BUCK enable api 4. Add pmif_arb for MT6363 TEST=build pass BUG=b:317009620 Change-Id: Iaf493b802522deba575d98c2ed69a93e94ce3d4e Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6363.h A src/soc/mediatek/common/mt6363.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6363.c 4 files changed, 783 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/85127/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/85127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf493b802522deba575d98c2ed69a93e94ce3d4e Gerrit-Change-Number: 85127 Gerrit-PatchSet: 18 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well
by Patrick Rudolph (Code Review) 05 Dec '24

05 Dec '24

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85319?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well ...................................................................... soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well Add the MEMMAP_DIMM_DEVICE_INFO_STRUCT for skylake_sp and let common code fill in the SMBIOS type 17 entries for all slots and found DIMMs. This also allows to build dimm.c unconditionally on all xeon_sp socs. Test: On ocp/tiogapass all DIMMs and slots are visible in SMBIOS. Change-Id: I686b1e3ef946240785111f86a5f23a109a6a52ad Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85319 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/cpx/Makefile.mk M src/soc/intel/xeon_sp/gnr/Makefile.mk M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/spr/Makefile.mk M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h 6 files changed, 73 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index 0fc32d8..c66b8ad 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -10,6 +10,7 @@ bootblock-y += bootblock.c spi.c lpc.c pch.c report_platform.c romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c romstage-y += config.c +romstage-y += dimm.c romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c ramstage-y += memmap.c pch.c lockdown.c finalize.c diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk index a24b50e..b54b0ef 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.mk +++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk @@ -6,7 +6,6 @@ subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c soc_util.c -romstage-y += ../dimm.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c diff --git a/src/soc/intel/xeon_sp/gnr/Makefile.mk b/src/soc/intel/xeon_sp/gnr/Makefile.mk index 9b07408..054d513 100644 --- a/src/soc/intel/xeon_sp/gnr/Makefile.mk +++ b/src/soc/intel/xeon_sp/gnr/Makefile.mk @@ -12,7 +12,6 @@ romstage-y += romstage.c romstage-y += soc_util.c romstage-y += soc_iio.c -romstage-y += ../dimm.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += chip.c diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index 21b3522..f66022d 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -26,4 +26,37 @@ m_cfg->VTdConfig.ATS = config->ats_support; } -void save_dimm_info(void) {} +uint8_t get_error_correction_type(const uint8_t RasModesEnabled) +{ + switch (RasModesEnabled) { + case CH_INDEPENDENT: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case FULL_MIRROR_1LM: + case PARTIAL_MIRROR_1LM: + case FULL_MIRROR_2LM: + case PARTIAL_MIRROR_2LM: + return MEMORY_ARRAY_ECC_MULTI_BIT; + case RK_SPARE: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + case CH_LOCKSTEP: + return MEMORY_ARRAY_ECC_SINGLE_BIT; + default: + return MEMORY_ARRAY_ECC_MULTI_BIT; + } +} + +uint32_t get_max_capacity_mib(void) +{ + /* According to Dear Customer Letter it's 1.12 TB per processor. */ + return 1.12 * MiB * CONFIG_MAX_SOCKET; +} + +uint8_t get_max_dimm_count(void) +{ + return MAX_DIMM; +} + +uint8_t get_dram_type(const struct SystemMemoryMapHob *hob) +{ + return MEMORY_TYPE_DDR4; +} diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk index c5f9ece..f1755e4 100644 --- a/src/soc/intel/xeon_sp/spr/Makefile.mk +++ b/src/soc/intel/xeon_sp/spr/Makefile.mk @@ -9,7 +9,6 @@ subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c soc_util.c -romstage-y += ../dimm.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h index f97056a..5a1b2f2 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h @@ -36,6 +36,15 @@ 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \ } +#define CH_INDEPENDENT 0 +#define FULL_MIRROR_1LM BIT0 +#define FULL_MIRROR_2LM BIT1 +#define CH_LOCKSTEP BIT2 +#define RK_SPARE BIT3 +#define PARTIAL_MIRROR_1LM BIT5 +#define PARTIAL_MIRROR_2LM BIT6 +#define STAT_VIRT_LOCKSTEP BIT7 + #define MEMTYPE_1LM_MASK (1 << 0) #define MEMTYPE_2LM_MASK (1 << 1) #define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) @@ -50,6 +59,34 @@ #pragma pack(1) +typedef struct DimmDevice { + UINT8 Present; + UINT8 reserved1[3]; + UINT8 NumRanks; + UINT8 reserved2[1]; + UINT8 actKeyByte2; + UINT8 reserved3[9]; + UINT16 DimmSize; + UINT8 reserved4[8]; + UINT16 VendorID; + UINT16 DeviceID; + UINT8 reserved5[24]; + UINT8 serialNumber[4]; + UINT8 PartNumber[4]; + UINT8 reserved6[50]; + INT32 commonTck; + UINT8 reserved7[24]; +} MEMMAP_DIMM_DEVICE_INFO_STRUCT; + +struct ChannelDevice { + UINT8 reserved1[191]; + MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_IMC]; +}; +typedef struct socket { + UINT8 reserved[2075]; + struct ChannelDevice ChannelInfo[MAX_CH]; +} MEMMAP_SOCKET; + struct SystemMemoryMapElement { UINT8 NodeId; // Node ID of the HA Owning the memory UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA @@ -98,7 +135,7 @@ UINT8 maxCh; struct SystemMemoryMapElement Element[MAX_SOCKET * SAD_RULES]; UINT8 reserved1[982]; - UINT8 reserved2[4901*MAX_SOCKET]; + MEMMAP_SOCKET Socket[MAX_SOCKET]; UINT8 reserved3[707]; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/85319?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I686b1e3ef946240785111f86a5f23a109a6a52ad Gerrit-Change-Number: 85319 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add PCU PCI drivers
by Patrick Rudolph (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85316?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/xeon_sp: Add PCU PCI drivers ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Depends on https://review.coreboot.org/c/coreboot/+/85439/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573 Gerrit-Change-Number: 85316 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 05 Dec 2024 07:39:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Fix debug print
by Patrick Rudolph (Code Review) 05 Dec '24

05 Dec '24

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85288?usp=email ) Change subject: soc/intel/xeon_sp: Fix debug print ...................................................................... soc/intel/xeon_sp: Fix debug print Fix debug prints that use non-thread safe dev_path(). Since the code is part of MPinit, it's using multiple threads and one threads modifies the only buffer used, resulting in path being printed that do not belong to the current thread. Drop the call since printing the APIC ID is sufficient and thread safe. Change-Id: I0cbc9cb11da8397ab6c2e8e56414558a8a0db93b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85288 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/skx/cpu.c 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index aaac83b..d90b8b5 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -78,8 +78,8 @@ { msr_t msr; - printk(BIOS_SPEW, "%s dev: %s, cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", - __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id, + printk(BIOS_SPEW, "%s: cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", + __func__, cpu_index(), cpu->path.apic.apic_id, cpu->path.apic.package_id); /* diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index 0d828c9..fc49ddc 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -79,8 +79,8 @@ { msr_t msr; - printk(BIOS_INFO, "%s dev: %s, cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", - __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id, + printk(BIOS_INFO, "%s: cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", + __func__, cpu_index(), cpu->path.apic.apic_id, cpu->path.apic.package_id); assert(chip_config); -- To view, visit https://review.coreboot.org/c/coreboot/+/85288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0cbc9cb11da8397ab6c2e8e56414558a8a0db93b Gerrit-Change-Number: 85288 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit December 2024