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Change subject: drivers/intel/dtbt: Add discrete Thunderbolt driver
......................................................................
drivers/intel/dtbt: Add discrete Thunderbolt driver
Add a new driver for discrete Thunderbolt controllers. This allows using
e.g. Maple Ridge devices on Raptor Point PCH.
Ref: Titan Ridge BIOS Implementation Guide v1.4
Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472)
Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
Signed-off-by: Jeremy Soller <jeremy(a)system76.com>
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
A src/drivers/intel/dtbt/Kconfig
A src/drivers/intel/dtbt/Makefile.mk
A src/drivers/intel/dtbt/chip.h
A src/drivers/intel/dtbt/dtbt.c
4 files changed, 214 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/75286/12
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Change subject: drivers/intel/dtbt: Add discrete Thunderbolt driver
......................................................................
drivers/intel/dtbt: Add discrete Thunderbolt driver
Add a new driver for discrete Thunderbolt controllers. This allows using
e.g. Maple Ridge devices on Raptor Point PCH.
Ref: Titan Ridge BIOS Implementation Guide v1.4
Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472)
Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
Signed-off-by: Jeremy Soller <jeremy(a)system76.com>
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
A src/drivers/intel/dtbt/Kconfig
A src/drivers/intel/dtbt/Makefile.mk
A src/drivers/intel/dtbt/chip.h
A src/drivers/intel/dtbt/dtbt.c
M src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
M src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
6 files changed, 220 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/75286/11
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Change subject: driver/amd/opensil: Add PHX OpenSIL POC TP2/TP3 calls
......................................................................
driver/amd/opensil: Add PHX OpenSIL POC TP2/TP3 calls
Call OpenSIL timepoint 2 for further initialization of AMD SoC after
coreboot has performed PCIe enumeration, and timepoint 3 for late SoC
IPs programming and register locking closer to payload load prior to OS
handoff. For future refactors, other generic OpenSIL calls from
vendorcode/src/amd/opensil may be moved into the driver directory as
well.
Change-Id: I8c335211bf36118fe1d6b7dacbf4064c1d7d3a38
Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com>
---
A src/drivers/amd/opensil/Kconfig
A src/drivers/amd/opensil/Makefile.mk
A src/drivers/amd/opensil/amd_silicon_init.c
M src/soc/amd/phoenix/Kconfig
M src/soc/amd/phoenix/chip.c
M src/vendorcode/amd/opensil/opensil.h
6 files changed, 59 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84915/9
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Change subject: mb/google/fatcat: Enable Intel DPTF support and configure policies
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS1:
> @sukumar, could you review the default DPTF values?
Done
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Change subject: mb/google/fatcat: Enable Intel DPTF support and configure policies
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Patchset:
PS4:
verified
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Change subject: mb/google/fatcat: Enable Intel DPTF support and configure policies
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/fatcat: Enable Intel DPTF support and configure policies
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/85457/comment/5cd5ce56_ea4184e7?us… :
PS3, Line 141: register "dptf_enable" = "true"
> > With all the default value below as well ? […]
Done
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Change subject: mb/google/fatcat: Enable Intel DPTF support and configure policies
......................................................................
mb/google/fatcat: Enable Intel DPTF support and configure policies
This commit enables the Dynamic Platform and Thermal Framework (DPTF)
for the fatcat board.
DPTF is a system management framework that allows the board to
dynamically adjust its power and thermal settings based on the system
load and thermal conditions. This can help to improve the board's
performance and battery life.
The following changes were made to enable DPTF:
- Added the Intel DPTF driver to the board's Kconfig file.
- Overrode the default DPTF settings in the fatcat variant
overridetree.cb file.
- Enabled the DPTF policy on the baseboard.
Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/mainboard/google/fatcat/Kconfig
M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
3 files changed, 128 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/85457/4
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Change subject: mb/google/fatcat: Enable Intel DPTF support and configure policies
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/85457/comment/6f720fc8_1494c562?us… :
PS3, Line 141: register "dptf_enable" = "true"
> With all the default value below as well ?
FATCAT is an open board, so none of the thermal policies apply. As long as dptf is enabled, the ODM team should configure the sensor policies.
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Change subject: driver/amd/opensil: Add PHX OpenSIL POC TP2/TP3 calls
......................................................................
Patch Set 8:
(4 comments)
File src/drivers/amd/opensil/amd_silicon_init.c:
https://review.coreboot.org/c/coreboot/+/84915/comment/421e97b9_ccfbb4f5?us… :
PS8, Line 29: BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, call_opensil_xSIM_timepoint, (void *)XSIM_TIMEPOINT_2);
: BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, call_opensil_xSIM_timepoint, (void *)XSIM_TIMEPOINT_3);
: BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, call_opensil_xSIM_timepoint, (void *)XSIM_TIMEPOINT_3);
Do these TP2/TP3 calls need to be conditioned to execute only when PHX is selected? Or will this be common for all SoCs?
File src/soc/amd/phoenix/Kconfig:
https://review.coreboot.org/c/coreboot/+/84915/comment/11767205_97b72ba9?us… :
PS7, Line 103: PLATFORM_USES_OPENSIL
> Yeah, I think that seems reasonable. […]
Done
File src/soc/amd/phoenix/chip.c:
PS6:
> I mentioned this in a private chat, but I agree that chip.c isn't really the place for this code.
Done
https://review.coreboot.org/c/coreboot/+/84915/comment/37937020_afe71339?us… :
PS6, Line 41: default:
: break;
> the latest patchset prints an error in the default case
Done
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