coreboot-gerrit December 2024

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[L] Change in coreboot[main]: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
by Name of user not set (Code Review) 06 Dec '24

06 Dec '24

Attention is currently required from: Felix Singer, Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/65225?usp=email to look at the new patch set (#20). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake) ...................................................................... mb/asrock: Add ASRock H370m-ITX support (Coffee Lake) I tested my code on a Intel i3-9100F under Ubuntu 24.04 and Windows 10 with SeaBIOS. the following things are working flawlessly: * all PCIe slots * all USB ports * VGA init in SeaBIOS (discrete nvida gpu) * WiFi and onboard sound * both Ethernet ports * all SATA ports (besides m.2) what was not tested: * front audio jacks whats not working: * suspend to ram, it won't poweroff correctly * edk2 with Windows 10+ * m.2 sata port/pcie is working romstage changes: * corrects resistor cfg (see 573387) * removes unused dq/dqs mappings * adds default config for Asrock H370M-ITX * uses devicetree pci aliases * removes unncesseray keys in devicetree.cb * rename Makefile.inc to Makefile.mk * load gpio config after FSP-S init * move gpio_table to C file * cleanup gpio.c * adds smbios_slot_desc * fixes pcie devicetree Change-Id: I79302247311471153ebbba991081365d9265791b Signed-off-by: Max Fritz <antischmock(a)googlemail.com> --- A configs/config.asrock_h370m_itx A src/mainboard/asrock/h370m/Kconfig A src/mainboard/asrock/h370m/Kconfig.name A src/mainboard/asrock/h370m/Makefile.mk A src/mainboard/asrock/h370m/board_info.txt A src/mainboard/asrock/h370m/bootblock.c A src/mainboard/asrock/h370m/cmos.default A src/mainboard/asrock/h370m/cmos.layout A src/mainboard/asrock/h370m/devicetree.cb A src/mainboard/asrock/h370m/dsdt.asl A src/mainboard/asrock/h370m/gpio.c A src/mainboard/asrock/h370m/include/gpio.h A src/mainboard/asrock/h370m/ramstage.c A src/mainboard/asrock/h370m/romstage.c 14 files changed, 699 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/65225/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/65225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79302247311471153ebbba991081365d9265791b Gerrit-Change-Number: 65225 Gerrit-PatchSet: 20 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/rex/var/kanix: Enable/Disable PCIE WLAN based on fw_config
by Tyler Wang (Code Review) 06 Dec '24

06 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Tyler Wang has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85511?usp=email ) Change subject: mb/google/rex/var/kanix: Enable/Disable PCIE WLAN based on fw_config ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/85511?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2020c431444f21d82f8722d24065558a62e0cb93 Gerrit-Change-Number: 85511 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 06 Dec 2024 01:11:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
by Boris Mittelberg (Code Review) 06 Dec '24

06 Dec '24

Attention is currently required from: Caveh Jalali, Gwendal Grignou, Rob Barnes. Boris Mittelberg has posted comments on this change by Rob Barnes. ( https://review.coreboot.org/c/coreboot/+/85461?usp=email ) Change subject: ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85461?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia476263620acc269f9dd8a6b3c9e5e247b403aee Gerrit-Change-Number: 85461 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Fri, 06 Dec 2024 00:40:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Disable FP_MCU based on fw_config
by Subrata Banik (Code Review) 06 Dec '24

06 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85365?usp=email ) Change subject: mb/google/rex/var/kanix: Disable FP_MCU based on fw_config ...................................................................... mb/google/rex/var/kanix: Disable FP_MCU based on fw_config BUG=b:377377766 TEST=emerge-rex coreboot pass Change-Id: I087f082c051bc3a97f2514dd121b279e27738022 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85365 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/kanix/Makefile.mk A src/mainboard/google/rex/variants/kanix/fw_config.c 2 files changed, 37 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved YH Lin: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/kanix/Makefile.mk b/src/mainboard/google/rex/variants/kanix/Makefile.mk index a49954c..2638540 100644 --- a/src/mainboard/google/rex/variants/kanix/Makefile.mk +++ b/src/mainboard/google/rex/variants/kanix/Makefile.mk @@ -1,7 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c - romstage-y += gpio.c - +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c diff --git a/src/mainboard/google/rex/variants/kanix/fw_config.c b/src/mainboard/google/rex/variants/kanix/fw_config.c new file mode 100644 index 0000000..23e3e3c --- /dev/null +++ b/src/mainboard/google/rex/variants/kanix/fw_config.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <gpio.h> + +#define GPIO_PADBASED_OVERRIDE(b, a) gpio_padbased_override(b, a, ARRAY_SIZE(a)) + +static const struct pad_config fp_disable_pads[] = { + /* GPP_B11 : [] ==> EN_FP_PWR */ + PAD_NC(GPP_B11, NONE), + /* GPP_C22 : [] ==> SOC_FP_BOOT0 */ + PAD_NC(GPP_C22, NONE), + /* GPP_C23 : [] ==> SOC_FP_RST_L */ + PAD_NC(GPP_C23, NONE), + /* GPP_E10 : [] ==> SOC_FPMCU_INT_L */ + PAD_NC(GPP_E10, NONE), + /* GPP_F11 : [] ==> GSPI1_SOC_CLK_R */ + PAD_NC(GPP_F11, NONE), + /* GPP_F12 : [] ==> GSPI1_SOC_MOSI_R */ + PAD_NC(GPP_F12, NONE), + /* GPP_F13 : [] ==> GSPI1_SOC_MISO_R */ + PAD_NC(GPP_F13, NONE), + /* GPP_F17 : [] ==> GSPI1_SOC_CS_L_R */ + PAD_NC(GPP_F17, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(FP_MCU, FP_MCU_ABSENT))) { + printk(BIOS_INFO, "Configure GPIOs for no FP module.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I087f082c051bc3a97f2514dd121b279e27738022 Gerrit-Change-Number: 85365 Gerrit-PatchSet: 4 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/fatcat: Update Soundwire codec address based on devicetree
by Subrata Banik (Code Review) 06 Dec '24

06 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85440?usp=email ) Change subject: mb/google/fatcat: Update Soundwire codec address based on devicetree ...................................................................... mb/google/fatcat: Update Soundwire codec address based on devicetree This change adds soundwire codec addresses in the devicetree to calculate addresses for the ACPI table instead of previous kconfig which allows single board to select multiple soundwire codecs at runtime based on FW_CONFIG. BUG=b:368495490 TEST=build coreboot image and boot on google fatcat. Disassemble SSDT and confirm ACPI entries are correct for alc7xx device. Change-Id: I3322ae2d106d3628dbf627aacf999056d82ee7a9 Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com> Signed-off-by: Naveen M <naveen.m(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85440 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 2 files changed, 11 insertions(+), 2 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index a67ea3b..3ab4be0 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -10,7 +10,7 @@ select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_WWAN_FM350GL select DRIVERS_AUDIO_SOF - select DRIVERS_SOUNDWIRE_ALC722 + select DRIVERS_SOUNDWIRE_ALC_BASE_7XX select DRIVERS_SPI_ACPI select DUMP_SMBIOS_TYPE17 select EC_ACPI diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index fba49fd..26490f1 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -621,11 +621,20 @@ chip drivers/intel/soundwire device generic 0 on chip drivers/soundwire/alc711 - # SoundWire Link 1 ID 1 register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2" + register "alc711_address.class" = "MIPI_CLASS_SDCA" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC722" + # SoundWire Link 1 ID 1 device generic 1.1 on probe AUDIO AUDIO_ALC722_SNDW end + end + chip drivers/soundwire/alc711 + register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2" + register "alc711_address.class" = "MIPI_CLASS_SDCA" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721" # SoundWire Link 3 ID 1 device generic 3.1 on probe AUDIO AUDIO_ALC721_SNDW -- To view, visit https://review.coreboot.org/c/coreboot/+/85440?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3322ae2d106d3628dbf627aacf999056d82ee7a9 Gerrit-Change-Number: 85440 Gerrit-PatchSet: 7 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs
by Subrata Banik (Code Review) 06 Dec '24

06 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85282?usp=email ) Change subject: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs ...................................................................... drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs - Use common config DRIVERS_SOUNDWIRE_ALC_BASE_7XX for ALC7xx variants - Introduce soundwire codec address in soundwire chip.h to calculate device address for acpi table based on overridetree. - Update devicetree and Kconfig to use common config. BUG=b:368495490 TEST=build coreboot image and boot on Intel RVP board. Disassemble SSDT and confirm ACPI entries are correct for alc7xx device. Change-Id: I5953d0fcb7b15368888901f88c5616757ac42877 Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com> Signed-off-by: Naveen M <naveen.m(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85282 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/alc711/chip.h M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 8 files changed, 22 insertions(+), 24 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/soundwire/alc711/alc711.c b/src/drivers/soundwire/alc711/alc711.c index 1a31f0d..83552c4 100644 --- a/src/drivers/soundwire/alc711/alc711.c +++ b/src/drivers/soundwire/alc711/alc711.c @@ -10,25 +10,6 @@ #include "chip.h" -static struct soundwire_address alc711_address = { -#if CONFIG(DRIVERS_SOUNDWIRE_ALC722) - .version = SOUNDWIRE_VERSION_1_2, - .part_id = MIPI_DEV_ID_REALTEK_ALC722, - .class = MIPI_CLASS_SDCA, -#elif CONFIG(DRIVERS_SOUNDWIRE_ALC721) - .version = SOUNDWIRE_VERSION_1_2, - .part_id = MIPI_DEV_ID_REALTEK_ALC721, - .class = MIPI_CLASS_SDCA, -#elif CONFIG(DRIVERS_SOUNDWIRE_ALC711) - .version = SOUNDWIRE_VERSION_1_1, - .part_id = MIPI_DEV_ID_REALTEK_ALC711, - .class = MIPI_CLASS_NONE, -#else -#error "No Realtek SoundWire codec selected" -#endif - .manufacturer_id = MIPI_MFG_ID_REALTEK, -}; - static struct soundwire_slave alc711_slave = { .wake_up_unavailable = false, .test_mode_supported = false, @@ -123,10 +104,11 @@ acpigen_write_device(acpi_device_name(dev)); /* Set codec address IDs. */ - alc711_address.link_id = dev->path.generic.id; - alc711_address.unique_id = dev->path.generic.subid; + config->alc711_address.link_id = dev->path.generic.id; + config->alc711_address.unique_id = dev->path.generic.subid; + config->alc711_address.manufacturer_id = MIPI_MFG_ID_REALTEK; - acpigen_write_ADR_soundwire_device(&alc711_address); + acpigen_write_ADR_soundwire_device(&config->alc711_address); acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name); acpigen_write_STA(acpi_device_status(dev)); diff --git a/src/drivers/soundwire/alc711/chip.h b/src/drivers/soundwire/alc711/chip.h index 6d317fd..c628209 100644 --- a/src/drivers/soundwire/alc711/chip.h +++ b/src/drivers/soundwire/alc711/chip.h @@ -3,9 +3,13 @@ #ifndef __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ #define __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ +#include <device/soundwire.h> +#include <mipi/ids.h> + struct drivers_soundwire_alc711_config { const char *name; const char *desc; + struct soundwire_address alc711_address; }; #endif /* __DRIVERS_SOUNDWIRE_ALC711_CHIP_H__ */ diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 0171ebc..279a8f9 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -10,7 +10,7 @@ select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_SOUNDWIRE - select DRIVERS_SOUNDWIRE_ALC711 + select DRIVERS_SOUNDWIRE_ALC_BASE_7XX select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index a6bad13..a3b3c93 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -456,6 +456,9 @@ chip drivers/soundwire/alc711 # SoundWire Link 0 ID 1 register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1" + register "alc711_address.class" = "MIPI_CLASS_NONE" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711" device generic 0.1 on end end end diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 922b673..d6bf36a 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -393,6 +393,9 @@ chip drivers/soundwire/alc711 # SoundWire Link 0 ID 1 register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1" + register "alc711_address.class" = "MIPI_CLASS_NONE" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711" device generic 0.1 on end end end diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index db859a1..7e66656 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -390,6 +390,9 @@ chip drivers/soundwire/alc711 # SoundWire Link 0 ID 1 register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1" + register "alc711_address.class" = "MIPI_CLASS_NONE" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711" device generic 0.1 on end end end diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 84ebade..dfe5e44 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -13,7 +13,7 @@ select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SOUNDWIRE_ALC5682 - select DRIVERS_SOUNDWIRE_ALC711 + select DRIVERS_SOUNDWIRE_ALC_BASE_7XX select DRIVERS_SOUNDWIRE_MAX98373 select DRIVERS_USB_ACPI select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 9ba7118..3b17bce 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -604,6 +604,9 @@ chip drivers/soundwire/alc711 # SoundWire Link 0 ID 1 register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1" + register "alc711_address.class" = "MIPI_CLASS_NONE" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711" device generic 0.1 on probe AUDIO MTL_ALC711_SNDW end -- To view, visit https://review.coreboot.org/c/coreboot/+/85282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5953d0fcb7b15368888901f88c5616757ac42877 Gerrit-Change-Number: 85282 Gerrit-PatchSet: 12 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/fatcat: Update flash layout
by Subrata Banik (Code Review) 06 Dec '24

06 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85497?usp=email ) Change subject: mb/google/fatcat: Update flash layout ...................................................................... mb/google/fatcat: Update flash layout This patch updates the flash layout for Fatcat variants to ensure the flash layout is in alignment with the previous generation CrOS devices like Rex. SI_ALL: 9MB -> 8MB SI_BIOS: 23MB -> 24MB BUG=b:382247229 TEST=Able to build and boot google/fatcat. Change-Id: I716fae09dee0c05b8b840dc80647d7959aa03a50 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85497 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/fatcat/chromeos-debug-fsp.fmd M src/mainboard/google/fatcat/chromeos.fmd 2 files changed, 24 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd index 8d41977..0e1e636 100644 --- a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd +++ b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd @@ -1,23 +1,14 @@ FLASH 32M { - SI_ALL 9M { + SI_ALL 8M { SI_DESC 16K SI_ME } - SI_BIOS 23M { + SI_BIOS 24M { RW_SECTION_A 7680K { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 } - # This section starts at the 16M boundary in SPI flash. - # PTL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 7680K { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K @@ -31,8 +22,17 @@ RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 24K } + # This section starts at the 16M boundary in SPI flash. + # PTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7680K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } RW_LEGACY(CBFS) 1M - RW_UNUSED 2M + RW_UNUSED 3M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 4M { diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd index 4b42403..ca29bbc 100644 --- a/src/mainboard/google/fatcat/chromeos.fmd +++ b/src/mainboard/google/fatcat/chromeos.fmd @@ -1,23 +1,14 @@ FLASH 32M { - SI_ALL 9M { + SI_ALL 8M { SI_DESC 16K SI_ME } - SI_BIOS 23M { + SI_BIOS 24M { RW_SECTION_A 7M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 } - # This section starts at the 16M boundary in SPI flash. - # PTL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 7M { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K @@ -31,8 +22,17 @@ RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 24K } + # This section starts at the 16M boundary in SPI flash. + # PTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } RW_LEGACY(CBFS) 1M - RW_UNUSED 3M + RW_UNUSED 4M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 4M { -- To view, visit https://review.coreboot.org/c/coreboot/+/85497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I716fae09dee0c05b8b840dc80647d7959aa03a50 Gerrit-Change-Number: 85497 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/ptl: Populate SMBIOS Type 4 with unique serial number
by Subrata Banik (Code Review) 06 Dec '24

06 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85456?usp=email ) Change subject: soc/intel/ptl: Populate SMBIOS Type 4 with unique serial number ...................................................................... soc/intel/ptl: Populate SMBIOS Type 4 with unique serial number This commit enhances the SMBIOS Type 4 table by populating the "serial number" field with the unique SoC QDF information retrieved via PMC IPC. This improvement provides more accurate and detailed processor information for Panther Lake SoCs and onwards, aiding in: - System identification - Diagnostics - Asset management Previously, the serial number field was not populated. TEST=Able to build and boot google/fatcat. Example of SMBIOS Type 4 output: Before this commit: Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified After this commit: Serial Number: ABCD (Example SoC QDF information) Asset Tag: Not Specified Part Number: Not Specified Change-Id: I38a0bb0e44c619393b8f058ae30fbf2f9719b724 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85456 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/soc/intel/pantherlake/cpu.c 1 file changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/cpu.c b/src/soc/intel/pantherlake/cpu.c index 28fa1d8..4b3c950 100644 --- a/src/soc/intel/pantherlake/cpu.c +++ b/src/soc/intel/pantherlake/cpu.c @@ -15,6 +15,8 @@ #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> +#include <intelblocks/pmclib.h> +#include <smbios.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -234,3 +236,14 @@ return 0; } + +/* Override SMBIOS type 4 processor serial numbers */ +const char *smbios_processor_serial_number(void) +{ + char *qdf = retrieve_soc_qdf_info_via_pmc_ipc(); + + if (qdf != NULL) + return qdf; + else + return ""; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85456?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I38a0bb0e44c619393b8f058ae30fbf2f9719b724 Gerrit-Change-Number: 85456 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Retrieve SoC QDF information via PMC IPC
by Subrata Banik (Code Review) 06 Dec '24

06 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85455?usp=email ) Change subject: soc/intel/cmn/pmc: Retrieve SoC QDF information via PMC IPC ...................................................................... soc/intel/cmn/pmc: Retrieve SoC QDF information via PMC IPC This commit introduces a new function, `retrieve_soc_qdf_info_via_pmc_ipc()`, to retrieve the SoC QDF information string using the PMC IPC mechanism. This function allows for more flexible use of the SoC QDF information, enabling its use in various data structures like the SMBIOS Type 4 table. The existing `pmc_dump_soc_qdf_info()` function is updated to use this new function to retrieve the QDF information before printing it. TEST=Able to build and boot google/fatcat. Change-Id: I91ccf8aae4be9e9bbcad8ef2f422b88edef66376 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85455 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 29 insertions(+), 9 deletions(-) Approvals: Christian Walter: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 18d1b4d..5423865 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -287,4 +287,15 @@ */ void pmc_dump_soc_qdf_info(void); +/* + * Retrieve SoC QDF information. + * + * This function retrieves the SoC QDF information string, which can be used to + * populate various data structures, such as the SMBIOS Type 4 table for CPU + * identification. + * + * @return A pointer to the SoC QDF information string. + */ +char *retrieve_soc_qdf_info_via_pmc_ipc(void); + #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index c51a960..0fadd6e 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -934,20 +934,16 @@ printk(BIOS_ERR, "PMC: Failed sending PCI Enumeration Done Command\n"); } -/* - * This function reads and prints SoC QDF information using PMC interface - * if SOC_QDF_DYNAMIC_READ_PMC config is enabled. - */ -void pmc_dump_soc_qdf_info(void) +char *retrieve_soc_qdf_info_via_pmc_ipc(void) { struct pmc_ipc_buffer req = { 0 }; struct pmc_ipc_buffer rsp; uint32_t cmd_reg; int r; - char qdf_info[5]; + static char qdf_info[5] = { 0 }; if (!CONFIG(SOC_QDF_DYNAMIC_READ_PMC)) - return; + return NULL; req.buf[0] = PMC_IPC_CMD_REGID_SOC_QDF; cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_SOC_REG_ACC, @@ -959,7 +955,7 @@ if (r < 0 || rsp.buf[0] == 0) { printk(BIOS_ERR, "%s: pmc_send_ipc_cmd failed or QDF not available.\n", __func__); - return; + return NULL; } qdf_info[0] = ((rsp.buf[0] >> 24) & 0xFF); @@ -967,5 +963,18 @@ qdf_info[2] = ((rsp.buf[0] >> 8) & 0xFF); qdf_info[3] = (rsp.buf[0] & 0xFF); qdf_info[4] = '\0'; - printk(BIOS_INFO, "SoC QDF: %s\n", qdf_info); + + return qdf_info; +} + +/* + * This function reads and prints SoC QDF information using PMC interface + * if SOC_QDF_DYNAMIC_READ_PMC config is enabled. + */ +void pmc_dump_soc_qdf_info(void) +{ + char *qdf = retrieve_soc_qdf_info_via_pmc_ipc(); + + if (qdf != NULL) + printk(BIOS_INFO, "SoC QDF: %s\n", qdf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85455?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91ccf8aae4be9e9bbcad8ef2f422b88edef66376 Gerrit-Change-Number: 85455 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/intel/dtbt: Add discrete Thunderbolt driver
by Máté Kukri (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Alexander Couzens, Kyösti Mälkki, Martin L Roth, Michał Żygowski, Paul Menzel, Tim Crawford, Tim Wawrzynczak, Utkarsh H Patel. Máté Kukri has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/75286?usp=email ) Change subject: drivers/intel/dtbt: Add discrete Thunderbolt driver ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: Reason for rebase is planned use on ThinkPad T480 for supporting the Alpine Ridge controller. -- To view, visit https://review.coreboot.org/c/coreboot/+/75286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364 Gerrit-Change-Number: 75286 Gerrit-PatchSet: 12 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Máté Kukri <km(a)mkukri.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Dec 2024 20:44:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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