coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[M] Change in coreboot[main]: mb/google/fatcat: Enable Intel DPTF support and configure policies
by Jérémy Compostella (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Pranava Y N, Subrata Banik, Sukumar Ghorai. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85457?usp=email ) Change subject: mb/google/fatcat: Enable Intel DPTF support and configure policies ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85457/comment/0c956621_1d3b67ba?us… : PS3, Line 141: register "dptf_enable" = "true" > can you please ensure overriding the baseboard directly ? […] With all the default value below as well ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85457?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97 Gerrit-Change-Number: 85457 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 05 Dec 2024 16:06:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[XS] Change in coreboot[main]: soc/intel/pantherlake: Remove unnecessary cep_enable SoC chip field
by Jérémy Compostella (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85452?usp=email ) Change subject: soc/intel/pantherlake: Remove unnecessary cep_enable SoC chip field ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > I noticed some contradictory changes in the last version of FSP. […] I am saying the we did not need the UPD controlling the current Excursion Protection on PantherLake (and another recent platform) but it looks like that it could be re-introduced. I am waiting for feedback from the right stakeholders and this is why I put this CL on hold. Stay tuned. -- To view, visit https://review.coreboot.org/c/coreboot/+/85452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42d8c793ac3f33eca212320605b16f3b92c60b9c Gerrit-Change-Number: 85452 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 05 Dec 2024 16:04:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[M] Change in coreboot[main]: driver/amd/opensil: Add PHX OpenSIL POC TP2/TP3 calls
by Nick Kochlowski (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Ana Carolina Cabral, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nick Kochlowski, Paul Menzel. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84915?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: driver/amd/opensil: Add PHX OpenSIL POC TP2/TP3 calls ...................................................................... driver/amd/opensil: Add PHX OpenSIL POC TP2/TP3 calls Call OpenSIL timepoint 2 for further initialization of AMD SoC after coreboot has performed PCIe enumeration, and timepoint 3 for late SoC IPs programming and register locking closer to payload load prior to OS handoff. For future refactors, other generic OpenSIL calls from vendorcode/src/amd/opensil may be moved into the driver directory as well. Change-Id: I8c335211bf36118fe1d6b7dacbf4064c1d7d3a38 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- A src/drivers/amd/opensil/Kconfig A src/drivers/amd/opensil/Makefile.mk A src/drivers/amd/opensil/amd_silicon_init.c M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/chip.c M src/vendorcode/amd/opensil/opensil.h 6 files changed, 53 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84915/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84915?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c335211bf36118fe1d6b7dacbf4064c1d7d3a38 Gerrit-Change-Number: 84915 Gerrit-PatchSet: 8 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral

1 0

[XS] Change in coreboot[main]: mb/amb/birman*/gpio: use native functions for VDD_MEM_VID[0,1]
by Ana Carolina Cabral (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Felix Held. Ana Carolina Cabral has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/85498?usp=email ) Change subject: mb/amb/birman*/gpio: use native functions for VDD_MEM_VID[0,1] ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85498/comment/c5b8cf68_9f3e441f?us… : PS1, Line 7: mb/amb/birman*: gpio.c > maybe: […] Done File src/mainboard/amd/birman/gpio.c: https://review.coreboot.org/c/coreboot/+/85498/comment/3ffd7e40_3d3f1f18?us… : PS1, Line 33: PULL_NONE > from the schematic, i'd expect this to be PULL_UP. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Gerrit-Change-Number: 85498 Gerrit-PatchSet: 2 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 05 Dec 2024 13:38:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[XS] Change in coreboot[main]: mb/amb/birman*/gpio: use native functions for VDD_MEM_VID[0,1]
by Ana Carolina Cabral (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Ana Carolina Cabral, Fred Reitberger, Jason Glenesk. Hello Felix Held, Fred Reitberger, Jason Glenesk, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85498?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/amb/birman*/gpio: use native functions for VDD_MEM_VID[0,1] ...................................................................... mb/amb/birman*/gpio: use native functions for VDD_MEM_VID[0,1] Fix VDD_MEM_VID[0,1] pin assignments that was causing boot issues. Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Signed-off-by: Ana Carolina Cabral <ana.cabral(a)amd.com> --- M src/mainboard/amd/birman/gpio.c M src/mainboard/amd/birman_plus/gpio.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/85498/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Gerrit-Change-Number: 85498 Gerrit-PatchSet: 2 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral

1 0

[M] Change in coreboot[main]: mb/google/brya/var/uldrenite: Add HDA verb tables
by Subrata Banik (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Frank Wu, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Paul Menzel. Subrata Banik has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85448?usp=email ) Change subject: mb/google/brya/var/uldrenite: Add HDA verb tables ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85448?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9d0e17e1ab13adc8aea0d5bcbbe44785a137d7b Gerrit-Change-Number: 85448 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 05 Dec 2024 09:22:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: mainboard/ocp/tiogapass: Enable TPM
by Patrick Rudolph (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Johnny Lin, Morgan Jang. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85510?usp=email ) Change subject: mainboard/ocp/tiogapass: Enable TPM ...................................................................... mainboard/ocp/tiogapass: Enable TPM Add support for the optional TPM. When GPP_A22 is low a TPM is installed. TEST: Found a working TPM 2.0 SLB9670 on ocp/tiogapass. Change-Id: I970033981a265eb0094bc91fc070487b34972a5a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/ocp/tiogapass/ramstage.c 3 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/85510/1 diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 8bf7e79..a1ff82f 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -14,6 +14,8 @@ select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400 select UART_OVERRIDE_BAUDRATE + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_USES_IFD_10GBE_0_REGION select VPD diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 37e740a..427694a 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -82,6 +82,9 @@ chip drivers/ipmi/ocp # OCP specific IPMI porting device pnp ca2.1 on end end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 alias tpm on end + end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.1 hidden end # p2sb device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index a07edb8..fbc5e92 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -3,8 +3,10 @@ #include <cpu/x86/smm.h> #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> +#include <gpio.h> #include <soc/ramstage.h> #include <soc/smmrelocate.h> +#include <static.h> extern struct fru_info_str fru_strings; @@ -165,8 +167,18 @@ t->count = smbios_add_oem_string(t->eos, TBF); } +WEAK_DEV_PTR(tpm); + static void mainboard_enable(struct device *dev) { + struct device *tpm = DEV_PTR(tpm); + + gpio_input(GPP_A22); + if (tpm) + tpm->enabled = !gpio_get(GPP_A22); + + printk(BIOS_DEBUG, "TPM present: %d\n", !gpio_get(GPP_A22)); + dev->ops->get_smbios_strings = tp_oem_smbios_strings; read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings); #if CONFIG(GENERATE_SMBIOS_TABLES) -- To view, visit https://review.coreboot.org/c/coreboot/+/85510?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I970033981a265eb0094bc91fc070487b34972a5a Gerrit-Change-Number: 85510 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com>

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Introduce early_pch_init
by Patrick Rudolph (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85505?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Introduce early_pch_init ...................................................................... soc/intel/xeon_sp: Introduce early_pch_init Stop using platform_fsp_memory_init_params_cb() as SoC specific romstage hook and introduce early_pch_init() to do PCH init in romstage before FSP-M runs. Move PCH specific code into early_pch_init and call it from common code. Change-Id: Id31a2018f5820098e83782b19a1672d2e35bdb83 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/ebg/soc_pch.c M src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h M src/soc/intel/xeon_sp/ibl/soc_pch.c M src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/lbg/soc_pch.c M src/soc/intel/xeon_sp/romstage.c M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 10 files changed, 29 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85505/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id31a2018f5820098e83782b19a1672d2e35bdb83 Gerrit-Change-Number: 85505 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs
by Patrick Rudolph (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Alicja Michalska, Angel Pons, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Hello Alicja Michalska, Angel Pons, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85170?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ...................................................................... soc/intel/xeon_sp/skx: Configure IOAPICs FSP only configures the PCH IOAPIC. Let coreboot reconfigure all IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, and the IOAPICs on Socket1 start at GSI 72, thus calculate the exact GSI address for each IOAPIC instead of assume it's a linear address space. Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info() from advertising wrong GSI addresses. TEST: Booted on ocp/tiogapass with correct GSI bases asigned matching the _PRT advertised GSI bases. Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/lpc_gen1.c M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.mk A src/soc/intel/xeon_sp/skx/ioapic.c 4 files changed, 71 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/85170/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Gerrit-Change-Number: 85170 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

1 0

[M] Change in coreboot[main]: mb/google/brya/var/uldrenite: Add HDA verb tables
by Dtrain Hsu (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Frank Wu, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85448?usp=email ) Change subject: mb/google/brya/var/uldrenite: Add HDA verb tables ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85448?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9d0e17e1ab13adc8aea0d5bcbbe44785a137d7b Gerrit-Change-Number: 85448 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 05 Dec 2024 09:10:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2024