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Change subject: mainboard: Add MSI MS-7788
......................................................................
Patch Set 9:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79979/comment/6dc61c93_aa7ddad1?us… :
PS9, Line 11: * I disabled it and everything seems to work...
Add early init to your mainboard tree, disable it in bootblock by calling the function:
```
#include <bootblock_common.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
void bootblock_mainboard_early_init(void)
{ mchbar_write16(SSKPD_HI, 0); }
```
https://review.coreboot.org/c/coreboot/+/79979/comment/9ecd826e_d3ed9683?us… :
PS9, Line 44: * PS/2
Likely won't work without configuring SIO registers
https://review.coreboot.org/c/coreboot/+/79979/comment/ff450a84_2c4e1baa?us… :
PS9, Line 47: Signed-off-by: mrhh69 <122405954+mrhh69(a)users.noreply.github.com>
Incorrect sign-off
File src/mainboard/msi/ms7788/Kconfig:
https://review.coreboot.org/c/coreboot/+/79979/comment/6506076a_c335c1fa?us… :
PS9, Line 1: if BOARD_MSI_MS_7788
Missing license identifier
File src/mainboard/msi/ms7788/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/79979/comment/4273552d_d345191c?us… :
PS9, Line 1: config BOARD_MSI_MS_7788
Missing license identifier
File src/mainboard/msi/ms7788/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/79979/comment/f0a02bea_e37d5e09?us… :
PS9, Line 8: register "docking_supported" = "0"
Why? This board isn't a laptop, right?
File src/northbridge/intel/sandybridge/romstage.c:
https://review.coreboot.org/c/coreboot/+/79979/comment/652e8c1b_ad3f409d?us… :
PS9, Line 56: //if (mchbar_read16(SSKPD_HI) == 0xcafe)
Please avoid modifying common code. If there are other mainboards experiencing the same issue, we could convert it to Kconfig option.
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Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
......................................................................
Patch Set 20:
(5 comments)
Patchset:
PS20:
Hi!
File src/mainboard/asrock/h370m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/65225/comment/6c4d02e9_4e94c35c?us… :
PS20, Line 6: register "s0ix_enable" = "1"
Try disabling it, platform might suspend correctly if you use S3 state instead
https://review.coreboot.org/c/coreboot/+/65225/comment/0f77075e_10ccbaa1?us… :
PS20, Line 14: device ref igpu on end
Did you forget to include DDI configuration?
Boot Linux with `drm.debug=0xe` kernel parameter and configure them according to VBT configuration.
https://review.coreboot.org/c/coreboot/+/65225/comment/57388f37_2bace93a?us… :
PS20, Line 59: device ref sata on
Check your GPIO config against Intel's PCH documentaton
https://review.coreboot.org/c/coreboot/+/65225/comment/1c51a956_771f600a?us… :
PS20, Line 115: device ref lpc_espi on
You can obtain a copy of datasheet for SuperIO from Nuvoton if you send them an email. This will allow you to add support for it, have RS232 port, suspend and fan control working.
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Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
......................................................................
Patch Set 20:
(2 comments)
This change is ready for review.
Patchset:
PS19:
> regarding the suspend issue i have something in my coreboot log like: […]
Done
Patchset:
PS20:
should i fix the suspend and m.2 sata issue here? or is it okay to create two new tickets for that, after this is merged?
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Change subject: soc/intel/pantherlake: Change CRASHLOG_NODES_COUNT to 1
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85531/comment/6822ffb0_d3afb1f5?us… :
PS6, Line 7: Change
Decrease
https://review.coreboot.org/c/coreboot/+/85531/comment/886420ea_6b7d2d70?us… :
PS6, Line 10:
Why do you change the number? Please elaborate in the commit message.
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Change subject: mb/trulo/var/uldrenite: Configuration Network and Audio
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85583/comment/36af4f7b_fdaabd49?us… :
PS2, Line 7: Configuration
Configure
https://review.coreboot.org/c/coreboot/+/85583/comment/b01c3044_c37c9a00?us… :
PS2, Line 11: 3. Enable HDA driver
Why not make HDA/audio a separate commit?
File src/mainboard/google/brya/variants/uldrenite/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/85583/comment/21c42d7d_8548dba4?us… :
PS2, Line 435: end #PCIE2 WWAN card
Space after #?
https://review.coreboot.org/c/coreboot/+/85583/comment/c0743dca_b620ebe4?us… :
PS2, Line 445: "max98360a"
: register "jack_tplg" = "rt5682"
Add this to the commit message?
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Change subject: mb/trulo/var/uldrenite: Configuration USB ports and mapping
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85582/comment/218b562c_a0968fc7?us… :
PS2, Line 7: Configuration
Configure
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Change subject: mb/google/brya/var/uldrenite: update gpio settings
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85522/comment/31680667_07c3ab62?us… :
PS5, Line 7: update
Maybe next time *Add*, because no settings were present before.
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Change subject: mb/google/nissa/var/quandiso2: Create a quandiso2 variant
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85570/comment/5624b7da_2255f6e9?us… :
PS5, Line 14: TEST=build, and boot into OS
Do you already have the time, how long coreboot takes to get to payload?
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Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/pantherlake: Change CRASHLOG_NODES_COUNT to 1
......................................................................
soc/intel/pantherlake: Change CRASHLOG_NODES_COUNT to 1
This patch changes child records count to 1.
source= 733648-LNLFAS-15.3.4
BUG=None
TEST=Build fatcat and verify the child record count
Change-Id: I209366d324c95b7a32afdcfb792c34d927a0508e
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/soc/intel/pantherlake/crashlog.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/85531/6
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