coreboot-gerrit December 2024

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[L] Change in coreboot[main]: mainboard: Add support for MiTAC Computing Whitestone-2
by Shuo Liu (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Lean Sheng Tan, Mark Chang, Patrick Rudolph, Paul Menzel, niehaitao(a)bytedance.com, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Mark Chang. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email ) Change subject: mainboard: Add support for MiTAC Computing Whitestone-2 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Gerrit-Change-Number: 85532 Gerrit-PatchSet: 6 Gerrit-Owner: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wilson-MiTACComputing <wilson.chien(a)mitaccomputing.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 02:59:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Yidi Lin (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Ccong Chen, Hung-Te Lin, Wenzhen Yu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Ccong Chen. ( https://review.coreboot.org/c/coreboot/+/85599?usp=email ) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... Patch Set 1: (16 comments) File src/soc/mediatek/common/spm.c: https://review.coreboot.org/c/coreboot/+/85599/comment/f7fdab66_d5988397?us… : PS1, Line 59: #ifndef CONFIG_MEDIATEK_SPM_V2 if (!CONFIG(MEDIATEK_SPM_V2)) Please explain in the commit message why the following setting is not needed on mt8196. https://review.coreboot.org/c/coreboot/+/85599/comment/21e80cd5_5adbfc4b?us… : PS1, Line 101: CONFIG_MEDIATEK_SPM_V2 if (!CONFIG(MEDIATEK_SPM_V2)) File src/soc/mediatek/mt8196/include/soc/spm.h: https://review.coreboot.org/c/coreboot/+/85599/comment/f12635b8_c4a9abda?us… : PS1, Line 508: u32 spm_power_on_val[4]; Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/e12a4422_8290a73c?us… : PS1, Line 535: u32 md32pcm_scu_ctrl[4]; Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/ed858277_2671a36f?us… : PS1, Line 562: u32 sw2spm_mailbox[4]; : u32 spm2sw_mailbox[4]; : Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/af5e328c_0472afd8?us… : PS1, Line 575: u32 pcm_apwdt_latch[20]; Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/24efaec5_bbe93016?us… : PS1, Line 591: u32 spm_dpsw_con; Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/afab2871_6fd84000?us… : PS1, Line 645: struct { : u32 latch_l; : u32 latch_h; : } sys_timer_latch[16]; Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/2642f38b_c846d224?us… : PS1, Line 654: u32 pcm_apwdt_latch_20[19]; : u8 reserved18[4]; Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/01f3327e_2f4fa341?us… : PS1, Line 660: u32 spm_sw_rsv[9]; Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/472d7112_c9f34364?us… : PS1, Line 684: u32 spm_sema_m[8]; Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/f363c798_c5a5d043?us… : PS1, Line 687: u32 spm2pmcu_mailbox[4]; : u32 pmcu2spm_mailbox[4]; Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/1dff1b27_0b7b24cc?us… : PS1, Line 704: u32 spm_src_mask[12]; : u32 spm_req_sta[12]; Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/d0c76ffc_e2fc2a8b?us… : PS1, Line 710: u32 spm_resource_ack_con[2]; : u32 spm_resource_ack_mask[9]; Keep it unmodified. https://review.coreboot.org/c/coreboot/+/85599/comment/83f8fe6f_f2710bfc?us… : PS1, Line 717: [1] remove `[1]` https://review.coreboot.org/c/coreboot/+/85599/comment/209dc9a9_24213def?us… : PS1, Line 968: u32 spm_src_mask_17; : u32 spm_src_mask_18; : u32 spm_resource_ack_mask_13; : u32 spm_resource_ack_mask_14; The offsets are varied previous version. Please make sure the offsets are correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 1 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 02:58:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/mtkheader: Add GFH header for mt8189 bootblock code
by Yu-Ping Wu (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Hung-Te Lin, Vince Liu. Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/85598?usp=email ) Change subject: util/mtkheader: Add GFH header for mt8189 bootblock code ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47078272880a89e81c851ede307cdc306b1c79ac Gerrit-Change-Number: 85598 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 02:57:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/gothrax: Add probe and GPIO config for HDMI and t...
by Kyle Lin (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Yunlong Jia. Kyle Lin has posted comments on this change by Yunlong Jia. ( https://review.coreboot.org/c/coreboot/+/85512?usp=email ) Change subject: mb/google/nissa/var/gothrax: Add probe and GPIO config for HDMI and touchpanel ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85512/comment/8d1144c3_8d971363?us… : PS1, Line 6: option DB_A 3 > Because DB_A is also used in non-HDMI situations. The name of the DB should clearly indicate the features. Using DB_A is misleading. And using DB_A for non-HDMI MB is just a temporary solution. It should be addressed later. https://review.coreboot.org/c/coreboot/+/85512/comment/8eaf69cd_158ace38?us… : PS1, Line 268: probe TOUCH_PANEL TOUCH_PANEL_DISABLE > One for i2c and another for i2c-hid. […] Please rename the options for TOUCH_PANEL as something like TOUCH_PANEL_I2C_HID and TOUCH_PANEL_I2C_GENERIC -- To view, visit https://review.coreboot.org/c/coreboot/+/85512?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1900658f7c2e09180287a4e61f02e04be203b6e9 Gerrit-Change-Number: 85512 Gerrit-PatchSet: 1 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 16 Dec 2024 02:42:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyle Lin <kylelinck(a)google.com> Comment-In-Reply-To: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/brya/var/uldrenite: Add PnP setting
by John Su (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85597?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/brya/var/uldrenite: Add PnP setting ...................................................................... mb/google/brya/var/uldrenite: Add PnP setting Referencing the baseboard PnP settings for Uldrenite. BUG=b:380789023 TEST=emerge-nissa coreboot Change-Id: Icd537fd5b6bfa589931633b72477414098523b54 --- M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/85597/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85597?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd537fd5b6bfa589931633b72477414098523b54 Gerrit-Change-Number: 85597 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure audio
by John Su (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85600?usp=email to look at the new patch set (#3). Change subject: mb/trulo/var/uldrenite: Configure audio ...................................................................... mb/trulo/var/uldrenite: Configure audio 1. Enable HDA driver 2. Add spkr_tplg = max98360a 3. Add jack_tplg = rt5682 BUG=b:380789023 TEST=emerge-nissa coreboot Change-Id: I8f78a8641de23eadb03348a31574045702b40554 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/Makefile.mk M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/85600/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85600?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f78a8641de23eadb03348a31574045702b40554 Gerrit-Change-Number: 85600 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure audio
by John Su (Code Review) 16 Dec '24

16 Dec '24

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85600?usp=email ) Change subject: mb/trulo/var/uldrenite: Configure audio ...................................................................... mb/trulo/var/uldrenite: Configure audio 1. Enable HDA driver 2. Add spkr_tplg = max98360a 3. Add jack_tplg = rt5682 BUG=b:380789023 TEST=emerge-nissa coreboot Change-Id: I8f78a8641de23eadb03348a31574045702b40554 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/Makefile.mk M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/85600/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index bc53fdf..aa7e643 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -616,6 +616,7 @@ select HAVE_PCIE_WWAN select HAVE_WWAN_POWER_SEQUENCE select DRIVERS_WWAN_FM350GL + select SOC_INTEL_COMMON_BLOCK_HDA_VERB config BOARD_GOOGLE_VELL select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk index 4c33dad..87f515a 100644 --- a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk +++ b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk @@ -4,3 +4,5 @@ romstage-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index 6b81e9f..6aad08f 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -78,6 +78,13 @@ # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. register "tcss_aux_ori" = "0" + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + # Configure external V1P05/Vnn/VnnSx Rails register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, @@ -433,5 +440,13 @@ device pnp 0c09.0 on end end end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85600?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f78a8641de23eadb03348a31574045702b40554 Gerrit-Change-Number: 85600 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Ccong Chen (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Wenzhen Yu. Hello Wenzhen Yu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85599?usp=email to review the following change. Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... soc/meidatek/mt8196: Add SPM loader This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. coreboot log: CBFS: Found 'spm_firmware.pm' @0xadf00 size 0x5a60 in mcache @0xfffdd3c mtk_init_mcu: Loaded (and reset) spm_firmware.pm in 3 msecs (30080 byt) TEST=build pass BUG=348147674 Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Signed-off-by: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/spm.c M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/pll.h M src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/spm.c 8 files changed, 1,643 insertions(+), 227 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/85599/1 diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 55ea5ec..c64329a 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -115,4 +115,10 @@ When this option is enabled, `mtk_mmu_init()` will be done in `bootblock_soc_early_init()` to reduce the boot time. +config MEDIATEK_SPM_V2 + bool + default n + help + This option enables spm version2. + endif diff --git a/src/soc/mediatek/common/spm.c b/src/soc/mediatek/common/spm.c index e39f3da..8e47dce 100644 --- a/src/soc/mediatek/common/spm.c +++ b/src/soc/mediatek/common/spm.c @@ -27,7 +27,10 @@ u32 pmem_start; u32 dmem_start; - ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET; + ptr = (uintptr_t)pcm->buf; + if (!CONFIG(MEDIATEK_SPM_V2)) + ptr += SPM_SYSTEM_BASE_OFFSET; + pmem_words = pcm->desc.pmem_words; total_words = pcm->desc.total_words; dmem_words = total_words - pmem_words; @@ -53,6 +56,7 @@ static void spm_init_pcm_register(void) { +#ifndef CONFIG_MEDIATEK_SPM_V2 /* Init r0 with POWER_ON_VAL0 */ write32(&mtk_spm->pcm_reg_data_ini, read32(&mtk_spm->spm_power_on_val0)); @@ -63,6 +67,8 @@ write32(&mtk_spm->pcm_reg_data_ini, read32(&mtk_spm->spm_power_on_val1)); write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); +#endif + /* In the new SOC design, this part has been simplified */ write32(&mtk_spm->pcm_pwr_io_en, 0); } @@ -92,12 +98,14 @@ while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) ; +#ifndef CONFIG_MEDIATEK_SPM_V2 /* Init register to match PCM expectation */ write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF); write32(&mtk_spm->spm_bus_protect2_mask_b, SPM_BUS_PROTECT2_MASK_B_DEF); write32(&mtk_spm->pcm_reg_data_ini, 0); - +#endif + /* In the new SOC design, this part has been simplified */ spm_set_pcm_flags(pwrctrl); /* Kick PCM to run (only toggle PCM_KICK) */ diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index 2133dbb..8fa30b5 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -17,6 +17,7 @@ select ARM64_USE_ARCH_TIMER select PCI select EARLY_MMU_INIT + select MEDIATEK_SPM_V2 if SOC_MEDIATEK_MT8196 @@ -45,4 +46,9 @@ help The file name of the MediaTek SSPM firmware. +config SPM_FIRMWARE + string + default "spm_firmware.pm" + help + The file name of the MediaTek SPM firmware. endif diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 9652a1e..f5ed93a 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -50,6 +50,7 @@ ramstage-y += ../common/mt6373.c mt6373.c ramstage-y += soc.c ramstage-y += ../common/sspm.c sspm_sram.c +ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/pmif_clk.c pmif_clk.c ramstage-y += ../common/pmif.c pmif_init.c ramstage-y += pmif_spmi.c @@ -65,7 +66,8 @@ mcu-firmware-files := \ $(CONFIG_DPM_DM_FIRMWARE) \ $(CONFIG_DPM_PM_FIRMWARE) \ - $(CONFIG_SSPM_FIRMWARE) + $(CONFIG_SSPM_FIRMWARE) \ + $(CONFIG_SPM_FIRMWARE) $(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \ $(eval $(fw)-file := $(MT8196_BLOB_DIR)/$(fw)) \ diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index cc57292..6000afc 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -143,6 +143,7 @@ APINFRA_SSR_AO_DEBUG_BASE = IO_PHYS + 0x080F1000, AUDIO_BASE = IO_PHYS + 0x0A110000, VLPCFG_BASE = IO_PHYS + 0x0C001000, + SCP_BASE = IO_PHYS + 0x0C004000, SPM_BASE = IO_PHYS + 0x0C004000, SPM_PBUS_BASE = IO_PHYS + 0x0C00D000, RGU_BASE = IO_PHYS + 0x0C010000, @@ -157,6 +158,7 @@ SSPM_CFG_BASE = IO_PHYS + 0x0C340000, SYSTIMER_BASE = IO_PHYS + 0x0C400000, VLP_TRACKER_BASE = IO_PHYS + 0x0C4E0000, + VLP_DEVAPC_BASE = IO_PHYS + 0x0C550A00, MMVOTE_MMSYS_CONFIG_BASE = IO_PHYS + 0x12000000, MMVOTE_MMSYS1_CONFIG_BASE = IO_PHYS + 0x12400000, MMVOTE_OVLSYS_CONFIG_BASE = IO_PHYS + 0x12800000, diff --git a/src/soc/mediatek/mt8196/include/soc/pll.h b/src/soc/mediatek/mt8196/include/soc/pll.h index 7995a65..9a2da4d 100644 --- a/src/soc/mediatek/mt8196/include/soc/pll.h +++ b/src/soc/mediatek/mt8196/include/soc/pll.h @@ -136,13 +136,15 @@ u32 reserved1[1]; u32 clk_cfg_update[3]; struct mtk_clk_cfg clk_cfg[23]; - u32 reserved2[16]; + u32 reserved2[8]; + u32 clk_scp_cfg_0; + u32 reserved3[7]; u32 clk26cali[2]; - u32 reserved3[3]; + u32 reserved4[3]; u32 clk_misc_cfg; - u32 reserved4[10]; + u32 reserved5[10]; u32 clk_dbg_cfg; - u32 reserved5[13]; + u32 reserved6[13]; u32 clk_prot_idle_reg; u32 clk_fenc_bypass_reg[3]; u32 clk_prot_idle_all_reg[3]; @@ -152,6 +154,7 @@ }; check_member(mtk_topckgen_regs, clk_cfg_update[0], 0x0004); check_member(mtk_topckgen_regs, clk_cfg[0], 0x0010); +check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x01A0); check_member(mtk_topckgen_regs, clk26cali[0], 0x01C0); check_member(mtk_topckgen_regs, clk_prot_idle_all_reg[0], 0x0248); check_member(mtk_topckgen_regs, clk_prot_spm_ck_en_reg, 0x026C); diff --git a/src/soc/mediatek/mt8196/include/soc/spm.h b/src/soc/mediatek/mt8196/include/soc/spm.h index b0f1264..5702a10 100644 --- a/src/soc/mediatek/mt8196/include/soc/spm.h +++ b/src/soc/mediatek/mt8196/include/soc/spm.h @@ -9,6 +9,10 @@ #include <soc/spm_common.h> #include <types.h> +#define INFRA_SW_CG 0x10001060 +#define DEBUG_MON_REG_1 0x1c001108 +#define DEBUG_MON_REG_2 0x1c00110c + /* SPM READ/WRITE CFG */ #define SPM_PROJECT_CODE 0xb16 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) @@ -61,11 +65,8 @@ /* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */ DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0) -/************************************** - * Config and Parameter - **************************************/ #define SPM_SYSTEM_BASE_OFFSET 0x40000000 -#define POWER_ON_VAL1_DEF 0x003ffe24 +#define POWER_ON_VAL1_DEF 0x003FFE20 #define SPM_WAKEUP_EVENT_MASK_DEF 0xefffffff #define SPM_BUS_PROTECT_MASK_B_DEF 0xffffffff #define SPM_BUS_PROTECT2_MASK_B_DEF 0xffffffff @@ -81,10 +82,15 @@ #define ARMPLL_CLK_SEL_DEF 0x3ff #define SPM_SYSCLK_SETTLE 0x60fe #define SPM_INIT_DONE_US 20 +#define PCM_WDT_TIMEOUT (30 * 32768) +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) +#define AP_WDT_TIMEOUT_SUSPEND 5400 +#define PCM_TIMER_SUSPEND ((AP_WDT_TIMEOUT_SUSPEND - 30) * 32768) +#define SPM_FLAG_ENABLE_MT8196_ES_WA BIT(24) +#define SPM_FLAG_ENABLE_MT8196_EMI_ES_WA BIT(25) +#define MT_SPM_VERSION_ES 0x0 +#define MT_SPM_VERSION_CS 0x1 -/************************************** - * Definition and Declaration - **************************************/ /* SPM_IRQ_MASK */ #define ISRM_TWAM BIT(2) #define ISRM_PCM_RETURN BIT(3) @@ -192,13 +198,32 @@ u8 vrf18_state; /* SPM_SRC_MASK_0 */ + u8 reg_apifr_mem_apsrc_req_mask_b; + u8 reg_apifr_mem_ddren_req_mask_b; + u8 reg_apifr_mem_emi_req_mask_b; + u8 reg_apifr_mem_infra_req_mask_b; + u8 reg_apifr_mem_pmic_req_mask_b; + u8 reg_apifr_mem_srcclkena_mask_b; + u8 reg_apifr_mem_vcore_req_mask_b; + u8 reg_apifr_mem_vrf18_req_mask_b; u8 reg_apu_apsrc_req_mask_b; u8 reg_apu_ddren_req_mask_b; u8 reg_apu_emi_req_mask_b; u8 reg_apu_infra_req_mask_b; u8 reg_apu_pmic_req_mask_b; u8 reg_apu_srcclkena_mask_b; + u8 reg_apu_vcore_req_mask_b; u8 reg_apu_vrf18_req_mask_b; + u8 reg_audio_apsrc_req_mask_b; + u8 reg_audio_ddren_req_mask_b; + u8 reg_audio_emi_req_mask_b; + u8 reg_audio_infra_req_mask_b; + u8 reg_audio_pmic_req_mask_b; + u8 reg_audio_srcclkena_mask_b; + u8 reg_audio_vcore_req_mask_b; + u8 reg_audio_vrf18_req_mask_b; + + /* SPM_SRC_MASK_1 */ u8 reg_audio_dsp_apsrc_req_mask_b; u8 reg_audio_dsp_ddren_req_mask_b; u8 reg_audio_dsp_emi_req_mask_b; @@ -214,33 +239,18 @@ u8 reg_cam_pmic_req_mask_b; u8 reg_cam_srcclkena_mask_b; u8 reg_cam_vrf18_req_mask_b; - - /* SPM_SRC_MASK_1 */ u32 reg_ccif_apsrc_req_mask_b; - u32 reg_ccif_emi_req_mask_b; - u8 reg_vlpcfg_rsv0_apsrc_req_mask_b; - u8 reg_vlpcfg_rsv0_ddren_req_mask_b; - u8 reg_vlpcfg_rsv0_emi_req_mask_b; - u8 reg_vlpcfg_rsv0_infra_req_mask_b; - u8 reg_vlpcfg_rsv0_pmic_req_mask_b; - u8 reg_vlpcfg_rsv0_srcclkena_mask_b; - u8 reg_vlpcfg_rsv0_vcore_req_mask_b; - u8 reg_vlpcfg_rsv0_vrf18_req_mask_b; /* SPM_SRC_MASK_2 */ + u32 reg_ccif_emi_req_mask_b; u32 reg_ccif_infra_req_mask_b; - u32 reg_ccif_pmic_req_mask_b; - u8 reg_vlpcfg_rsv1_apsrc_req_mask_b; - u8 reg_vlpcfg_rsv1_ddren_req_mask_b; - u8 reg_vlpcfg_rsv1_emi_req_mask_b; - u8 reg_vlpcfg_rsv1_infra_req_mask_b; - u8 reg_vlpcfg_rsv1_pmic_req_mask_b; - u8 reg_vlpcfg_rsv1_srcclkena_mask_b; - u8 reg_vlpcfg_rsv1_vcore_req_mask_b; - u8 reg_vlpcfg_rsv1_vrf18_req_mask_b; /* SPM_SRC_MASK_3 */ + u32 reg_ccif_pmic_req_mask_b; u32 reg_ccif_srcclkena_mask_b; + + /* SPM_SRC_MASK_4 */ + u32 reg_ccif_vcore_req_mask_b; u32 reg_ccif_vrf18_req_mask_b; u8 reg_ccu_apsrc_req_mask_b; u8 reg_ccu_ddren_req_mask_b; @@ -251,7 +261,7 @@ u8 reg_ccu_vrf18_req_mask_b; u8 reg_cg_check_apsrc_req_mask_b; - /* SPM_SRC_MASK_4 */ + /* SPM_SRC_MASK_5 */ u8 reg_cg_check_ddren_req_mask_b; u8 reg_cg_check_emi_req_mask_b; u8 reg_cg_check_infra_req_mask_b; @@ -259,6 +269,32 @@ u8 reg_cg_check_srcclkena_mask_b; u8 reg_cg_check_vcore_req_mask_b; u8 reg_cg_check_vrf18_req_mask_b; + u8 reg_cksys_apsrc_req_mask_b; + u8 reg_cksys_ddren_req_mask_b; + u8 reg_cksys_emi_req_mask_b; + u8 reg_cksys_infra_req_mask_b; + u8 reg_cksys_pmic_req_mask_b; + u8 reg_cksys_srcclkena_mask_b; + u8 reg_cksys_vcore_req_mask_b; + u8 reg_cksys_vrf18_req_mask_b; + u8 reg_cksys_1_apsrc_req_mask_b; + u8 reg_cksys_1_ddren_req_mask_b; + u8 reg_cksys_1_emi_req_mask_b; + u8 reg_cksys_1_infra_req_mask_b; + u8 reg_cksys_1_pmic_req_mask_b; + u8 reg_cksys_1_srcclkena_mask_b; + u8 reg_cksys_1_vcore_req_mask_b; + u8 reg_cksys_1_vrf18_req_mask_b; + + /* SPM_SRC_MASK_6 */ + u8 reg_cksys_2_apsrc_req_mask_b; + u8 reg_cksys_2_ddren_req_mask_b; + u8 reg_cksys_2_emi_req_mask_b; + u8 reg_cksys_2_infra_req_mask_b; + u8 reg_cksys_2_pmic_req_mask_b; + u8 reg_cksys_2_srcclkena_mask_b; + u8 reg_cksys_2_vcore_req_mask_b; + u8 reg_cksys_2_vrf18_req_mask_b; u8 reg_conn_apsrc_req_mask_b; u8 reg_conn_ddren_req_mask_b; u8 reg_conn_emi_req_mask_b; @@ -268,12 +304,23 @@ u8 reg_conn_srcclkenb_mask_b; u8 reg_conn_vcore_req_mask_b; u8 reg_conn_vrf18_req_mask_b; + u8 reg_corecfg_rsv0_apsrc_req_mask_b; + u8 reg_corecfg_rsv0_ddren_req_mask_b; + u8 reg_corecfg_rsv0_emi_req_mask_b; + u8 reg_corecfg_rsv0_infra_req_mask_b; + u8 reg_corecfg_rsv0_pmic_req_mask_b; + u8 reg_corecfg_rsv0_srcclkena_mask_b; + u8 reg_corecfg_rsv0_vcore_req_mask_b; + u8 reg_corecfg_rsv0_vrf18_req_mask_b; + + /* SPM_SRC_MASK_7 */ u8 reg_cpueb_apsrc_req_mask_b; u8 reg_cpueb_ddren_req_mask_b; u8 reg_cpueb_emi_req_mask_b; u8 reg_cpueb_infra_req_mask_b; u8 reg_cpueb_pmic_req_mask_b; u8 reg_cpueb_srcclkena_mask_b; + u8 reg_cpueb_vcore_req_mask_b; u8 reg_cpueb_vrf18_req_mask_b; u8 reg_disp0_apsrc_req_mask_b; u8 reg_disp0_ddren_req_mask_b; @@ -284,8 +331,6 @@ u8 reg_disp0_vrf18_req_mask_b; u8 reg_disp1_apsrc_req_mask_b; u8 reg_disp1_ddren_req_mask_b; - - /* SPM_SRC_MASK_5 */ u8 reg_disp1_emi_req_mask_b; u8 reg_disp1_infra_req_mask_b; u8 reg_disp1_pmic_req_mask_b; @@ -293,12 +338,12 @@ u8 reg_disp1_vrf18_req_mask_b; u8 reg_dpm_apsrc_req_mask_b; u8 reg_dpm_ddren_req_mask_b; + + /* SPM_SRC_MASK_8 */ u8 reg_dpm_emi_req_mask_b; u8 reg_dpm_infra_req_mask_b; u8 reg_dpm_pmic_req_mask_b; u8 reg_dpm_srcclkena_mask_b; - - /* SPM_SRC_MASK_6 */ u8 reg_dpm_vcore_req_mask_b; u8 reg_dpm_vrf18_req_mask_b; u8 reg_dpmaif_apsrc_req_mask_b; @@ -307,17 +352,26 @@ u8 reg_dpmaif_infra_req_mask_b; u8 reg_dpmaif_pmic_req_mask_b; u8 reg_dpmaif_srcclkena_mask_b; + u8 reg_dpmaif_vcore_req_mask_b; u8 reg_dpmaif_vrf18_req_mask_b; + + /* SPM_SRC_MASK_9 */ u8 reg_dvfsrc_level_req_mask_b; u8 reg_emisys_apsrc_req_mask_b; u8 reg_emisys_ddren_req_mask_b; u8 reg_emisys_emi_req_mask_b; + u8 reg_emisys_infra_req_mask_b; + u8 reg_emisys_pmic_req_mask_b; + u8 reg_emisys_srcclkena_mask_b; + u8 reg_emisys_vcore_req_mask_b; + u8 reg_emisys_vrf18_req_mask_b; u8 reg_gce_apsrc_req_mask_b; u8 reg_gce_ddren_req_mask_b; u8 reg_gce_emi_req_mask_b; u8 reg_gce_infra_req_mask_b; u8 reg_gce_pmic_req_mask_b; u8 reg_gce_srcclkena_mask_b; + u8 reg_gce_vcore_req_mask_b; u8 reg_gce_vrf18_req_mask_b; u8 reg_gpueb_apsrc_req_mask_b; u8 reg_gpueb_ddren_req_mask_b; @@ -325,8 +379,7 @@ u8 reg_gpueb_infra_req_mask_b; u8 reg_gpueb_pmic_req_mask_b; u8 reg_gpueb_srcclkena_mask_b; - - /* SPM_SRC_MASK_7 */ + u8 reg_gpueb_vcore_req_mask_b; u8 reg_gpueb_vrf18_req_mask_b; u8 reg_hwccf_apsrc_req_mask_b; u8 reg_hwccf_ddren_req_mask_b; @@ -335,6 +388,8 @@ u8 reg_hwccf_pmic_req_mask_b; u8 reg_hwccf_srcclkena_mask_b; u8 reg_hwccf_vcore_req_mask_b; + + /* SPM_SRC_MASK_10 */ u8 reg_hwccf_vrf18_req_mask_b; u8 reg_img_apsrc_req_mask_b; u8 reg_img_ddren_req_mask_b; @@ -347,6 +402,9 @@ u8 reg_infrasys_ddren_req_mask_b; u8 reg_infrasys_emi_req_mask_b; u8 reg_infrasys_infra_req_mask_b; + u8 reg_infrasys_pmic_req_mask_b; + u8 reg_infrasys_srcclkena_mask_b; + u8 reg_infrasys_vcore_req_mask_b; u8 reg_infrasys_vrf18_req_mask_b; u8 reg_ipic_infra_req_mask_b; u8 reg_ipic_vrf18_req_mask_b; @@ -356,15 +414,16 @@ u8 reg_mcu_infra_req_mask_b; u8 reg_mcu_pmic_req_mask_b; u8 reg_mcu_srcclkena_mask_b; + u8 reg_mcu_vcore_req_mask_b; u8 reg_mcu_vrf18_req_mask_b; u8 reg_md_apsrc_req_mask_b; u8 reg_md_ddren_req_mask_b; - - /* SPM_SRC_MASK_8 */ u8 reg_md_emi_req_mask_b; u8 reg_md_infra_req_mask_b; u8 reg_md_pmic_req_mask_b; u8 reg_md_srcclkena_mask_b; + + /* SPM_SRC_MASK_11 */ u8 reg_md_srcclkena1_mask_b; u8 reg_md_vcore_req_mask_b; u8 reg_md_vrf18_req_mask_b; @@ -374,6 +433,7 @@ u8 reg_mm_proc_infra_req_mask_b; u8 reg_mm_proc_pmic_req_mask_b; u8 reg_mm_proc_srcclkena_mask_b; + u8 reg_mm_proc_vcore_req_mask_b; u8 reg_mm_proc_vrf18_req_mask_b; u8 reg_mml0_apsrc_req_mask_b; u8 reg_mml0_ddren_req_mask_b; @@ -393,11 +453,11 @@ u8 reg_ovl0_ddren_req_mask_b; u8 reg_ovl0_emi_req_mask_b; u8 reg_ovl0_infra_req_mask_b; - - /* SPM_SRC_MASK_9 */ u8 reg_ovl0_pmic_req_mask_b; u8 reg_ovl0_srcclkena_mask_b; u8 reg_ovl0_vrf18_req_mask_b; + + /* SPM_SRC_MASK_12 */ u8 reg_ovl1_apsrc_req_mask_b; u8 reg_ovl1_ddren_req_mask_b; u8 reg_ovl1_emi_req_mask_b; @@ -413,13 +473,32 @@ u8 reg_pcie0_srcclkena_mask_b; u8 reg_pcie0_vcore_req_mask_b; u8 reg_pcie0_vrf18_req_mask_b; + u8 reg_pcie1_apsrc_req_mask_b; + u8 reg_pcie1_ddren_req_mask_b; + u8 reg_pcie1_emi_req_mask_b; + u8 reg_pcie1_infra_req_mask_b; + u8 reg_pcie1_pmic_req_mask_b; + u8 reg_pcie1_srcclkena_mask_b; + u8 reg_pcie1_vcore_req_mask_b; + u8 reg_pcie1_vrf18_req_mask_b; u8 reg_perisys_apsrc_req_mask_b; u8 reg_perisys_ddren_req_mask_b; u8 reg_perisys_emi_req_mask_b; u8 reg_perisys_infra_req_mask_b; u8 reg_perisys_pmic_req_mask_b; u8 reg_perisys_srcclkena_mask_b; + u8 reg_perisys_vcore_req_mask_b; u8 reg_perisys_vrf18_req_mask_b; + u8 reg_pmsr_apsrc_req_mask_b; + + /* SPM_SRC_MASK_13 */ + u8 reg_pmsr_ddren_req_mask_b; + u8 reg_pmsr_emi_req_mask_b; + u8 reg_pmsr_infra_req_mask_b; + u8 reg_pmsr_pmic_req_mask_b; + u8 reg_pmsr_srcclkena_mask_b; + u8 reg_pmsr_vcore_req_mask_b; + u8 reg_pmsr_vrf18_req_mask_b; u8 reg_scp_apsrc_req_mask_b; u8 reg_scp_ddren_req_mask_b; u8 reg_scp_emi_req_mask_b; @@ -427,8 +506,6 @@ u8 reg_scp_pmic_req_mask_b; u8 reg_scp_srcclkena_mask_b; u8 reg_scp_vcore_req_mask_b; - - /* SPM_SRC_MASK_10 */ u8 reg_scp_vrf18_req_mask_b; u8 reg_spu_hwrot_apsrc_req_mask_b; u8 reg_spu_hwrot_ddren_req_mask_b; @@ -436,6 +513,7 @@ u8 reg_spu_hwrot_infra_req_mask_b; u8 reg_spu_hwrot_pmic_req_mask_b; u8 reg_spu_hwrot_srcclkena_mask_b; + u8 reg_spu_hwrot_vcore_req_mask_b; u8 reg_spu_hwrot_vrf18_req_mask_b; u8 reg_spu_ise_apsrc_req_mask_b; u8 reg_spu_ise_ddren_req_mask_b; @@ -443,10 +521,14 @@ u8 reg_spu_ise_infra_req_mask_b; u8 reg_spu_ise_pmic_req_mask_b; u8 reg_spu_ise_srcclkena_mask_b; + u8 reg_spu_ise_vcore_req_mask_b; u8 reg_spu_ise_vrf18_req_mask_b; + + /* SPM_SRC_MASK_14 */ u8 reg_srcclkeni_infra_req_mask_b; u8 reg_srcclkeni_pmic_req_mask_b; u8 reg_srcclkeni_srcclkena_mask_b; + u8 reg_srcclkeni_vcore_req_mask_b; u8 reg_sspm_apsrc_req_mask_b; u8 reg_sspm_ddren_req_mask_b; u8 reg_sspm_emi_req_mask_b; @@ -458,12 +540,21 @@ u8 reg_ssrsys_ddren_req_mask_b; u8 reg_ssrsys_emi_req_mask_b; u8 reg_ssrsys_infra_req_mask_b; - - /* SPM_SRC_MASK_11 */ u8 reg_ssrsys_pmic_req_mask_b; u8 reg_ssrsys_srcclkena_mask_b; + u8 reg_ssrsys_vcore_req_mask_b; u8 reg_ssrsys_vrf18_req_mask_b; + u8 reg_ssusb_apsrc_req_mask_b; + u8 reg_ssusb_ddren_req_mask_b; + u8 reg_ssusb_emi_req_mask_b; + u8 reg_ssusb_infra_req_mask_b; + u8 reg_ssusb_pmic_req_mask_b; + u8 reg_ssusb_srcclkena_mask_b; + u8 reg_ssusb_vcore_req_mask_b; + u8 reg_ssusb_vrf18_req_mask_b; u8 reg_uart_hub_infra_req_mask_b; + + /* SPM_SRC_MASK_15 */ u8 reg_uart_hub_pmic_req_mask_b; u8 reg_uart_hub_srcclkena_mask_b; u8 reg_uart_hub_vcore_req_mask_b; @@ -474,6 +565,7 @@ u8 reg_ufs_infra_req_mask_b; u8 reg_ufs_pmic_req_mask_b; u8 reg_ufs_srcclkena_mask_b; + u8 reg_ufs_vcore_req_mask_b; u8 reg_ufs_vrf18_req_mask_b; u8 reg_vdec_apsrc_req_mask_b; u8 reg_vdec_ddren_req_mask_b; @@ -489,11 +581,36 @@ u8 reg_venc_pmic_req_mask_b; u8 reg_venc_srcclkena_mask_b; u8 reg_venc_vrf18_req_mask_b; + u8 reg_vlpcfg_rsv0_apsrc_req_mask_b; + u8 reg_vlpcfg_rsv0_ddren_req_mask_b; + u8 reg_vlpcfg_rsv0_emi_req_mask_b; + u8 reg_vlpcfg_rsv0_infra_req_mask_b; + u8 reg_vlpcfg_rsv0_pmic_req_mask_b; + u8 reg_vlpcfg_rsv0_srcclkena_mask_b; + + /* SPM_SRC_MASK_16 */ + u8 reg_vlpcfg_rsv0_vcore_req_mask_b; + u8 reg_vlpcfg_rsv0_vrf18_req_mask_b; + u8 reg_vlpcfg_rsv1_apsrc_req_mask_b; + u8 reg_vlpcfg_rsv1_ddren_req_mask_b; + u8 reg_vlpcfg_rsv1_emi_req_mask_b; + u8 reg_vlpcfg_rsv1_infra_req_mask_b; + u8 reg_vlpcfg_rsv1_pmic_req_mask_b; + u8 reg_vlpcfg_rsv1_srcclkena_mask_b; + u8 reg_vlpcfg_rsv1_vcore_req_mask_b; + u8 reg_vlpcfg_rsv1_vrf18_req_mask_b; /* SPM_EVENT_CON_MISC */ u8 reg_srcclken_fast_resp; u8 reg_csyspwrup_ack_mask; + /* SPM_SRC_MASK_17 */ + u32 reg_spm_sw_rsv_vcore_req_mask_b; + u32 reg_spm_sw_rsv_pmic_req_mask_b; + + /* SPM_SRC_MASK_18 */ + u32 reg_spm_sw_rsv_srcclkena_mask_b; + /* SPM_WAKEUP_EVENT_MASK */ u32 reg_wakeup_event_mask; @@ -505,48 +622,62 @@ struct mtk_spm_regs { u32 poweron_config_en; - u32 spm_power_on_val[4]; + u32 spm_power_on_val0; + u32 spm_power_on_val1; + u32 spm_power_on_val2; + u32 spm_power_on_val3; u32 pcm_pwr_io_en; u32 pcm_con0; u32 pcm_con1; u32 spm_sram_sleep_ctrl; u32 spm_clk_con; u32 spm_clk_settle; - u8 reserved0[20]; + u32 reserved0[5]; u32 spm_sw_rst_con; u32 spm_sw_rst_con_set; u32 spm_sw_rst_con_clr; - u8 reserved1[4]; + u32 reserved1[1]; u32 r_sec_read_mask; u32 r_one_time_lock_l; u32 r_one_time_lock_m; u32 r_one_time_lock_h; - u8 reserved2[36]; + u32 reserved2[9]; u32 sspm_clk_con; u32 scp_clk_con; - u8 reserved3[4]; + u32 reserved3[1]; u32 spm_swint; u32 spm_swint_set; u32 spm_swint_clr; - u8 reserved4[20]; + u32 reserved4[5]; u32 spm_cpu_wakeup_event; u32 spm_irq_mask; - u8 reserved5[72]; - u32 md32pcm_scu_ctrl[4]; + u32 reserved5[18]; + u32 md32pcm_scu_ctrl0; + u32 md32pcm_scu_ctrl1; + u32 md32pcm_scu_ctrl2; + u32 md32pcm_scu_ctrl3; u32 md32pcm_scu_sta0; - u8 reserved6[20]; + u32 reserved6[5]; u32 spm_irq_sta; - u8 reserved7[4]; + u32 reserved7[1]; u32 md32pcm_wakeup_sta; u32 md32pcm_event_sta; - u8 reserved8[8]; + u32 reserved8[2]; u32 spm_wakeup_misc; - u8 reserved9[32]; + u32 reserved9[8]; u32 spm_ck_sta; - u8 reserved10[40]; + u32 reserved10[10]; u32 md32pcm_sta; u32 md32pcm_pc; - u8 reserved11[104]; + u32 spm_ulposc_en_cg_con; + u32 spm_resource_ulposc_ack_con; + u32 spm_ulposc_off_mode_con; + u32 spm_ulposc_ack_sta; + u32 spm_reosource_ulposc_mask; + u32 spm_req_block; + u32 dvfs_ips_ctrl; + u32 top_cksys_con; + u32 reserved11[18]; u32 spm_ap_standby_con; u32 cpu_wfi_en; u32 cpu_wfi_en_set; @@ -559,24 +690,31 @@ u32 sw2spm_wakeup; u32 sw2spm_wakeup_set; u32 sw2spm_wakeup_clr; - u32 sw2spm_mailbox[4]; - u32 spm2sw_mailbox[4]; + u32 sw2spm_mailbox_0; + u32 sw2spm_mailbox_1; + u32 sw2spm_mailbox_2; + u32 sw2spm_mailbox_3; + u32 spm2sw_mailbox_0; + u32 spm2sw_mailbox_1; + u32 spm2sw_mailbox_2; + u32 spm2sw_mailbox_3; u32 spm2mcupm_con; - u8 reserved12[12]; + u32 reserved12[3]; u32 spm_mcusys_pwr_con; u32 spm_cputop_pwr_con; u32 spm_cpu_pwr_con[8]; u32 spm_mcupm_spmc_con; - u8 reserved13[20]; + u32 sodi5_mcusys_con; + u32 reserved13[4]; u32 spm_dpm_p2p_sta; u32 spm_dpm_p2p_con; u32 spm_dpm_intf_sta; u32 spm_dpm_wb_con; - u32 pcm_apwdt_latch[20]; + u32 reserved14[20]; u32 spm_pwrap_con; u32 spm_pwrap_con_sta; u32 spm_pmic_spmi_con; - u8 reserved14[4]; + u32 reserved15[1]; u32 spm_pwrap_cmd[32]; u32 dvfsrc_event_sta; u32 spm_force_dvfs; @@ -588,13 +726,23 @@ u32 spm_dvfs_con; u32 spm_sramrc_con; u32 spm_srclkenrc_con; - u32 spm_dpsw_con; + u32 reserved16[1]; u32 spm_dpsw_vapu_iso_con; u32 spm_dpsw_vmm_iso_con; u32 spm_dpsw_vmd_iso_con; u32 spm_dpsw_vmodem_iso_con; u32 spm_dpsw_vcore_iso_con; - u8 reserved15[48]; + u32 spm_dpsw_con; + u32 spm_dpsw_con_set; + u32 spm_dpsw_con_clr; + u32 spm_dpsw_aoc_iso_con; + u32 spm_dpsw_aoc_iso_con_set; + u32 spm_dpsw_aoc_iso_con_clr; + u32 spm_dpsw_force_switch_con; + u32 spm_dpsw_force_switch_con_set; + u32 spm_dpsw_force_switch_con_clr; + u32 spm2dpsw_ctrl_ack; + u32 reserved17[2]; u32 ulposc_con; u32 ap_mdsrc_req; u32 spm2md_switch_ctrl; @@ -612,7 +760,13 @@ u32 cirq_bypass_con; u32 aoc_vcore_sram_con; u32 spm2emi_pdn_ctrl; - u8 reserved16[28]; + u32 vlp_rtff_ctrl_mask; + u32 vlp_rtff_ctrl_mask_set; + u32 vlp_rtff_ctrl_mask_clr; + u32 vlp_rtff_ctrl_mask_2; + u32 vlp_rtff_ctrl_mask_2_set; + u32 vlp_rtff_ctrl_mask_2_clr; + u32 reserved38[1]; u32 reg_module_sw_cg_ddren_req_mask[4]; u32 reg_module_sw_cg_vrf18_req_mask[4]; u32 reg_module_sw_cg_infra_req_mask[4]; @@ -636,33 +790,68 @@ u32 reg_module_busy_f26m_req_mask; u32 reg_module_busy_pmic_req_mask; u32 reg_module_busy_vcore_req_mask; - u8 reserved17[8]; + u32 reserved18[2]; u32 sys_timer_con; u32 sys_timer_value_l; u32 sys_timer_value_h; u32 sys_timer_start_l; u32 sys_timer_start_h; - struct { - u32 latch_l; - u32 latch_h; - } sys_timer_latch[16]; + u32 sys_timer_latch_l_00; + u32 sys_timer_latch_h_00; + u32 sys_timer_latch_l_01; + u32 sys_timer_latch_h_01; + u32 sys_timer_latch_l_02; + u32 sys_timer_latch_h_02; + u32 sys_timer_latch_l_03; + u32 sys_timer_latch_h_03; + u32 sys_timer_latch_l_04; + u32 sys_timer_latch_h_04; + u32 sys_timer_latch_l_05; + u32 sys_timer_latch_h_05; + u32 sys_timer_latch_l_06; + u32 sys_timer_latch_h_06; + u32 sys_timer_latch_l_07; + u32 sys_timer_latch_h_07; + u32 sys_timer_latch_l_08; + u32 sys_timer_latch_h_08; + u32 sys_timer_latch_l_09; + u32 sys_timer_latch_h_09; + u32 sys_timer_latch_l_10; + u32 sys_timer_latch_h_10; + u32 sys_timer_latch_l_11; + u32 sys_timer_latch_h_11; + u32 sys_timer_latch_l_12; + u32 sys_timer_latch_h_12; + u32 sys_timer_latch_l_13; + u32 sys_timer_latch_h_13; + u32 sys_timer_latch_l_14; + u32 sys_timer_latch_h_14; + u32 sys_timer_latch_l_15; + u32 sys_timer_latch_h_15; u32 pcm_timer_val; u32 pcm_timer_out; u32 spm_counter[3]; u32 pcm_wdt_val; u32 pcm_wdt_out; - u32 pcm_apwdt_latch_20[19]; - u8 reserved18[4]; + u32 reserved19[20]; u32 spm_sw_flag_0; u32 spm_sw_debug_0; u32 spm_sw_flag_1; u32 spm_sw_debug_1; - u32 spm_sw_rsv[9]; + u32 spm_sw_rsv_0; + u32 spm_sw_rsv_1; + u32 spm_sw_rsv_2; + u32 spm_sw_rsv_3; + u32 spm_sw_rsv_4; + u32 spm_sw_rsv_5; + u32 spm_sw_rsv_6; + u32 spm_sw_rsv_7; + u32 spm_sw_rsv_8; u32 spm_bk_wake_event; u32 spm_bk_vtcxo_dur; u32 spm_bk_wake_misc; u32 spm_bk_pcm_timer; - u8 reserved19[12]; + u32 reserved20[3]; u32 spm_rsv_con_0; u32 spm_rsv_con_1; u32 spm_rsv_sta_0; @@ -680,12 +869,25 @@ u32 spm_sw_debug_2; u32 spm_dv_con_0; u32 spm_dv_con_1; - u8 reserved20[8]; - u32 spm_sema_m[8]; + u32 reserved21[2]; + u32 spm_sema_m0; + u32 spm_sema_m1; + u32 spm_sema_m2; + u32 spm_sema_m3; + u32 spm_sema_m4; + u32 spm_sema_m5; + u32 spm_sema_m6; + u32 spm_sema_m7; u32 spm2adsp_mailbox; u32 adsp2spm_mailbox; - u32 spm2pmcu_mailbox[4]; - u32 pmcu2spm_mailbox[4]; + u32 spm2pmcu_mailbox_0; + u32 spm2pmcu_mailbox_1; + u32 spm2pmcu_mailbox_2; + u32 spm2pmcu_mailbox_3; + u32 pmcu2spm_mailbox_0; + u32 pmcu2spm_mailbox_1; + u32 pmcu2spm_mailbox_2; + u32 pmcu2spm_mailbox_3; u32 spm2scp_mailbox; u32 scp2spm_mailbox; u32 scp_aov_bus_con; @@ -693,7 +895,7 @@ u32 vcore_rtff_ctrl_mask_set; u32 vcore_rtff_ctrl_mask_clr; u32 spm_sram_srclkeno_mask; - u8 reserved21[256]; + u32 reserved22[64]; u32 spm_wakeup_sta; u32 spm_wakeup_ext_sta; u32 spm_wakeup_event_mask; @@ -701,26 +903,389 @@ u32 spm_wakeup_event_sens; u32 spm_wakeup_event_clear; u32 spm_src_req; - u32 spm_src_mask[12]; - u32 spm_req_sta[12]; + u32 spm_src_mask_0; + u32 spm_src_mask_1; + u32 spm_src_mask_2; + u32 spm_src_mask_3; + u32 spm_src_mask_4; + u32 spm_src_mask_5; + u32 spm_src_mask_6; + u32 spm_src_mask_7; + u32 spm_src_mask_8; + u32 spm_src_mask_9; + u32 spm_src_mask_10; + u32 spm_src_mask_11; + u32 spm_src_mask_12; + u32 spm_src_mask_13; + u32 spm_src_mask_14; + u32 spm_src_mask_15; + u32 spm_src_mask_16; + u32 spm_req_sta_0; + u32 spm_req_sta_1; + u32 spm_req_sta_2; + u32 spm_req_sta_3; + u32 spm_req_sta_4; + u32 spm_req_sta_5; + u32 spm_req_sta_6; + u32 spm_req_sta_7; + u32 spm_req_sta_8; + u32 spm_req_sta_9; + u32 spm_req_sta_10; + u32 spm_req_sta_11; + u32 spm_req_sta_12; + u32 spm_req_sta_13; + u32 spm_req_sta_14; + u32 spm_req_sta_15; + u32 spm_req_sta_16; u32 spm_ipc_wakeup_req; u32 ipc_wakeup_req_mask_sta; u32 spm_event_con_misc; u32 ddren_dbc_con; - u32 spm_resource_ack_con[2]; - u32 spm_resource_ack_mask[9]; + u32 spm_resource_ack_con_0; + u32 spm_resource_ack_con_1; + u32 spm_resource_ack_mask_0; + u32 spm_resource_ack_mask_1; + u32 spm_resource_ack_mask_2; + u32 spm_resource_ack_mask_3; + u32 spm_resource_ack_mask_4; + u32 spm_resource_ack_mask_5; + u32 spm_resource_ack_mask_6; + u32 spm_resource_ack_mask_7; + u32 spm_resource_ack_mask_8; + u32 spm_resource_ack_mask_9; + u32 spm_resource_ack_mask_10; + u32 spm_resource_ack_mask_11; + u32 spm_resource_ack_mask_12; u32 spm_event_counter_clear; u32 spm_vcore_event_count_sta; u32 spm_pmic_event_count_sta; - u32 spm_srcclkena_event_count_sta; + u32 spm_srclkena_event_count_sta; u32 spm_infra_event_count_sta; u32 spm_vrf18_event_count_sta; u32 spm_emi_event_count_sta; u32 spm_apsrc_event_count_sta; u32 spm_ddren_event_count_sta; - u32 pcm_wdt_latch[39]; - u32 pcm_wdt_latch_spare[10]; - u32 dramc_gating_err_latch[6]; + u32 spm_src_mask_17; + u32 spm_src_mask_18; + u32 spm_resource_ack_mask_13; + u32 spm_resource_ack_mask_14; + u32 spm_req_sta_17; + u32 spm_req_sta_18; + u32 reserved23[53]; + u32 md32pcm_cfgreg_sw_rstn; + u32 reserved24[127]; + u32 md32pcm_dma0_src; + u32 md32pcm_dma0_dst; + u32 md32pcm_dma0_wppt; + u32 md32pcm_dma0_wpto; + u32 md32pcm_dma0_count; + u32 md32pcm_dma0_con; + u32 md32pcm_dma0_start; + u32 reserved25[2]; + u32 md32pcm_dma0_rlct; + u32 reserved26[118]; + u32 md1_pwr_con; + u32 conn_pwr_con; + u32 apifr_io_pwr_con; + u32 apifr_mem_pwr_con; + u32 peri_pwr_con; + u32 peri_ether_pwr_con; + u32 ssusb_dp_phy_p0_pwr_con; + u32 ssusb_p0_pwr_con; + u32 ssusb_p1_pwr_con; + u32 ssusb_p23_pwr_con; + u32 ssusb_phy_p2_pwr_con; + u32 ufs0_pwr_con; + u32 ufs0_phy_pwr_con; + u32 pextp_mac0_pwr_con; + u32 pextp_mac1_pwr_con; + u32 pextp_mac2_pwr_con; + u32 pextp_phy0_pwr_con; + u32 pextp_phy1_pwr_con; + u32 pextp_phy2_pwr_con; + u32 audio_pwr_con; + u32 adsp_core1_pwr_con; + u32 adsp_top_pwr_con; + u32 adsp_infra_pwr_con; + u32 adsp_ao_pwr_con; + u32 mm_proc_pwr_con; + u32 scp_pwr_con; + u32 dpm0_pwr_con; + u32 dpm1_pwr_con; + u32 dpm2_pwr_con; + u32 dpm3_pwr_con; + u32 emi0_pwr_con; + u32 emi1_pwr_con; + u32 emi_infra_pwr_con; + u32 ssrsys_pwr_con; + u32 spu_ise_pwr_con; + u32 spu_hwrot_pwr_con; + u32 vlp_pwr_con; + u32 hsgmii0_pwr_con; + u32 hsgmii1_pwr_con; + u32 mfg_vlp_pwr_con; + u32 mcusys_busblk_pwr_con; + u32 cpueb_pwr_con; + u32 mfg0_pwr_con; + u32 adsp_hre_sram_con; + u32 ccu_sleep_sram_con; + u32 efuse_sram_con; + u32 emi_hre_sram_con; + u32 infra_hre_sram_con; + u32 infra_sleep_sram_con; + u32 mml_hre_sram_con; + u32 mm_hre_sram_con; + u32 mm_infra_ao_pdn_sram_con; + u32 nth_emi_slb_sram_con; + u32 peri_sleep_sram_con; + u32 spm_sram_con; + u32 spu_hwrot_sleep_sram_con; + u32 spu_ise_sleep_sram_con; + u32 sspm_sram_con; + u32 ssr_sleep_sram_con; + u32 sth_emi_slb_sram_con; + u32 ufs_sleep_sram_con; + u32 unipro_pdn_sram_con; + u32 cpu_buck_iso_con; + u32 md_buck_iso_con; + u32 soc_buck_iso_con; + u32 reserved27[2]; + u32 soc_buck_iso_con_set; + u32 soc_buck_iso_con_clr; + u32 pwr_status; + u32 pwr_status_2nd; + u32 pwr_status_msb; + u32 pwr_status_msb_2nd; + u32 xpu_pwr_status; + u32 xpu_pwr_status_2nd; + u32 dfd_soc_pwr_latch; + u32 nth_emi_slb_sram_ack; + u32 sth_emi_slb_sram_ack; + u32 dpyd0_pwr_con; + u32 dpyd1_pwr_con; + u32 dpyd2_pwr_con; + u32 dpyd3_pwr_con; + u32 dpya0_pwr_con; + u32 dpya1_pwr_con; + u32 dpya2_pwr_con; + u32 reserved28[2]; + u32 dpya3_pwr_con; + u32 scp_2_pwr_con; + u32 rsv_0_sleep_sram_con; + u32 rsv_1_sleep_sram_con; + u32 apifr_mem_sleep_sram_con; + u32 rsv_0_pwr_con; + u32 rsv_1_pwr_con; + u32 reserved29[22]; + u32 spm_twam_con; + u32 spm_twam_window_len; + u32 spm_twam_idle_sel; + u32 spm_twam_last_sta_0; + u32 spm_twam_last_sta_1; + u32 spm_twam_last_sta_2; + u32 spm_twam_last_sta_3; + u32 spm_twam_curr_sta_0; + u32 spm_twam_curr_sta_1; + u32 spm_twam_curr_sta_2; + u32 spm_twam_curr_sta_3; + u32 spm_twam_timer_out; + u32 reserved30[8192]; + u32 md1_ssyspm_con; + u32 conn_ssyspm_con; + u32 apifr_io_ssyspm_con; + u32 apifr_mem_ssyspm_con; + u32 peri_ssyspm_con; + u32 peri_ether_ssyspm_con; + u32 ssusb_dp_phy_p0_ssyspm_con; + u32 ssusb_p0_ssyspm_con; + u32 ssusb_p1_ssyspm_con; + u32 ssusb_p23_ssyspm_con; + u32 ssusb_phy_p2_ssyspm_con; + u32 ufs0_ssyspm_con; + u32 ufs0_phy_ssyspm_con; + u32 pextp_mac0_ssyspm_con; + u32 pextp_mac1_ssyspm_con; + u32 pextp_mac2_ssyspm_con; + u32 pextp_phy0_ssyspm_con; + u32 pextp_phy1_ssyspm_con; + u32 pextp_phy2_ssyspm_con; + u32 audio_ssyspm_con; + u32 adsp_core1_ssyspm_con; + u32 adsp_top_ssyspm_con; + u32 adsp_infra_ssyspm_con; + u32 adsp_ao_ssyspm_con; + u32 mm_proc_ssyspm_con; + u32 scp_ssyspm_con; + u32 scp_2_ssyspm_con; + u32 dpyd0_ssyspm_con; + u32 dpyd1_ssyspm_con; + u32 dpyd2_ssyspm_con; + u32 dpyd3_ssyspm_con; + u32 dpya0_ssyspm_con; + u32 dpya1_ssyspm_con; + u32 dpya2_ssyspm_con; + u32 dpya3_ssyspm_con; + u32 dpm0_ssyspm_con; + u32 dpm1_ssyspm_con; + u32 dpm2_ssyspm_con; + u32 dpm3_ssyspm_con; + u32 emi0_ssyspm_con; + u32 emi1_ssyspm_con; + u32 emi_infra_ssyspm_con; + u32 ssrsys_ssyspm_con; + u32 spu_ise_ssyspm_con; + u32 spu_hwrot_ssyspm_con; + u32 vlp_ssyspm_con; + u32 hsgmii0_ssyspm_con; + u32 hsgmii1_ssyspm_con; + u32 mfg_vlp_ssyspm_con; + u32 mcusys_busblk_ssyspm_con; + u32 rsv_0_ssyspm_con; + u32 rsv_1_ssyspm_con; + u32 cpueb_ssyspm_con; + u32 mfg0_ssyspm_con; + u32 bus_protect_con; + u32 bus_protect_con_set; + u32 bus_protect_con_clr; + u32 bus_protect_msb_con; + u32 bus_protect_msb_con_set; + u32 bus_protect_msb_con_clr; + u32 bus_protect_cg_con; + u32 bus_protect_cg_con_set; + u32 bus_protect_cg_con_clr; + u32 bus_protect_cg_msb_con; + u32 ocla_en; + u32 ocla_sw_rst; + u32 ocla_config_0; + u32 ocla_cand_mux_sel; + u32 ocla_sleep_sram_con; + u32 ocla_comp_val; + u32 ocla_vcore_req_sel; + u32 ocla_vcore_ack_sel; + u32 ocla_pmic_req_sel; + u32 ocla_pmic_ack_sel; + u32 ocla_26m_req_sel; + u32 ocla_26m_ack_sel; + u32 ocla_infra_req_sel; + u32 ocla_infra_ack_sel; + u32 ocla_buspll_req_sel; + u32 ocla_buspll_ack_sel; + u32 ocla_emi_req_sel; + u32 ocla_emi_ack_sel; + u32 ocla_apsrc_req_sel; + u32 ocla_apsrc_ack_sel; + u32 ocla_ddren_req_sel; + u32 ocla_ddren_ack_sel; + u32 ocla_mtcmos_pwr_on_sel; + u32 ocla_mtcmos_pwr_ack_sel; + u32 ocla_mon_mode_0; + u32 ocla_mon_mode_1; + u32 ocla_bit_seq_0; + u32 ocla_bit_seq_1; + u32 ocla_bit_en; + u32 ocla_timer_lsb; + u32 ocla_timer_msb; + u32 ocla_trig_addr; + u32 ocla_sta; + u32 ocla_level_max_time; + u32 ocla_rsv_0; + u32 ocla_rsv_1; + u32 ocla_rsv_2; + u32 ocla_rsv_3; + u32 ocla_rsv_4; + u32 ocla_rsv_5; + u32 reserved39[24]; + u32 bus_protect_cg_msb_con_set; + u32 bus_protect_cg_msb_con_clr; + u32 bus_protect_rdy; + u32 bus_protect_rdy_msb; + u32 spm_rsv_ulposc_req; + u32 spm_sw_rsv_vcore_req_con; + u32 spm_sw_rsv_vcore_req_con_set; + u32 spm_sw_rsv_vcore_req_con_clr; + u32 spm_lteclksq_bg_off; + u32 reserved31[55]; + u32 pbus_vcore_pkt_ctrl; + u32 pbus_vlp_pkt_ctrl; + u32 reserved32[2]; + u32 pbus_vlp_pkt_data_0; + u32 pbus_vlp_pkt_data_1; + u32 pbus_vlp_pkt_data_2; + u32 pbus_vlp_pkt_data_3; + u32 pbus_vcore_pkt_data_0; + u32 pbus_vcore_pkt_data_1; + u32 pbus_vcore_pkt_data_2; + u32 pbus_vcore_pkt_data_3; + u32 pbus_vcore_ctrl; + u32 pbus_vlp_ctrl; + u32 reserved33[2]; + u32 pbus_vcore_rx_pkt_ctrl; + u32 pbus_vlp_rx_pkt_ctrl; + u32 reserved34[2]; + u32 pbus_vlp_rx_pkt_data_0; + u32 pbus_vlp_rx_pkt_data_1; + u32 pbus_vlp_rx_pkt_data_2; + u32 pbus_vlp_rx_pkt_data_3; + u32 pbus_vcore_rx_pkt_data_0; + u32 pbus_vcore_rx_pkt_data_1; + u32 pbus_vcore_rx_pkt_data_2; + u32 pbus_vcore_rx_pkt_data_3; + u32 reserved35[100]; + u32 pcm_wdt_latch_0; + u32 pcm_wdt_latch_1; + u32 pcm_wdt_latch_2; + u32 pcm_wdt_latch_3; + u32 pcm_wdt_latch_4; + u32 pcm_wdt_latch_5; + u32 pcm_wdt_latch_6; + u32 pcm_wdt_latch_7; + u32 pcm_wdt_latch_8; + u32 pcm_wdt_latch_9; + u32 pcm_wdt_latch_10; + u32 pcm_wdt_latch_11; + u32 pcm_wdt_latch_12; + u32 pcm_wdt_latch_13; + u32 pcm_wdt_latch_14; + u32 pcm_wdt_latch_15; + u32 pcm_wdt_latch_16; + u32 pcm_wdt_latch_17; + u32 pcm_wdt_latch_18; + u32 pcm_wdt_latch_19; + u32 pcm_wdt_latch_20; + u32 pcm_wdt_latch_21; + u32 pcm_wdt_latch_22; + u32 pcm_wdt_latch_23; + u32 pcm_wdt_latch_24; + u32 pcm_wdt_latch_25; + u32 pcm_wdt_latch_26; + u32 pcm_wdt_latch_27; + u32 pcm_wdt_latch_28; + u32 pcm_wdt_latch_29; + u32 pcm_wdt_latch_30; + u32 pcm_wdt_latch_31; + u32 pcm_wdt_latch_32; + u32 pcm_wdt_latch_33; + u32 pcm_wdt_latch_34; + u32 pcm_wdt_latch_35; + u32 pcm_wdt_latch_36; + u32 pcm_wdt_latch_37; + u32 pcm_wdt_latch_38; + u32 pcm_wdt_latch_spare_0; + u32 pcm_wdt_latch_spare_1; + u32 pcm_wdt_latch_spare_2; + u32 pcm_wdt_latch_spare_3; + u32 pcm_wdt_latch_spare_4; + u32 pcm_wdt_latch_spare_5; + u32 pcm_wdt_latch_spare_6; + u32 pcm_wdt_latch_spare_7; + u32 pcm_wdt_latch_spare_8; + u32 pcm_wdt_latch_spare_9; + u32 dramc_gating_err_latch_0; + u32 dramc_gating_err_latch_1; + u32 dramc_gating_err_latch_2; + u32 dramc_gating_err_latch_3; + u32 dramc_gating_err_latch_4; + u32 dramc_gating_err_latch_5; u32 dramc_gating_err_latch_spare_0; u32 spm_debug_con; u32 spm_ack_chk_con_0; @@ -739,152 +1304,72 @@ u32 spm_ack_chk_sel_3; u32 spm_ack_chk_timer_3; u32 spm_ack_chk_sta_3; - u32 md32pcm_cfgreg_sw_rstn; - u8 reserved22[508]; - u32 md32pcm_dma0_src; - u32 md32pcm_dma0_dst; - u32 md32pcm_dma0_wppt; - u32 md32pcm_dma0_wpto; - u32 md32pcm_dma0_count; - u32 md32pcm_dma0_con; - u32 md32pcm_dma0_start; - u8 reserved23[8]; - u32 md32pcm_dma0_rlct; - u8 reserved24[276]; - u32 md32pcm_intc_irq_raw_sta; - u8 reserved25[192]; - u32 md1_pwr_con; - u32 conn_pwr_con; - u32 ifr_pwr_con; - u32 peri_pwr_con; - u32 peri_usb0_pwr_con; - u32 ufs0_pwr_con; - u32 ufs0_phy_pwr_con; - u32 pextp_mac0_pwr_con; - u32 pextp_mac1_pwr_con; - u32 pextp_phy0_pwr_con; - u32 pextp_phy1_pwr_con; - u32 audio_pwr_con; - u32 adsp_core1_pwr_con; - u32 adsp_top_pwr_con; - u32 adsp_infra_pwr_con; - u32 adsp_ao_pwr_con; - u32 isp_traw_pwr_con; - u32 isp_dip1_pwr_con; - u32 isp_main_pwr_con; - u32 isp_vcore_pwr_con; - u32 vde0_pwr_con; - u32 vde1_pwr_con; - u32 vde_vcore0_pwr_con; - u32 vde_vcore1_pwr_con; - u32 ven0_pwr_con; - u32 ven1_pwr_con; - u32 ven2_pwr_con; - u32 cam_mraw_pwr_con; - u32 cam_suba_pwr_con; - u32 cam_subb_pwr_con; - u32 cam_subc_pwr_con; - u32 cam_main_pwr_con; - u32 cam_vcore_pwr_con; - u32 cam_ccu_pwr_con; - u32 cam_ccu_ao_pwr_con; - u32 disp_vcore_pwr_con; - u32 mml0_pwr_con; - u32 mml1_pwr_con; - u32 dis0_pwr_con; - u32 dis1_pwr_con; - u32 ovl0_pwr_con; - u32 ovl1_pwr_con; - u32 mm_infra_pwr_con; - u32 mm_proc_pwr_con; - u32 dp_tx_pwr_con; - u32 scp_pwr_con; - u32 dpyd0_pwr_con; - u32 dpyd1_pwr_con; - u32 dpyd2_pwr_con; - u32 dpyd3_pwr_con; - u32 dpya0_pwr_con; - u32 dpya1_pwr_con; - u32 dpya2_pwr_con; - u32 dpya3_pwr_con; - u32 dpm0_pwr_con; - u32 dpm1_pwr_con; - u32 dpm2_pwr_con; - u32 dpm3_pwr_con; - u32 emi0_pwr_con; - u32 emi1_pwr_con; - u32 cpueb_pwr_con; - u32 csi_rx_pwr_con; - u32 ssrsys_pwr_con; - u32 spu_ise_pwr_con; - u32 spu_hwrot_pwr_con; - u32 mfg0_pwr_con; - u32 unipro_pdn_sram_con; - u32 ufs_sleep_sram_con; - u32 ccu_sleep_sram_con; - u32 mm_infra_ao_pdn_sram_con; - u32 infra_sleep_sram_con; - u32 peri_sleep_sram_con; - u32 nth_emi_slb_sram_con; - u32 nth_emi_slb_sram_ack; - u32 sth_emi_slb_sram_con; - u32 sth_emi_slb_sram_ack; - u32 ssr_sleep_sram_con; - u32 spu_ise_sleep_sram_con; - u32 spu_hwrot_sleep_sram_con; - u32 infra_hre_sram_con; - u32 emi_hre_sram_con; - u32 mm_hre_sram_con; - u32 mml_hre_sram_con; - u32 adsp_hre_sram_con; - u32 efuse_sram_con; - u32 spm_sram_con; - u32 sspm_sram_con; - u32 cpu_buck_iso_con; - u32 md_buck_iso_con; - u32 soc_buck_iso_con; - u32 soc_buck_iso_con_set; - u32 soc_buck_iso_con_clr; - u32 pwr_status; - u32 pwr_status_2nd; - u32 pwr_status_msb; - u32 pwr_status_msb_2nd; - u32 xpu_pwr_status; - u32 xpu_pwr_status_2nd; - u32 dfd_soc_pwr_latch; - u8 reserved26[68]; - u32 spm_twam_con; - u32 spm_twam_window_len; - u32 spm_twam_idle_sel; - u32 spm_twam_last_sta[4]; - u32 spm_twam_curr_sta[4]; - u32 spm_twam_timer_out; + u32 reserved36[3]; + u32 pcm_apwdt_latch_0; + u32 pcm_apwdt_latch_1; + u32 pcm_apwdt_latch_2; + u32 pcm_apwdt_latch_3; + u32 pcm_apwdt_latch_4; + u32 pcm_apwdt_latch_5; + u32 pcm_apwdt_latch_6; + u32 pcm_apwdt_latch_7; + u32 pcm_apwdt_latch_8; + u32 pcm_apwdt_latch_9; + u32 pcm_apwdt_latch_10; + u32 pcm_apwdt_latch_11; + u32 pcm_apwdt_latch_12; + u32 pcm_apwdt_latch_13; + u32 pcm_apwdt_latch_14; + u32 pcm_apwdt_latch_15; + u32 pcm_apwdt_latch_16; + u32 pcm_apwdt_latch_17; + u32 pcm_apwdt_latch_18; + u32 pcm_apwdt_latch_19; + u32 pcm_apwdt_latch_20; + u32 pcm_apwdt_latch_21; + u32 pcm_apwdt_latch_22; + u32 pcm_apwdt_latch_23; + u32 pcm_apwdt_latch_24; + u32 pcm_apwdt_latch_25; + u32 pcm_apwdt_latch_26; + u32 reserved37[2]; + u32 pcm_apwdt_latch_27; + u32 pcm_apwdt_latch_28; + u32 pcm_apwdt_latch_29; + u32 pcm_apwdt_latch_30; + u32 pcm_apwdt_latch_31; + u32 pcm_apwdt_latch_32; + u32 pcm_apwdt_latch_33; + u32 pcm_apwdt_latch_34; + u32 pcm_apwdt_latch_35; + u32 pcm_apwdt_latch_36; + u32 pcm_apwdt_latch_37; + u32 pcm_apwdt_latch_38; }; check_member(mtk_spm_regs, spm_wakeup_misc, 0x140); check_member(mtk_spm_regs, spm_mcupm_spmc_con, 0x288); check_member(mtk_spm_regs, spm_dpm_wb_con, 0x2ac); check_member(mtk_spm_regs, spm_pwrap_cmd[31], 0x38c); -check_member(mtk_spm_regs, spm_dpsw_con, 0x3b8); +check_member(mtk_spm_regs, spm_dpsw_con, 0x3d0); check_member(mtk_spm_regs, spm2emi_pdn_ctrl, 0x440); +check_member(mtk_spm_regs, reg_module_busy_vcore_req_mask, 0x4F4); +check_member(mtk_spm_regs, sys_timer_con, 0x500); check_member(mtk_spm_regs, pcm_wdt_out, 0x5ac); check_member(mtk_spm_regs, spm_sram_srclkeno_mask, 0x6fc); -check_member(mtk_spm_regs, spm_vcore_event_count_sta, 0x8bc); -check_member(mtk_spm_regs, spm_ack_chk_sta_3, 0x9fc); +check_member(mtk_spm_regs, spm_vcore_event_count_sta, 0x8f4); check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xa00); check_member(mtk_spm_regs, md32pcm_dma0_src, 0xc00); check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24); -check_member(mtk_spm_regs, soc_buck_iso_con, 0xf64); +check_member(mtk_spm_regs, soc_buck_iso_con, 0xf00); check_member(mtk_spm_regs, spm_twam_timer_out, 0xffc); +check_member(mtk_spm_regs, spm_lteclksq_bg_off, 0x9220); +check_member(mtk_spm_regs, pbus_vcore_pkt_ctrl, 0x9300); +check_member(mtk_spm_regs, pbus_vlp_pkt_data_3, 0x931C); +check_member(mtk_spm_regs, pbus_vcore_rx_pkt_data_3, 0x936C); +check_member(mtk_spm_regs, pcm_wdt_latch_0, 0x9500); +check_member(mtk_spm_regs, spm_ack_chk_sta_3, 0x9620); -static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; - -static const struct power_domain_data disp[] = { - /* TODO: add disp power domains */ -}; - -static const struct power_domain_data audio[] = { - /* TODO: add audio power domains */ -}; +static struct mtk_spm_regs *const mtk_spm = (void *)SCP_BASE; #endif /* SOC_MEDIATEK_MT8196_SPM_H */ diff --git a/src/soc/mediatek/mt8196/spm.c b/src/soc/mediatek/mt8196/spm.c new file mode 100644 index 0000000..442603b --- /dev/null +++ b/src/soc/mediatek/mt8196/spm.c @@ -0,0 +1,904 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <assert.h> +#include <delay.h> +#include <soc/mcu_common.h> +#include <soc/pll.h> +#include <soc/spm.h> + +struct mtk_vlpcksys_regs { + u32 reserved0[136]; + u32 vlp_clksq_con1; + u32 reserved1[15]; + u32 vlp_ap_pll_con3; +}; +check_member(mtk_vlpcksys_regs, vlp_clksq_con1, 0x220); +check_member(mtk_vlpcksys_regs, vlp_ap_pll_con3, 0x260); + + +struct mtk_vlpdevapc_regs { + u32 vlp_ao_mas_sec_0; + u32 reserved0[319]; + u32 vlp_ao_apc_con; +}; +check_member(mtk_vlpdevapc_regs, vlp_ao_apc_con, 0x500); + +/* TODO: replace with common regs structure if they have been defined */ +static struct mtk_vlpcksys_regs *const mtk_vlpcksys = (void *)VLP_CKSYS_BASE; +static struct mtk_vlpdevapc_regs *const mtk_vlpdevapc = (void *)VLP_DEVAPC_BASE; + +unsigned int mt_spm_version; + +#define SPM_INIT_PCM_FLAG (SPM_FLAG_DISABLE_VCORE_DVS\ + | SPM_FLAG_DISABLE_DDR_DFS\ + | SPM_FLAG_DISABLE_EMI_DFS\ + | SPM_FLAG_DISABLE_BUS_DFS\ + | SPM_FLAG_RUN_COMMON_SCENARIO\ + | SPM_FLAG_ENABLE_MT8196_ES_WA\ + | SPM_FLAG_ENABLE_MT8196_EMI_ES_WA) + +static struct pwr_ctrl spm_init_ctrl = { + /* SPM_SRC_REQ */ + .reg_spm_adsp_mailbox_req = 0, + .reg_spm_apsrc_req = 1, + .reg_spm_ddren_req = 0, + .reg_spm_dvfs_req = 0, + .reg_spm_emi_req = 0, + .reg_spm_f26m_req = 0, + .reg_spm_infra_req = 0, + .reg_spm_pmic_req = 0, + .reg_spm_scp_mailbox_req = 0, + .reg_spm_sspm_mailbox_req = 0, + .reg_spm_sw_mailbox_req = 0, + .reg_spm_vcore_req = 1, + .reg_spm_vrf18_req = 0, + .adsp_mailbox_state = 0, + .apsrc_state = 0, + .ddren_state = 0, + .dvfs_state = 0, + .emi_state = 0, + .f26m_state = 0, + .infra_state = 0, + .pmic_state = 0, + .scp_mailbox_state = 0, + .sspm_mailbox_state = 0, + .sw_mailbox_state = 0, + .vcore_state = 0, + .vrf18_state = 0, + + /* SPM_SRC_MASK_0 */ + .reg_apu_apsrc_req_mask_b = 1, + .reg_apu_ddren_req_mask_b = 1, + .reg_apu_emi_req_mask_b = 1, + .reg_apu_infra_req_mask_b = 1, + .reg_apu_pmic_req_mask_b = 1, + .reg_apu_srcclkena_mask_b = 1, + .reg_apu_vrf18_req_mask_b = 1, + .reg_audio_dsp_apsrc_req_mask_b = 1, + .reg_audio_dsp_ddren_req_mask_b = 1, + .reg_audio_dsp_emi_req_mask_b = 1, + .reg_audio_dsp_infra_req_mask_b = 1, + .reg_audio_dsp_pmic_req_mask_b = 1, + .reg_audio_dsp_srcclkena_mask_b = 1, + .reg_audio_dsp_vcore_req_mask_b = 1, + .reg_audio_dsp_vrf18_req_mask_b = 1, + .reg_cam_apsrc_req_mask_b = 1, + .reg_cam_ddren_req_mask_b = 1, + .reg_cam_emi_req_mask_b = 1, + .reg_cam_infra_req_mask_b = 1, + .reg_cam_pmic_req_mask_b = 1, + .reg_cam_srcclkena_mask_b = 1, + .reg_cam_vrf18_req_mask_b = 1, + + /* SPM_SRC_MASK_1 */ + .reg_ccif_apsrc_req_mask_b = 0xfff, + .reg_ccif_emi_req_mask_b = 0xfff, + .reg_vlpcfg_rsv0_apsrc_req_mask_b = 1, + .reg_vlpcfg_rsv0_ddren_req_mask_b = 1, + .reg_vlpcfg_rsv0_emi_req_mask_b = 1, + .reg_vlpcfg_rsv0_infra_req_mask_b = 1, + .reg_vlpcfg_rsv0_pmic_req_mask_b = 1, + .reg_vlpcfg_rsv0_srcclkena_mask_b = 1, + .reg_vlpcfg_rsv0_vcore_req_mask_b = 1, + .reg_vlpcfg_rsv0_vrf18_req_mask_b = 1, + + /* SPM_SRC_MASK_2 */ + .reg_ccif_infra_req_mask_b = 0xfff, + .reg_ccif_pmic_req_mask_b = 0xfff, + .reg_vlpcfg_rsv1_apsrc_req_mask_b = 1, + .reg_vlpcfg_rsv1_ddren_req_mask_b = 1, + .reg_vlpcfg_rsv1_emi_req_mask_b = 1, + .reg_vlpcfg_rsv1_infra_req_mask_b = 1, + .reg_vlpcfg_rsv1_pmic_req_mask_b = 1, + .reg_vlpcfg_rsv1_srcclkena_mask_b = 1, + .reg_vlpcfg_rsv1_vcore_req_mask_b = 1, + .reg_vlpcfg_rsv1_vrf18_req_mask_b = 1, + + /* SPM_SRC_MASK_3 */ + .reg_ccif_srcclkena_mask_b = 0xfff, + .reg_ccif_vrf18_req_mask_b = 0xfff, + .reg_ccu_apsrc_req_mask_b = 1, + .reg_ccu_ddren_req_mask_b = 1, + .reg_ccu_emi_req_mask_b = 1, + .reg_ccu_infra_req_mask_b = 1, + .reg_ccu_pmic_req_mask_b = 1, + .reg_ccu_srcclkena_mask_b = 1, + .reg_ccu_vrf18_req_mask_b = 1, + .reg_cg_check_apsrc_req_mask_b = 1, + + /* SPM_SRC_MASK_4 */ + .reg_cg_check_ddren_req_mask_b = 1, + .reg_cg_check_emi_req_mask_b = 1, + .reg_cg_check_infra_req_mask_b = 1, + .reg_cg_check_pmic_req_mask_b = 1, + .reg_cg_check_srcclkena_mask_b = 1, + .reg_cg_check_vcore_req_mask_b = 1, + .reg_cg_check_vrf18_req_mask_b = 1, + .reg_conn_apsrc_req_mask_b = 1, + .reg_conn_ddren_req_mask_b = 1, + .reg_conn_emi_req_mask_b = 1, + .reg_conn_infra_req_mask_b = 1, + .reg_conn_pmic_req_mask_b = 1, + .reg_conn_srcclkena_mask_b = 1, + .reg_conn_srcclkenb_mask_b = 1, + .reg_conn_vcore_req_mask_b = 1, + .reg_conn_vrf18_req_mask_b = 1, + .reg_cpueb_apsrc_req_mask_b = 1, + .reg_cpueb_ddren_req_mask_b = 1, + .reg_cpueb_emi_req_mask_b = 1, + .reg_cpueb_infra_req_mask_b = 1, + .reg_cpueb_pmic_req_mask_b = 1, + .reg_cpueb_srcclkena_mask_b = 1, + .reg_cpueb_vrf18_req_mask_b = 1, + .reg_disp0_apsrc_req_mask_b = 1, + .reg_disp0_ddren_req_mask_b = 1, + .reg_disp0_emi_req_mask_b = 1, + .reg_disp0_infra_req_mask_b = 1, + .reg_disp0_pmic_req_mask_b = 1, + .reg_disp0_srcclkena_mask_b = 1, + .reg_disp0_vrf18_req_mask_b = 1, + .reg_disp1_apsrc_req_mask_b = 1, + .reg_disp1_ddren_req_mask_b = 1, + + /* SPM_SRC_MASK_5 */ + .reg_disp1_emi_req_mask_b = 1, + .reg_disp1_infra_req_mask_b = 1, + .reg_disp1_pmic_req_mask_b = 1, + .reg_disp1_srcclkena_mask_b = 1, + .reg_disp1_vrf18_req_mask_b = 1, + .reg_dpm_apsrc_req_mask_b = 0xf, + .reg_dpm_ddren_req_mask_b = 0xf, + .reg_dpm_emi_req_mask_b = 0xf, + .reg_dpm_infra_req_mask_b = 0xf, + .reg_dpm_pmic_req_mask_b = 0xf, + .reg_dpm_srcclkena_mask_b = 0xf, + + /* SPM_SRC_MASK_6 */ + .reg_dpm_vcore_req_mask_b = 0xf, + .reg_dpm_vrf18_req_mask_b = 0xf, + .reg_dpmaif_apsrc_req_mask_b = 1, + .reg_dpmaif_ddren_req_mask_b = 1, + .reg_dpmaif_emi_req_mask_b = 1, + .reg_dpmaif_infra_req_mask_b = 1, + .reg_dpmaif_pmic_req_mask_b = 1, + .reg_dpmaif_srcclkena_mask_b = 1, + .reg_dpmaif_vrf18_req_mask_b = 1, + .reg_dvfsrc_level_req_mask_b = 1, + .reg_emisys_apsrc_req_mask_b = 0, + .reg_emisys_ddren_req_mask_b = 1, + .reg_emisys_emi_req_mask_b = 0, + .reg_gce_apsrc_req_mask_b = 1, + .reg_gce_ddren_req_mask_b = 1, + .reg_gce_emi_req_mask_b = 1, + .reg_gce_infra_req_mask_b = 1, + .reg_gce_pmic_req_mask_b = 1, + .reg_gce_srcclkena_mask_b = 1, + .reg_gce_vrf18_req_mask_b = 1, + .reg_gpueb_apsrc_req_mask_b = 1, + .reg_gpueb_ddren_req_mask_b = 1, + .reg_gpueb_emi_req_mask_b = 1, + .reg_gpueb_infra_req_mask_b = 1, + .reg_gpueb_pmic_req_mask_b = 1, + .reg_gpueb_srcclkena_mask_b = 1, + + /* SPM_SRC_MASK_7 */ + .reg_gpueb_vrf18_req_mask_b = 1, + .reg_hwccf_apsrc_req_mask_b = 1, + .reg_hwccf_ddren_req_mask_b = 1, + .reg_hwccf_emi_req_mask_b = 1, + .reg_hwccf_infra_req_mask_b = 1, + .reg_hwccf_pmic_req_mask_b = 1, + .reg_hwccf_srcclkena_mask_b = 1, + .reg_hwccf_vcore_req_mask_b = 1, + .reg_hwccf_vrf18_req_mask_b = 1, + .reg_img_apsrc_req_mask_b = 1, + .reg_img_ddren_req_mask_b = 1, + .reg_img_emi_req_mask_b = 1, + .reg_img_infra_req_mask_b = 1, + .reg_img_pmic_req_mask_b = 1, + .reg_img_srcclkena_mask_b = 1, + .reg_img_vrf18_req_mask_b = 1, + .reg_infrasys_apsrc_req_mask_b = 0, + .reg_infrasys_ddren_req_mask_b = 1, + .reg_infrasys_emi_req_mask_b = 0, + .reg_infrasys_infra_req_mask_b = 1, + .reg_infrasys_vrf18_req_mask_b = 1, + .reg_ipic_infra_req_mask_b = 1, + .reg_ipic_vrf18_req_mask_b = 1, + .reg_mcu_apsrc_req_mask_b = 1, + .reg_mcu_ddren_req_mask_b = 1, + .reg_mcu_emi_req_mask_b = 1, + .reg_mcu_infra_req_mask_b = 1, + .reg_mcu_pmic_req_mask_b = 1, + .reg_mcu_srcclkena_mask_b = 1, + .reg_mcu_vrf18_req_mask_b = 1, + .reg_md_apsrc_req_mask_b = 1, + .reg_md_ddren_req_mask_b = 1, + + /* SPM_SRC_MASK_8 */ + .reg_md_emi_req_mask_b = 1, + .reg_md_infra_req_mask_b = 1, + .reg_md_pmic_req_mask_b = 1, + .reg_md_srcclkena_mask_b = 1, + .reg_md_srcclkena1_mask_b = 1, + .reg_md_vcore_req_mask_b = 1, + .reg_md_vrf18_req_mask_b = 1, + .reg_mm_proc_apsrc_req_mask_b = 1, + .reg_mm_proc_ddren_req_mask_b = 1, + .reg_mm_proc_emi_req_mask_b = 1, + .reg_mm_proc_infra_req_mask_b = 1, + .reg_mm_proc_pmic_req_mask_b = 1, + .reg_mm_proc_srcclkena_mask_b = 1, + .reg_mm_proc_vrf18_req_mask_b = 1, + .reg_mml0_apsrc_req_mask_b = 1, + .reg_mml0_ddren_req_mask_b = 1, + .reg_mml0_emi_req_mask_b = 1, + .reg_mml0_infra_req_mask_b = 1, + .reg_mml0_pmic_req_mask_b = 1, + .reg_mml0_srcclkena_mask_b = 1, + .reg_mml0_vrf18_req_mask_b = 1, + .reg_mml1_apsrc_req_mask_b = 1, + .reg_mml1_ddren_req_mask_b = 1, + .reg_mml1_emi_req_mask_b = 1, + .reg_mml1_infra_req_mask_b = 1, + .reg_mml1_pmic_req_mask_b = 1, + .reg_mml1_srcclkena_mask_b = 1, + .reg_mml1_vrf18_req_mask_b = 1, + .reg_ovl0_apsrc_req_mask_b = 1, + .reg_ovl0_ddren_req_mask_b = 1, + .reg_ovl0_emi_req_mask_b = 1, + .reg_ovl0_infra_req_mask_b = 1, + + /* SPM_SRC_MASK_9 */ + .reg_ovl0_pmic_req_mask_b = 1, + .reg_ovl0_srcclkena_mask_b = 1, + .reg_ovl0_vrf18_req_mask_b = 1, + .reg_ovl1_apsrc_req_mask_b = 1, + .reg_ovl1_ddren_req_mask_b = 1, + .reg_ovl1_emi_req_mask_b = 1, + .reg_ovl1_infra_req_mask_b = 1, + .reg_ovl1_pmic_req_mask_b = 1, + .reg_ovl1_srcclkena_mask_b = 1, + .reg_ovl1_vrf18_req_mask_b = 1, + .reg_pcie0_apsrc_req_mask_b = 1, + .reg_pcie0_ddren_req_mask_b = 1, + .reg_pcie0_emi_req_mask_b = 1, + .reg_pcie0_infra_req_mask_b = 1, + .reg_pcie0_pmic_req_mask_b = 1, + .reg_pcie0_srcclkena_mask_b = 1, + .reg_pcie0_vcore_req_mask_b = 1, + .reg_pcie0_vrf18_req_mask_b = 1, + .reg_perisys_apsrc_req_mask_b = 1, + .reg_perisys_ddren_req_mask_b = 1, + .reg_perisys_emi_req_mask_b = 1, + .reg_perisys_infra_req_mask_b = 1, + .reg_perisys_pmic_req_mask_b = 1, + .reg_perisys_srcclkena_mask_b = 1, + .reg_perisys_vrf18_req_mask_b = 1, + .reg_scp_apsrc_req_mask_b = 1, + .reg_scp_ddren_req_mask_b = 1, + .reg_scp_emi_req_mask_b = 1, + .reg_scp_infra_req_mask_b = 1, + .reg_scp_pmic_req_mask_b = 1, + .reg_scp_srcclkena_mask_b = 1, + .reg_scp_vcore_req_mask_b = 1, + + /* SPM_SRC_MASK_10 */ + .reg_scp_vrf18_req_mask_b = 1, + .reg_spu_hwrot_apsrc_req_mask_b = 1, + .reg_spu_hwrot_ddren_req_mask_b = 1, + .reg_spu_hwrot_emi_req_mask_b = 1, + .reg_spu_hwrot_infra_req_mask_b = 1, + .reg_spu_hwrot_pmic_req_mask_b = 1, + .reg_spu_hwrot_srcclkena_mask_b = 1, + .reg_spu_hwrot_vrf18_req_mask_b = 1, + .reg_spu_ise_apsrc_req_mask_b = 1, + .reg_spu_ise_ddren_req_mask_b = 1, + .reg_spu_ise_emi_req_mask_b = 1, + .reg_spu_ise_infra_req_mask_b = 1, + .reg_spu_ise_pmic_req_mask_b = 1, + .reg_spu_ise_srcclkena_mask_b = 1, + .reg_spu_ise_vrf18_req_mask_b = 1, + .reg_srcclkeni_infra_req_mask_b = 3, + .reg_srcclkeni_pmic_req_mask_b = 3, + .reg_srcclkeni_srcclkena_mask_b = 3, + .reg_sspm_apsrc_req_mask_b = 1, + .reg_sspm_ddren_req_mask_b = 1, + .reg_sspm_emi_req_mask_b = 1, + .reg_sspm_infra_req_mask_b = 1, + .reg_sspm_pmic_req_mask_b = 1, + .reg_sspm_srcclkena_mask_b = 1, + .reg_sspm_vrf18_req_mask_b = 1, + .reg_ssrsys_apsrc_req_mask_b = 1, + .reg_ssrsys_ddren_req_mask_b = 1, + .reg_ssrsys_emi_req_mask_b = 1, + .reg_ssrsys_infra_req_mask_b = 1, + + /* SPM_SRC_MASK_11 */ + .reg_ssrsys_pmic_req_mask_b = 1, + .reg_ssrsys_srcclkena_mask_b = 1, + .reg_ssrsys_vrf18_req_mask_b = 1, + .reg_uart_hub_infra_req_mask_b = 1, + .reg_uart_hub_pmic_req_mask_b = 1, + .reg_uart_hub_srcclkena_mask_b = 1, + .reg_uart_hub_vcore_req_mask_b = 1, + .reg_uart_hub_vrf18_req_mask_b = 1, + .reg_ufs_apsrc_req_mask_b = 1, + .reg_ufs_ddren_req_mask_b = 1, + .reg_ufs_emi_req_mask_b = 1, + .reg_ufs_infra_req_mask_b = 1, + .reg_ufs_pmic_req_mask_b = 1, + .reg_ufs_srcclkena_mask_b = 1, + .reg_ufs_vrf18_req_mask_b = 1, + .reg_vdec_apsrc_req_mask_b = 1, + .reg_vdec_ddren_req_mask_b = 1, + .reg_vdec_emi_req_mask_b = 1, + .reg_vdec_infra_req_mask_b = 1, + .reg_vdec_pmic_req_mask_b = 1, + .reg_vdec_srcclkena_mask_b = 1, + .reg_vdec_vrf18_req_mask_b = 1, + .reg_venc_apsrc_req_mask_b = 1, + .reg_venc_ddren_req_mask_b = 1, + .reg_venc_emi_req_mask_b = 1, + .reg_venc_infra_req_mask_b = 1, + .reg_venc_pmic_req_mask_b = 1, + .reg_venc_srcclkena_mask_b = 1, + .reg_venc_vrf18_req_mask_b = 1, + + /* SPM_EVENT_CON_MISC */ + .reg_srcclken_fast_resp = 0, + .reg_csyspwrup_ack_mask = 0, + + /* SPM_WAKEUP_EVENT_MASK */ + .reg_wakeup_event_mask = 0xEFFFFFF7, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .reg_ext_wakeup_event_mask = 0xFFFFFFFF, + + /*sw flag setting */ + .pcm_flags = SPM_INIT_PCM_FLAG, +}; + +void spm_set_power_control(const struct pwr_ctrl *pwrctrl) +{ + /* SPM_SRC_REQ */ + write32(&mtk_spm->spm_src_req, + ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 0) | + ((pwrctrl->reg_spm_apsrc_req & 0x1) << 1) | + ((pwrctrl->reg_spm_ddren_req & 0x1) << 2) | + ((pwrctrl->reg_spm_dvfs_req & 0x1) << 3) | + ((pwrctrl->reg_spm_emi_req & 0x1) << 4) | + ((pwrctrl->reg_spm_f26m_req & 0x1) << 5) | + ((pwrctrl->reg_spm_infra_req & 0x1) << 6) | + ((pwrctrl->reg_spm_pmic_req & 0x1) << 7) | + ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 8) | + ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 9) | + ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 10) | + ((pwrctrl->reg_spm_vcore_req & 0x1) << 11) | + ((pwrctrl->reg_spm_vrf18_req & 0x1) << 12) | + ((pwrctrl->adsp_mailbox_state & 0x1) << 16) | + ((pwrctrl->apsrc_state & 0x1) << 17) | + ((pwrctrl->ddren_state & 0x1) << 18) | + ((pwrctrl->dvfs_state & 0x1) << 19) | + ((pwrctrl->emi_state & 0x1) << 20) | + ((pwrctrl->f26m_state & 0x1) << 21) | + ((pwrctrl->infra_state & 0x1) << 22) | + ((pwrctrl->pmic_state & 0x1) << 23) | + ((pwrctrl->scp_mailbox_state & 0x1) << 24) | + ((pwrctrl->sspm_mailbox_state & 0x1) << 25) | + ((pwrctrl->sw_mailbox_state & 0x1) << 26) | + ((pwrctrl->vcore_state & 0x1) << 27) | + ((pwrctrl->vrf18_state & 0x1) << 28)); + + /* SPM_SRC_MASK_0 */ + write32(&mtk_spm->spm_src_mask_0, + ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_apu_emi_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_apu_pmic_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_audio_dsp_emi_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_audio_dsp_pmic_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_audio_dsp_vcore_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_cam_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_cam_emi_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_cam_infra_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_cam_pmic_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_cam_srcclkena_mask_b & 0x1) << 20) | + ((pwrctrl->reg_cam_vrf18_req_mask_b & 0x1) << 21)); + + /* SPM_SRC_MASK_1 */ + write32(&mtk_spm->spm_src_mask_1, + ((pwrctrl->reg_ccif_apsrc_req_mask_b & 0xfff) << 0) | + ((pwrctrl->reg_ccif_emi_req_mask_b & 0xfff) << 12) | + ((pwrctrl->reg_vlpcfg_rsv0_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_vlpcfg_rsv0_ddren_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_vlpcfg_rsv0_emi_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_vlpcfg_rsv0_infra_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_vlpcfg_rsv0_pmic_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_vlpcfg_rsv0_srcclkena_mask_b & 0x1) << 29) | + ((pwrctrl->reg_vlpcfg_rsv0_vcore_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_vlpcfg_rsv0_vrf18_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_2 */ + write32(&mtk_spm->spm_src_mask_2, + ((pwrctrl->reg_ccif_infra_req_mask_b & 0xfff) << 0) | + ((pwrctrl->reg_ccif_pmic_req_mask_b & 0xfff) << 12) | + ((pwrctrl->reg_vlpcfg_rsv1_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_vlpcfg_rsv1_ddren_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_vlpcfg_rsv1_emi_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_vlpcfg_rsv1_infra_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_vlpcfg_rsv1_pmic_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_vlpcfg_rsv1_srcclkena_mask_b & 0x1) << 29) | + ((pwrctrl->reg_vlpcfg_rsv1_vcore_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_vlpcfg_rsv1_vrf18_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_3 */ + write32(&mtk_spm->spm_src_mask_3, + ((pwrctrl->reg_ccif_srcclkena_mask_b & 0xfff) << 0) | + ((pwrctrl->reg_ccif_vrf18_req_mask_b & 0xfff) << 12) | + ((pwrctrl->reg_ccu_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_ccu_ddren_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_ccu_emi_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_ccu_infra_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_ccu_pmic_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_ccu_srcclkena_mask_b & 0x1) << 29) | + ((pwrctrl->reg_ccu_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_4 */ + write32(&mtk_spm->spm_src_mask_4, + ((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_cg_check_emi_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_cg_check_infra_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_cg_check_pmic_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 4) | + ((pwrctrl->reg_cg_check_vcore_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_conn_emi_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_conn_pmic_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) | + ((pwrctrl->reg_conn_vcore_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_cpueb_ddren_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_cpueb_emi_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_cpueb_pmic_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 21) | + ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_disp0_emi_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_disp0_infra_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_disp0_pmic_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_disp0_srcclkena_mask_b & 0x1) << 28) | + ((pwrctrl->reg_disp0_vrf18_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_5 */ + write32(&mtk_spm->spm_src_mask_5, + ((pwrctrl->reg_disp1_emi_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_disp1_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_disp1_pmic_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_disp1_srcclkena_mask_b & 0x1) << 3) | + ((pwrctrl->reg_disp1_vrf18_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_dpm_apsrc_req_mask_b & 0xf) << 5) | + ((pwrctrl->reg_dpm_ddren_req_mask_b & 0xf) << 9) | + ((pwrctrl->reg_dpm_emi_req_mask_b & 0xf) << 13) | + ((pwrctrl->reg_dpm_infra_req_mask_b & 0xf) << 17) | + ((pwrctrl->reg_dpm_pmic_req_mask_b & 0xf) << 21) | + ((pwrctrl->reg_dpm_srcclkena_mask_b & 0xf) << 25)); + + /* SPM_SRC_MASK_6 */ + write32(&mtk_spm->spm_src_mask_6, + ((pwrctrl->reg_dpm_vcore_req_mask_b & 0xf) << 0) | + ((pwrctrl->reg_dpm_vrf18_req_mask_b & 0xf) << 4) | + ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_dpmaif_emi_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_dpmaif_pmic_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 13) | + ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_dvfsrc_level_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_emisys_apsrc_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_emisys_ddren_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_emisys_emi_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_gce_emi_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_gce_pmic_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_gce_srcclkena_mask_b & 0x1) << 24) | + ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_gpueb_apsrc_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_gpueb_ddren_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_gpueb_emi_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_gpueb_infra_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_gpueb_pmic_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_gpueb_srcclkena_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_7 */ + write32(&mtk_spm->spm_src_mask_7, + ((pwrctrl->reg_gpueb_vrf18_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_hwccf_apsrc_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_hwccf_ddren_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_hwccf_emi_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_hwccf_infra_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_hwccf_pmic_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_hwccf_srcclkena_mask_b & 0x1) << 6) | + ((pwrctrl->reg_hwccf_vcore_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_hwccf_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_img_apsrc_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_img_emi_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_img_infra_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_img_pmic_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_img_srcclkena_mask_b & 0x1) << 14) | + ((pwrctrl->reg_img_vrf18_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_infrasys_emi_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_infrasys_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_infrasys_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_ipic_infra_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_ipic_vrf18_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_mcu_apsrc_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_mcu_ddren_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_mcu_emi_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_mcu_infra_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_mcu_pmic_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_mcu_srcclkena_mask_b & 0x1) << 28) | + ((pwrctrl->reg_mcu_vrf18_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_md_apsrc_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_md_ddren_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_8 */ + write32(&mtk_spm->spm_src_mask_8, + ((pwrctrl->reg_md_emi_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_md_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_md_pmic_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_md_srcclkena_mask_b & 0x1) << 3) | + ((pwrctrl->reg_md_srcclkena1_mask_b & 0x1) << 4) | + ((pwrctrl->reg_md_vcore_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_md_vrf18_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_mm_proc_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_mm_proc_ddren_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_mm_proc_emi_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_mm_proc_infra_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_mm_proc_pmic_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_mm_proc_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_mm_proc_vrf18_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_mml0_apsrc_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_mml0_ddren_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_mml0_emi_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_mml0_infra_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_mml0_pmic_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_mml0_srcclkena_mask_b & 0x1) << 19) | + ((pwrctrl->reg_mml0_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_mml1_apsrc_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_mml1_ddren_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_mml1_emi_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_mml1_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_mml1_pmic_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_mml1_srcclkena_mask_b & 0x1) << 26) | + ((pwrctrl->reg_mml1_vrf18_req_mask_b & 0x1) << 27) | + (((u32)pwrctrl->reg_ovl0_apsrc_req_mask_b & 0x1) << 28) | + (((u32)pwrctrl->reg_ovl0_ddren_req_mask_b & 0x1) << 29) | + (((u32)pwrctrl->reg_ovl0_emi_req_mask_b & 0x1) << 30) | + (((u32)pwrctrl->reg_ovl0_infra_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_9 */ + write32(&mtk_spm->spm_src_mask_9, + ((pwrctrl->reg_ovl0_pmic_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_ovl0_srcclkena_mask_b & 0x1) << 1) | + ((pwrctrl->reg_ovl0_vrf18_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_ovl1_apsrc_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_ovl1_ddren_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_ovl1_emi_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_ovl1_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_ovl1_pmic_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_ovl1_srcclkena_mask_b & 0x1) << 8) | + ((pwrctrl->reg_ovl1_vrf18_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_pcie0_apsrc_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_pcie0_ddren_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_pcie0_emi_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_pcie0_infra_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_pcie0_pmic_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_pcie0_srcclkena_mask_b & 0x1) << 15) | + ((pwrctrl->reg_pcie0_vcore_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_pcie0_vrf18_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_perisys_apsrc_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_perisys_ddren_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_perisys_emi_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_perisys_infra_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_perisys_pmic_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_perisys_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_perisys_vrf18_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_scp_emi_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_scp_pmic_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 30) | + ((pwrctrl->reg_scp_vcore_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_10 */ + write32(&mtk_spm->spm_src_mask_10, + ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_spu_hwrot_apsrc_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_spu_hwrot_ddren_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_spu_hwrot_emi_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_spu_hwrot_infra_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_spu_hwrot_pmic_req_mask_b & 0x1) << 5) | + ((pwrctrl->reg_spu_hwrot_srcclkena_mask_b & 0x1) << 6) | + ((pwrctrl->reg_spu_hwrot_vrf18_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_spu_ise_apsrc_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_spu_ise_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_spu_ise_emi_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_spu_ise_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_spu_ise_pmic_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_spu_ise_srcclkena_mask_b & 0x1) << 13) | + ((pwrctrl->reg_spu_ise_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x3) << 15) | + ((pwrctrl->reg_srcclkeni_pmic_req_mask_b & 0x3) << 17) | + ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x3) << 19) | + ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_sspm_emi_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_sspm_pmic_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 26) | + ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 27) | + ((pwrctrl->reg_ssrsys_apsrc_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_ssrsys_ddren_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_ssrsys_emi_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_ssrsys_infra_req_mask_b & 0x1) << 31)); + + /* SPM_SRC_MASK_11 */ + write32(&mtk_spm->spm_src_mask_11, + ((pwrctrl->reg_ssrsys_pmic_req_mask_b & 0x1) << 0) | + ((pwrctrl->reg_ssrsys_srcclkena_mask_b & 0x1) << 1) | + ((pwrctrl->reg_ssrsys_vrf18_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_uart_hub_infra_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_uart_hub_pmic_req_mask_b & 0x1) << 4) | + ((pwrctrl->reg_uart_hub_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_uart_hub_vcore_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_uart_hub_vrf18_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 9) | + ((pwrctrl->reg_ufs_emi_req_mask_b & 0x1) << 10) | + ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_ufs_pmic_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 13) | + ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_vdec_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_vdec_ddren_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_vdec_emi_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_vdec_infra_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_vdec_pmic_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_vdec_srcclkena_mask_b & 0x1) << 20) | + ((pwrctrl->reg_vdec_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_venc_apsrc_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_venc_ddren_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_venc_emi_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_venc_infra_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_venc_pmic_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_venc_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_venc_vrf18_req_mask_b & 0x1) << 28)); + + /* SPM_EVENT_CON_MISC */ + write32(&mtk_spm->spm_event_con_misc, + ((pwrctrl->reg_srcclken_fast_resp & 0x1) << 0) | + ((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 1)); + + /* SPM_WAKEUP_EVENT_MASK */ + write32(&mtk_spm->spm_wakeup_event_mask, + ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + write32(&mtk_spm->spm_wakeup_event_ext_mask, + ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); +} + +static void spm_hw_s1_state_monitor(int en, unsigned int *status) +{ + unsigned int reg; + + if (en) { + clrbits32(&mtk_spm->spm_ack_chk_con_3, SPM_ACK_CHK_3_CON_CLR_ALL); + setbits32(&mtk_spm->spm_ack_chk_con_3, SPM_ACK_CHK_3_CON_EN); + } else { + + reg = read32(&mtk_spm->spm_ack_chk_con_3); + + if (reg & SPM_ACK_CHK_3_CON_RESULT) { + if (status) + *status |= SPM_INTERNAL_STATUS_HW_S1; + } + + setbits32(&mtk_spm->spm_ack_chk_con_3, + SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL); + clrbits32(&mtk_spm->spm_ack_chk_con_3, SPM_ACK_CHK_3_CON_EN); + } +} + +static void spm_init_ulposc_ctrl(void) +{ + write32(&mtk_spm->spm_reosource_ulposc_mask, 0x0); + + clrbits32(&mtk_spm->spm_ulposc_en_cg_con, BIT(16)); + + write32(&mtk_spm->spm_resource_ulposc_ack_con, 0x185); + + setbits32(&mtk_spm->spm_reosource_ulposc_mask, + BIT(2) | BIT(18) | BIT(5) | BIT(21) | BIT(6) | BIT(22) | BIT(1) | BIT(17)); + + setbits32(&mtk_spm->spm_ulposc_en_cg_con, BIT(5) | BIT(0) | BIT(16)); + + setbits32(&mtk_spm->spm_rsv_ulposc_req, (0x1)); + + udelay(100); + + write32(&mtk_spm->spm_ulposc_off_mode_con, 0x1); +} + +void spm_register_init(void) +{ + /* Enable scpsys(SPM) clock off control, 0: Topck AO */ + setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3FF); + setbits32(&mtk_vlpcksys->vlp_clksq_con1, 0x1); + clrbits32(&mtk_vlpcksys->vlp_ap_pll_con3, BIT(1)); + clrbits32(&mtk_vlpcksys->vlp_ap_pll_con3, BIT(6)); + + /* Enable register control */ + write32(&mtk_spm->poweron_config_en, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); + + /* init power control register */ + write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); + + clrbits32(&mtk_spm->spm_sram_con, (0xF << 16)); + + /* SRAM Workaround for Sleep FSM */ + setbits32(&mtk_spm->spm_sram_sleep_ctrl, (0x2 << 8)); + + write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + write32(&mtk_spm->pcm_con1, + SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB | REG_SSPM_APB_P2P_EN_LSB); + + write32(&mtk_spm->spm_clk_con, (0x10 << 24) | (0x7 << 4)); + + /* clean wakeup event raw status */ + write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); + + /* clean ISR status */ + write32(&mtk_spm->spm_irq_mask, ISRM_ALL); + write32(&mtk_spm->spm_irq_sta, ISRC_ALL); + write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); + + setbits32(&mtk_spm->spm_ap_standby_con, BIT(1)); + + write32(&mtk_spm->spm_resource_ack_con_0, 0xCC4E4ECC); + write32(&mtk_spm->spm_resource_ack_con_1, 0x00CCCCCC); + + /* Init Other Reg */ + write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1); + write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT); + spm_hw_s1_state_monitor(0, NULL); + + /* Init SPM DEBUG Output enable */ + write32(&mtk_spm->spm_debug_con, 0x1); + /* Init for SPM Resource ACK */ + write32(&mtk_spm->spm_resource_ack_con_0, 0xCC4E4ECC); + write32(&mtk_spm->spm_resource_ack_con_1, 0x00CCCCCC); + + clrbits32(&mtk_vlpdevapc->vlp_ao_apc_con, BIT(2)); + setbits32(&mtk_vlpdevapc->vlp_ao_mas_sec_0, 0x3); + /* infra sw cg mask for all bit */ + write32p(INFRA_SW_CG, 0xFFFFFFFF); + /* debug_mon for spm pwr_status_msb mtcmos ack check */ + write32p(DEBUG_MON_REG_1, ((0x79U << 16) | (0x78U << 0))); + write32p(DEBUG_MON_REG_2, ((0x7BU << 16) | (0x7AU << 0))); + + spm_init_ulposc_ctrl(); + + spm_set_power_control(&spm_init_ctrl); +} + +void spm_reset_and_init_pcm(void) +{ + /* disable r0 and r7 to control power */ + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* disable pcm timer after leaving FW */ + clrsetbits32(&mtk_spm->pcm_con1, + REG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY); + + /* reset PCM */ + write32(&mtk_spm->pcm_con0, + SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */ + clrsetbits32(&mtk_spm->pcm_con1, ~REG_PCM_WDT_WAKE_LSB, + SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB | + REG_SSPM_APB_P2P_EN_LSB); +} + +void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) +{ + u32 val, mask; + + /* toggle event counter clear */ + write32(&mtk_spm->spm_event_counter_clear, REG_SPM_EVENT_COUNTER_CLR_LSB); + /* toggle for reset SYS TIMER start point */ + setbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB); + + if (pwrctrl->timer_val_cust == 0) + val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_SUSPEND; + else + val = pwrctrl->timer_val_cust; + + write32(&mtk_spm->pcm_timer_val, val); + setbits32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | REG_PCM_TIMER_EN_LSB); + + /* unmask AP wakeup source */ + if (pwrctrl->wake_src_cust == 0) + mask = pwrctrl->wake_src; + else + mask = pwrctrl->wake_src_cust; + + if (pwrctrl->reg_csyspwrup_ack_mask) + mask &= ~R12_CSYSPWREQ_B; + write32(&mtk_spm->spm_wakeup_event_mask, ~mask); + + /* unmask SPM ISR (keep TWAM setting) */ + setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX); + + /* toggle event counter clear */ + write32(&mtk_spm->spm_event_counter_clear, 0); + /* toggle for reset SYS TIMER start point */ + clrbits32(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB); +} + +const struct pwr_ctrl *get_pwr_ctrl(void) +{ + return &spm_init_ctrl; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 1 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure Network
by John Su (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85583?usp=email ) Change subject: mb/trulo/var/uldrenite: Configure Network ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85583/comment/e1d56add_d1bf66ad?us… : PS2, Line 7: Configuration > Configure Done https://review.coreboot.org/c/coreboot/+/85583/comment/b1828228_9c11a4c3?us… : PS2, Line 11: 3. Enable HDA driver > Why not make HDA/audio a separate commit? Done File src/mainboard/google/brya/variants/uldrenite/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85583/comment/d2649401_33e90fda?us… : PS2, Line 435: end #PCIE2 WWAN card > Space after #? Done https://review.coreboot.org/c/coreboot/+/85583/comment/7beee42d_8b432a22?us… : PS2, Line 445: "max98360a" : register "jack_tplg" = "rt5682" > Add this to the commit message? Create new CL for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/85583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fd292550700817f15813dabfbaf9ccab3a907d8 Gerrit-Change-Number: 85583 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 16 Dec 2024 02:27:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure Network
by John Su (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85583?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/trulo/var/uldrenite: Configure Network ...................................................................... mb/trulo/var/uldrenite: Configure Network 1. Enable CNVi WiFI and BT 2. Enable WWAN driver BUG=b:380789023 TEST=emerge-nissa coreboot Change-Id: I2fd292550700817f15813dabfbaf9ccab3a907d8 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 3 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/85583/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fd292550700817f15813dabfbaf9ccab3a907d8 Gerrit-Change-Number: 85583 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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