coreboot-gerrit December 2024

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown
by Subrata Banik (Code Review) 18 Dec '24

18 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85566?usp=email ) Change subject: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown ...................................................................... mb/google/nissa/var/rull: For probe, change unprovisioned to unknown The nissa project fw branch is more suitable for compatibility with unknown, so the compatible methods of wifi and ssd are replaced. BUG=b:383675207 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85566 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb M src/mainboard/google/brya/variants/rull/variant.c 2 files changed, 14 insertions(+), 10 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve Kun Liu: Looks good to me, but someone else must approve build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index 92bc5d4..633d5bc 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -6,6 +6,7 @@ field WIFI 8 9 option WIFI_CNVI_WIFI6E 0 option WIFI_PCIE_WIFI7 1 + option WIFI_UNKNOWN 2 end end @@ -393,8 +394,8 @@ register "add_acpi_dma_property" = "true" device generic 0 on end end - probe WIFI WIFI_CNVI_WIFI6E - probe unprovisioned + probe WIFI WIFI_CNVI_WIFI6E + probe WIFI WIFI_UNKNOWN end device ref pcie_rp4 on # PCIe 4 WLAN @@ -416,7 +417,7 @@ device generic 0 on end end probe WIFI WIFI_PCIE_WIFI7 - probe unprovisioned + probe WIFI WIFI_UNKNOWN end device ref pch_espi on chip ec/google/chromeec @@ -518,7 +519,10 @@ register "desc" = ""PCIe Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" - device ref usb2_port8 on end + device ref usb2_port8 on + probe WIFI WIFI_PCIE_WIFI7 + probe WIFI WIFI_UNKNOWN + end end chip drivers/usb/acpi register "desc" = ""CNVi Bluetooth"" @@ -526,6 +530,7 @@ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" device ref usb2_port10 on probe WIFI WIFI_CNVI_WIFI6E + probe WIFI WIFI_UNKNOWN end end chip drivers/usb/acpi @@ -569,15 +574,14 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" register "srcclk_pin" = "1" - device generic 0 on - probe STORAGE STORAGE_NVME - probe unprovisioned - end + device generic 0 on end end + probe STORAGE STORAGE_NVME + probe STORAGE STORAGE_UNKNOWN end device ref emmc on probe STORAGE STORAGE_EMMC - probe unprovisioned + probe STORAGE STORAGE_UNKNOWN end device ref hda on chip drivers/sof diff --git a/src/mainboard/google/brya/variants/rull/variant.c b/src/mainboard/google/brya/variants/rull/variant.c index e1a95e6..4f8fd47 100644 --- a/src/mainboard/google/brya/variants/rull/variant.c +++ b/src/mainboard/google/brya/variants/rull/variant.c @@ -18,7 +18,7 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { - if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E))) { + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || fw_config_probe(FW_CONFIG(WIFI, WIFI_UNKNOWN))) { printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); config->cnvi_bt_core = true; config->cnvi_bt_audio_offload = true; -- To view, visit https://review.coreboot.org/c/coreboot/+/85566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4 Gerrit-Change-Number: 85566 Gerrit-PatchSet: 4 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure Network
by Dtrain Hsu (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, John Su, Nick Vaccaro, Paul Menzel, Subrata Banik. Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85583?usp=email ) Change subject: mb/trulo/var/uldrenite: Configure Network ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fd292550700817f15813dabfbaf9ccab3a907d8 Gerrit-Change-Number: 85583 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 18 Dec 2024 03:26:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure USB ports and mapping
by Dtrain Hsu (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, John Su, Nick Vaccaro, Paul Menzel. Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85582?usp=email ) Change subject: mb/trulo/var/uldrenite: Configure USB ports and mapping ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8fa3bf958faaf17b35e33fe93e2a11e0d2eb48d6 Gerrit-Change-Number: 85582 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 18 Dec 2024 03:25:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure serial_io and I2C
by Dtrain Hsu (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, John Su, Nick Vaccaro, Paul Menzel, Subrata Banik. Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85581?usp=email ) Change subject: mb/trulo/var/uldrenite: Configure serial_io and I2C ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85581?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c1b6028c7e4392a2142851d5fd0199954e2272d Gerrit-Change-Number: 85581 Gerrit-PatchSet: 11 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 18 Dec 2024 03:19:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox: Include CSE reset in mainboard reset expectation
by Subrata Banik (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Karthik Ramasubramanian, Nick Vaccaro, Ren Kuo. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85642?usp=email ) Change subject: mb/google/brox: Include CSE reset in mainboard reset expectation ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85642?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80a46b15813b6bdfa6c029c54590f4b7c2a6754b Gerrit-Change-Number: 85642 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 03:13:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Enable DPTF, S0ix and configure FIVR setting
by Dtrain Hsu (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, John Su, Nick Vaccaro, Paul Menzel, Subrata Banik. Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85578?usp=email ) Change subject: mb/trulo/var/uldrenite: Enable DPTF, S0ix and configure FIVR setting ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7777b7560b40c1427df9645d991240c027e58e4 Gerrit-Change-Number: 85578 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 18 Dec 2024 03:11:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd: Add some PSP commands
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

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[L] Change in coreboot[main]: temp. for build psp command
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85649?usp=email to review the following change. Change subject: temp. for build psp command ...................................................................... temp. for build psp command Change-Id: Ibb077dcf0581a530751b356af5ba3d3fcd7e8c93 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_efs.c M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/psp_gen2.c M src/soc/amd/common/block/psp/psp_smm.c M src/soc/amd/common/block/psp/spl_fuse.c 8 files changed, 82 insertions(+), 315 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85649/1 diff --git a/src/soc/amd/common/block/psp/psb.c b/src/soc/amd/common/block/psp/psb.c index 5e497a2..be20fc8 100644 --- a/src/soc/amd/common/block/psp/psb.c +++ b/src/soc/amd/common/block/psp/psb.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/reset.h> +#include <amdblocks/smn.h> #include <bootstate.h> #include <console/console.h> #include <device/mmio.h> @@ -34,7 +35,7 @@ #define FUSE_STATUS_FUSING_ERR 0x0a #define FUSE_STATUS_BOOT_DONE 0x0b -static const char *psb_test_status_to_string(uint32_t status) +static const char *psb_test_status_to_string(u32 status) { switch (status) { case PSB_TEST_STATUS_PASS: @@ -66,7 +67,7 @@ } } -static const char *fuse_status_to_string(uint32_t status) +static const char *fuse_status_to_string(u32 status) { switch (status) { case FUSE_STATUS_SUCCESS: @@ -82,16 +83,9 @@ } } -static enum cb_err get_psb_status(uint32_t *psb_status_value) +static uint32_t get_psb_status(void) { - const uintptr_t psp_mmio = get_psp_mmio_base(); - - if (!psp_mmio) { - printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n"); - return CB_ERR; - } - *psb_status_value = read32p(psp_mmio | PSB_STATUS_OFFSET); - return CB_SUCCESS; + return smn_read32(SMN_PSP_PUBLIC_BASE + PSB_STATUS_OFFSET); } /* @@ -101,18 +95,14 @@ */ static enum cb_err psb_enable(void) { - uint32_t status; + u32 status; struct mbox_default_buffer buffer = { .header = { .size = sizeof(buffer) } }; - if (get_psb_status(&status) != CB_SUCCESS) { - printk(BIOS_ERR, "PSP: Failed to get base address.\n"); - return CB_ERR; - } - + status = get_psb_status(); printk(BIOS_INFO, "PSB: Status = %x\n", status); if (status & FUSE_PLATFORM_SECURE_BOOT_EN) { @@ -120,14 +110,10 @@ return CB_SUCCESS; } - if (soc_read_c2p38(&status) != CB_SUCCESS) { - printk(BIOS_ERR, "PSP: Failed to get base address.\n"); - return CB_ERR; - } - + status = soc_read_c2p38(); printk(BIOS_INFO, "PSB: HSTI = %x\n", status); - const uint32_t psb_test_status = status & PSB_TEST_STATUS_MASK; + const u32 psb_test_status = status & PSB_TEST_STATUS_MASK; if (psb_test_status != PSB_TEST_STATUS_PASS) { printk(BIOS_ERR, "PSB: %s\n", psb_test_status_to_string(psb_test_status)); @@ -139,7 +125,7 @@ return CB_ERR; } - printk(BIOS_DEBUG, "PSB: Enable...\n"); + printk(BIOS_DEBUG, "PSB: Enable... "); const int cmd_status = send_psp_command(MBOX_BIOS_CMD_PSB_AUTO_FUSING, &buffer); @@ -150,7 +136,7 @@ return CB_ERR; } - const uint32_t fuse_status = read32(&buffer.header.status); + const u32 fuse_status = read32(&buffer.header.status); if (fuse_status != FUSE_STATUS_SUCCESS) { printk(BIOS_ERR, "PSB: %s\n", fuse_status_to_string(fuse_status)); return CB_ERR; diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 9ad04e1..f989a3b 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -35,7 +35,7 @@ } } -static uint32_t rd_resp_sts(struct mbox_buffer_header *header) +static u32 rd_resp_sts(struct mbox_buffer_header *header) { return read32(&header->status); } @@ -55,52 +55,6 @@ printk(BIOS_DEBUG, "OK\n"); } -enum cb_err psp_get_ftpm_capabilties(uint32_t *capabilities) -{ - int cmd_status; - struct mbox_cmd_capability_query_buffer buffer = { - .header = { - .size = sizeof(buffer) - }, - }; - - printk(BIOS_DEBUG, "PSP: Querying fTPM capabilities..."); - - cmd_status = send_psp_command(MBOX_BIOS_CMD_PSP_FTPM_QUERY, &buffer); - - /* buffer's status shouldn't change but report it if it does */ - psp_print_cmd_status(cmd_status, &buffer.header); - - if (cmd_status) - return CB_ERR; - - *capabilities = read32(&buffer.capabilities); - return CB_SUCCESS; -} - -enum cb_err psp_get_hsti_state(uint32_t *state) -{ - int cmd_status; - struct mbox_cmd_hsti_query_buffer buffer = { - .header = { - .size = sizeof(buffer) - }, - }; - - printk(BIOS_DEBUG, "PSP: Querying HSTI state..."); - - cmd_status = send_psp_command(MBOX_BIOS_CMD_HSTI_QUERY, &buffer); - - /* buffer's status shouldn't change but report it if it does */ - psp_print_cmd_status(cmd_status, &buffer.header); - - if (cmd_status) - return CB_ERR; - - *state = read32(&buffer.state); - return CB_SUCCESS; -} - /* * Notify the PSP that the system is completing the boot process. Upon * receiving this command, the PSP will only honor commands where the buffer diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 369ef08..9def98b 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -18,16 +18,13 @@ #define MBOX_BIOS_CMD_SX_INFO 0x03 #define MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX 0x07 #define MBOX_BIOS_CMD_RSM_INFO 0x04 -#define MBOX_BIOS_CMD_PSP_FTPM_QUERY 0x05 +#define MBOX_BIOS_CMD_PSP_QUERY 0x05 #define MBOX_BIOS_CMD_BOOT_DONE 0x06 #define MBOX_BIOS_CMD_CLEAR_S3_STS 0x07 #define MBOX_BIOS_CMD_S3_DATA_INFO 0x08 #define MBOX_BIOS_CMD_NOP 0x09 -#define MBOX_BIOS_CMD_HSTI_QUERY 0x14 #define MBOX_BIOS_CMD_PSB_AUTO_FUSING 0x21 -#define MBOX_BIOS_CMD_PSP_CAPS_QUERY 0x27 #define MBOX_BIOS_CMD_SET_SPL_FUSE 0x2d -#define MBOX_BIOS_CMD_SET_RPMC_ADDRESS 0x39 #define MBOX_BIOS_CMD_QUERY_SPL_FUSE 0x47 #define MBOX_BIOS_CMD_I2C_TPM_ARBITRATION 0x64 #define MBOX_BIOS_CMD_ABORT 0xfe @@ -46,16 +43,17 @@ * AMD reference code aligns and pads all buffers to 32 bytes. */ struct mbox_buffer_header { - uint32_t size; /* total size of buffer */ - uint32_t status; /* command status, filled by PSP if applicable */ + u32 size; /* total size of buffer */ + u32 status; /* command status, filled by PSP if applicable */ } __packed; /* - * x86 to PSP mailbox commands that don't take any parameter or return any data, use the - * mbox_default_buffer, while x86 to PSP commands that either pass data to the PSP or get data - * returned from the PSP use command-specific buffer definitions. For details on the specific - * buffer definitions for the various commands, see NDA document #54267 for the generations - * before family 17h and NDA document #55758 for the generations from family 17h on. + * command-specific buffer definitions: see NDA document #54267 + * The following commands need a buffer definition if they are to be used. + * All other commands will work with the default buffer. + * MBOX_BIOS_CMD_SMM_INFO MBOX_BIOS_CMD_PSP_QUERY + * MBOX_BIOS_CMD_SX_INFO MBOX_BIOS_CMD_S3_DATA_INFO + * MBOX_BIOS_CMD_RSM_INFO */ struct mbox_default_buffer { /* command-response buffer unused by command */ @@ -75,37 +73,16 @@ uint64_t psp_mbox_smm_flag_address; } __packed; -/* MBOX_BIOS_CMD_SMM_INFO */ struct mbox_cmd_smm_info_buffer { struct mbox_buffer_header header; struct smm_req_buffer req; } __packed __aligned(32); -/* MBOX_BIOS_CMD_SX_INFO */ struct mbox_cmd_sx_info_buffer { struct mbox_buffer_header header; - uint8_t sleep_type; + u8 sleep_type; } __packed __aligned(32); -/* MBOX_BIOS_CMD_PSP_FTPM_QUERY, MBOX_BIOS_CMD_PSP_CAPS_QUERY */ -struct mbox_cmd_capability_query_buffer { - struct mbox_buffer_header header; - uint32_t capabilities; -} __packed __aligned(32); - -/* MBOX_BIOS_CMD_HSTI_QUERY */ -struct mbox_cmd_hsti_query_buffer { - struct mbox_buffer_header header; - uint32_t state; -} __packed __aligned(32); - -/* MBOX_BIOS_CMD_SET_RPMC_ADDRESS */ -struct mbox_cmd_set_rpmc_address_buffer { - struct mbox_buffer_header header; - uint32_t address; -} __packed __aligned(32); - -/* MBOX_BIOS_CMD_SET_SPL_FUSE */ struct mbox_cmd_late_spl_buffer { struct mbox_buffer_header header; uint32_t spl_value; @@ -122,7 +99,6 @@ DTPM_REQUEST_MAX, }; -/* MBOX_BIOS_CMD_I2C_TPM_ARBITRATION */ struct mbox_cmd_dtpm_config_buffer { struct mbox_buffer_header header; uint32_t request_type; @@ -132,32 +108,11 @@ #define PSP_INIT_TIMEOUT 10000 /* 10 seconds */ #define PSP_CMD_TIMEOUT 1000 /* 1 second */ -#define C2P_BUFFER_MAXSIZE 0xc00 /* Core-to-PSP buffer */ -#define P2C_BUFFER_MAXSIZE 0x1000 /* PSP-to-core buffer */ - -/* PSP to x86 status */ -enum mbox_p2c_status { - MBOX_PSP_SUCCESS = 0x00, - MBOX_PSP_INVALID_PARAMETER = 0x01, - MBOX_PSP_CRC_ERROR = 0x02, - MBOX_PSP_COMMAND_PROCESS_ERROR = 0x04, - MBOX_PSP_UNSUPPORTED = 0x08, - MBOX_PSP_SPI_BUSY_ASYNC = 0x0a, - MBOX_PSP_SPI_BUSY = 0x0b, -}; - -uintptr_t get_psp_mmio_base(void); - void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header); /* This command needs to be implemented by the generation specific code. */ -int send_psp_command(uint32_t command, void *buffer); +int send_psp_command(u32 command, void *buffer); -enum cb_err psp_get_ftpm_capabilties(uint32_t *capabilities); -enum cb_err psp_get_psp_capabilities(uint32_t *capabilities); -enum cb_err psp_get_hsti_state(uint32_t *state); -enum cb_err soc_read_c2p38(uint32_t *msg_38_value); - -void enable_psp_smi(void); +uint32_t soc_read_c2p38(void); #endif /* __AMD_PSP_DEF_H__ */ diff --git a/src/soc/amd/common/block/psp/psp_efs.c b/src/soc/amd/common/block/psp/psp_efs.c index fa69aea..7227b92 100644 --- a/src/soc/amd/common/block/psp/psp_efs.c +++ b/src/soc/amd/common/block/psp/psp_efs.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/psp_efs.h> +#include <assert.h> #include <boot_device.h> #include <commonlib/region.h> #include <device/mmio.h> diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index b3815f9..1227c2a 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -32,9 +32,9 @@ * cmd_response: pointer to command/response buffer */ struct pspv1_mbox { - uint32_t mbox_command; - uint32_t mbox_status; - uint64_t cmd_response; /* definition conflicts w/BKDG but matches agesa */ + u32 mbox_command; + u32 mbox_status; + u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */ } __packed; static void *soc_get_mbox_address(void) @@ -64,17 +64,17 @@ return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); } -static uint32_t rd_mbox_sts(struct pspv1_mbox *mbox) +static u32 rd_mbox_sts(struct pspv1_mbox *mbox) { return read32(&mbox->mbox_status); } -static void wr_mbox_cmd(struct pspv1_mbox *mbox, uint32_t cmd) +static void wr_mbox_cmd(struct pspv1_mbox *mbox, u32 cmd) { write32(&mbox->mbox_command, cmd); } -static uint32_t rd_mbox_cmd(struct pspv1_mbox *mbox) +static u32 rd_mbox_cmd(struct pspv1_mbox *mbox) { return read32(&mbox->mbox_command); } @@ -112,7 +112,7 @@ return -PSPSTS_CMD_TIMEOUT; } -int send_psp_command(uint32_t command, void *buffer) +int send_psp_command(u32 command, void *buffer) { struct pspv1_mbox *mbox = soc_get_mbox_address(); if (!mbox) @@ -153,7 +153,7 @@ int psp_load_named_blob(enum psp_blob_type type, const char *name) { int cmd_status; - uint32_t command; + u32 command; void *blob; switch (type) { diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index 21c1f2a..0fffb17 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -3,131 +3,63 @@ #include <timer.h> #include <types.h> #include <amdblocks/psp.h> -#include <amdblocks/root_complex.h> #include <amdblocks/smn.h> -#include <device/mmio.h> #include "psp_def.h" #define PSP_MAILBOX_COMMAND_OFFSET 0x10570 /* 4 bytes */ -#define PSP_MAILBOX_BUFFER_OFFSET 0x10574 /* 8 bytes */ - -#define IOHC_MISC_PSP_MMIO_REG 0x2e0 - -static uint64_t get_psp_mmio_mask(void) -{ - const struct non_pci_mmio_reg *mmio_regs; - size_t reg_count; - mmio_regs = get_iohc_non_pci_mmio_regs(&reg_count); - - for (size_t i = 0; i < reg_count; i++) { - if (mmio_regs[i].iohc_misc_offset == IOHC_MISC_PSP_MMIO_REG) - return mmio_regs[i].mask; - } - - printk(BIOS_ERR, "No PSP MMIO register description found.\n"); - return 0; -} - -#define PSP_MMIO_LOCK BIT(8) - -/* Getting the PSP MMIO base from the domain resources only works in ramstage, but not in SMM, - so we have to read this from the hardware registers */ -uintptr_t get_psp_mmio_base(void) -{ - static uintptr_t psp_mmio_base; - const struct domain_iohc_info *iohc; - size_t iohc_count; - - if (psp_mmio_base) - return psp_mmio_base; - - iohc = get_iohc_info(&iohc_count); - const uint64_t psp_mmio_mask = get_psp_mmio_mask(); - - if (!psp_mmio_mask) - return 0; - - for (size_t i = 0; i < iohc_count; i++) { - uint64_t reg64 = smn_read64(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG); - - if (!(reg64 & IOHC_MMIO_EN)) - continue; - - const uint64_t base = reg64 & psp_mmio_mask; - - if (ENV_X86_32 && base >= 4ull * GiB) { - printk(BIOS_WARNING, "PSP MMIO base above 4GB.\n"); - continue; - } - - /* If the PSP MMIO base is enabled but the register isn't locked, set the lock - bit. This shouldn't happen, but better be a bit too careful here */ - if (!(reg64 & PSP_MMIO_LOCK)) { - printk(BIOS_WARNING, "Enabled PSP MMIO in domain %zu isn't locked. " - "Locking it.\n", i); - reg64 |= PSP_MMIO_LOCK; - /* Since the lock bit lives in the lower one of the two 32 bit SMN - registers, we only need to write that one to lock it */ - smn_write32(iohc[i].misc_smn_base | IOHC_MISC_PSP_MMIO_REG, - reg64 & 0xffffffff); - } - - psp_mmio_base = base; - } - - if (!psp_mmio_base) - printk(BIOS_ERR, "No usable PSP MMIO found.\n"); - - return psp_mmio_base; -} +#define PSP_MAILBOX_BUFFER_L_OFFSET 0x10574 /* 4 bytes */ +#define PSP_MAILBOX_BUFFER_H_OFFSET 0x10578 /* 4 bytes */ union pspv2_mbox_command { - uint32_t val; + u32 val; struct pspv2_mbox_cmd_fields { - uint16_t mbox_status; - uint8_t mbox_command; - uint32_t reserved:6; - uint32_t recovery:1; - uint32_t ready:1; + u16 mbox_status; + u8 mbox_command; + u32 reserved:6; + u32 recovery:1; + u32 ready:1; } __packed fields; }; -static uint16_t rd_mbox_sts(uintptr_t psp_mmio) +static u16 rd_mbox_sts(void) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET); return tmp.fields.mbox_status; } -static void wr_mbox_cmd(uintptr_t psp_mmio, uint8_t cmd) +static void wr_mbox_cmd(u8 cmd) { union pspv2_mbox_command tmp = { .val = 0 }; /* Write entire 32-bit area to begin command execution */ tmp.fields.mbox_command = cmd; - write32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET, tmp.val); + smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET, tmp.val); } -static uint8_t rd_mbox_recovery(uintptr_t psp_mmio) +static u8 rd_mbox_recovery(void) { union pspv2_mbox_command tmp; - tmp.val = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET); return !!tmp.fields.recovery; } -static void wr_mbox_buffer_ptr(uintptr_t psp_mmio, void *buffer) +static void wr_mbox_buffer_ptr(void *buffer) { - write64p(psp_mmio | PSP_MAILBOX_BUFFER_OFFSET, (uintptr_t)buffer); + const uint32_t buf_addr_h = (uint64_t)(uintptr_t)buffer >> 32; + const uint32_t buf_addr_l = (uint64_t)(uintptr_t)buffer & 0xffffffff; + smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_H_OFFSET, buf_addr_h); + smn_write32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_BUFFER_L_OFFSET, buf_addr_l); } -static int wait_command(uintptr_t psp_mmio, bool wait_for_ready) +static int wait_command(bool wait_for_ready) { union pspv2_mbox_command and_mask = { .val = ~0 }; union pspv2_mbox_command expected = { .val = 0 }; struct stopwatch sw; - uint32_t tmp; + u32 tmp; /* Zero fields from and_mask that should be kept */ and_mask.fields.mbox_command = 0; @@ -140,7 +72,7 @@ stopwatch_init_msecs_expire(&sw, PSP_CMD_TIMEOUT); do { - tmp = read32p(psp_mmio | PSP_MAILBOX_COMMAND_OFFSET); + tmp = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET); tmp &= ~and_mask.val; if (tmp == expected.val) return 0; @@ -149,65 +81,39 @@ return -PSPSTS_CMD_TIMEOUT; } -int send_psp_command(uint32_t command, void *buffer) +int send_psp_command(u32 command, void *buffer) { - const uintptr_t psp_mmio = get_psp_mmio_base(); - if (!psp_mmio) - return -PSPSTS_NOBASE; - - if (rd_mbox_recovery(psp_mmio)) + if (rd_mbox_recovery()) return -PSPSTS_RECOVERY; - if (wait_command(psp_mmio, true)) + if (wait_command(true)) return -PSPSTS_CMD_TIMEOUT; /* set address of command-response buffer and write command register */ - wr_mbox_buffer_ptr(psp_mmio, buffer); - wr_mbox_cmd(psp_mmio, command); + wr_mbox_buffer_ptr(buffer); + wr_mbox_cmd(command); /* PSP clears command register when complete. All commands except * SxInfo set the Ready bit. */ - if (wait_command(psp_mmio, command != MBOX_BIOS_CMD_SX_INFO)) + if (wait_command(command != MBOX_BIOS_CMD_SX_INFO)) return -PSPSTS_CMD_TIMEOUT; /* check delivery status */ - if (rd_mbox_sts(psp_mmio)) + if (rd_mbox_sts()) return -PSPSTS_SEND_ERROR; return 0; } -enum cb_err psp_get_psp_capabilities(uint32_t *capabilities) +uint32_t soc_read_c2p38(void) { - int cmd_status; - struct mbox_cmd_capability_query_buffer buffer = { - .header = { - .size = sizeof(buffer) - }, - }; - - printk(BIOS_DEBUG, "PSP: Querying PSP capabilities..."); - - cmd_status = send_psp_command(MBOX_BIOS_CMD_PSP_CAPS_QUERY, &buffer); - - /* buffer's status shouldn't change but report it if it does */ - psp_print_cmd_status(cmd_status, &buffer.header); - - if (cmd_status) - return CB_ERR; - - *capabilities = read32(&buffer.capabilities); - return CB_SUCCESS; + return smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET); } -enum cb_err soc_read_c2p38(uint32_t *msg_38_value) +uint8_t check_abrecovery(void) { - const uintptr_t psp_mmio = get_psp_mmio_base(); + union pspv2_mbox_command tmp; - if (!psp_mmio) { - printk(BIOS_WARNING, "PSP: PSP_ADDR_MSR uninitialized\n"); - return CB_ERR; - } - *msg_38_value = read32p(psp_mmio | CORE_2_PSP_MSG_38_OFFSET); - return CB_SUCCESS; + tmp.val = smn_read32(SMN_PSP_PUBLIC_BASE + PSP_MAILBOX_COMMAND_OFFSET); + return !!tmp.fields.recovery; } diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 671942b..2112e86 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -6,34 +6,23 @@ #include <region_file.h> #include <console/console.h> #include <amdblocks/psp.h> -#include <amdblocks/smi.h> #include <soc/iomap.h> #include <string.h> #include "psp_def.h" -/* - * When sending PSP mailbox commands to the PSP from the SMI handler after the boot done - * command was sent, the corresponding data buffer needs to be placed in this core to PSP (C2P) - * buffer. - */ +#define C2P_BUFFER_MAXSIZE 0xc00 /* Core-to-PSP buffer */ +#define P2C_BUFFER_MAXSIZE 0xc00 /* PSP-to-core buffer */ + struct { - uint8_t buffer[C2P_BUFFER_MAXSIZE]; + u8 buffer[C2P_BUFFER_MAXSIZE]; } __aligned(32) c2p_buffer; -/* - * When the PSP sends mailbox commands to the host, it will update the PSP to core (P2C) buffer - * and then send an SMI to the host to process the request. - */ struct { - uint8_t buffer[P2C_BUFFER_MAXSIZE]; + u8 buffer[P2C_BUFFER_MAXSIZE]; } __aligned(32) p2c_buffer; -/* - * When sending PSP mailbox commands to the PSP from the SMI handler, the SMM flag needs to be - * set for the PSP to accept it. Otherwise it should be cleared. - */ -static uint32_t smm_flag; +static uint32_t smm_flag; /* Non-zero for SMM, clear when not */ static void set_smm_flag(void) { @@ -45,24 +34,6 @@ smm_flag = 0; } -static int send_psp_command_smm(uint32_t command, void *buffer) -{ - int cmd_status; - - set_smm_flag(); - cmd_status = send_psp_command(command, buffer); - clear_smm_flag(); - - return cmd_status; -} - -/* - * The MBOX_BIOS_CMD_SMM_INFO PSP mailbox command doesn't necessarily need be sent from SMM, - * but doing so allows the linker to sort out the addresses of c2p_buffer, p2c_buffer and - * smm_flag without us needing to pass this info between ramstage and smm. In the PSP gen2 case - * this will also make sure that the PSP MMIO base will be cached in SMM before the OS takes - * over so no SMN accesses will be needed during OS runtime. - */ int psp_notify_smm(void) { msr_t msr; @@ -90,14 +61,11 @@ soc_fill_smm_reg_info(&buffer.req.smm_reg_info); #endif - if (CONFIG(SOC_AMD_COMMON_BLOCK_PSP_SMI)) { - configure_psp_smi(); - enable_psp_smi(); - } - printk(BIOS_DEBUG, "PSP: Notify SMM info... "); - cmd_status = send_psp_command_smm(MBOX_BIOS_CMD_SMM_INFO, &buffer); + set_smm_flag(); + cmd_status = send_psp_command(MBOX_BIOS_CMD_SMM_INFO, &buffer); + clear_smm_flag(); /* buffer's status shouldn't change but report it if it does */ psp_print_cmd_status(cmd_status, &buffer.header); @@ -106,7 +74,7 @@ } /* Notify PSP the system is going to a sleep state. */ -void psp_notify_sx_info(uint8_t sleep_type) +void psp_notify_sx_info(u8 sleep_type) { int cmd_status; struct mbox_cmd_sx_info_buffer *buffer; @@ -125,7 +93,9 @@ buffer->sleep_type = sleep_type; - cmd_status = send_psp_command_smm(MBOX_BIOS_CMD_SX_INFO, buffer); + set_smm_flag(); + cmd_status = send_psp_command(MBOX_BIOS_CMD_SX_INFO, buffer); + clear_smm_flag(); /* buffer's status shouldn't change but report it if it does */ psp_print_cmd_status(cmd_status, &buffer->header); diff --git a/src/soc/amd/common/block/psp/spl_fuse.c b/src/soc/amd/common/block/psp/spl_fuse.c index b6e715a..cb1fab0 100644 --- a/src/soc/amd/common/block/psp/spl_fuse.c +++ b/src/soc/amd/common/block/psp/spl_fuse.c @@ -8,17 +8,12 @@ static void psp_set_spl_fuse(void *unused) { int cmd_status = 0; - uint32_t c2p38 = 0; struct mbox_cmd_late_spl_buffer buffer = { .header = { .size = sizeof(buffer) } }; - - if (soc_read_c2p38(&c2p38) != CB_SUCCESS) { - printk(BIOS_ERR, "PSP: Failed to get base address.\n"); - return; - } + uint32_t c2p38 = soc_read_c2p38(); if (c2p38 & CORE_2_PSP_MSG_38_FUSE_SPL) { printk(BIOS_DEBUG, "PSP: SPL Fusing may be updated.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/85649?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb077dcf0581a530751b356af5ba3d3fcd7e8c93 Gerrit-Change-Number: 85649 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: AMD A/B recovery: Add flashmap data for B partition
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85648?usp=email to review the following change. Change subject: AMD A/B recovery: Add flashmap data for B partition ...................................................................... AMD A/B recovery: Add flashmap data for B partition Change-Id: I5eb4cc8a5a64f47a9a7fe2085e3b601fe7162ffb Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/birman/board_glinda.fmd M src/mainboard/amd/birman/board_phoenix.fmd M src/mainboard/amd/majolica/Kconfig A src/mainboard/amd/majolica/board_ab.fmd 4 files changed, 32 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85648/1 diff --git a/src/mainboard/amd/birman/board_glinda.fmd b/src/mainboard/amd/birman/board_glinda.fmd index 7567090..c1367be 100644 --- a/src/mainboard/amd/birman/board_glinda.fmd +++ b/src/mainboard/amd/birman/board_glinda.fmd @@ -1,8 +1,14 @@ -FLASH@0xFF000000 16M { +FLASH 16M { BIOS { EC_SIG 4K FMAP 4K - COREBOOT(CBFS) + EFS @128K + PARTITIION @8M { + COREBOOT(CBFS) + } + BCOPY @12M { + COREBOOTB(CBFS) + } EC_BODY@15872K 256K RW_MRC_CACHE 120K } diff --git a/src/mainboard/amd/birman/board_phoenix.fmd b/src/mainboard/amd/birman/board_phoenix.fmd index bc09fe7..9cccec2 100644 --- a/src/mainboard/amd/birman/board_phoenix.fmd +++ b/src/mainboard/amd/birman/board_phoenix.fmd @@ -1,8 +1,15 @@ -FLASH@0xFF000000 16M { +FLASH 16M { BIOS { EC_SIG 4K FMAP 4K - COREBOOT(CBFS) + EFS @128K + PARTITIION @2M { + COREBOOT(CBFS) + } + BCOPY @8M { + COREBOOTB(CBFS) + } +# COREBOOT(CBFS) EC_BODY@15872K 256K RW_MRC_CACHE 256K } diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig index a167dff..569fe52 100644 --- a/src/mainboard/amd/majolica/Kconfig +++ b/src/mainboard/amd/majolica/Kconfig @@ -15,6 +15,7 @@ config FMDFILE default "src/mainboard/amd/majolica/chromeos.fmd" if CHROMEOS + default "src/mainboard/amd/majolica/board_ab.fmd" if PSP_AB_RECOVERY default "src/mainboard/amd/majolica/board.fmd" config MAINBOARD_DIR diff --git a/src/mainboard/amd/majolica/board_ab.fmd b/src/mainboard/amd/majolica/board_ab.fmd new file mode 100644 index 0000000..2b5dac9 --- /dev/null +++ b/src/mainboard/amd/majolica/board_ab.fmd @@ -0,0 +1,14 @@ +FLASH@0xFF000000 16M { + BIOS { + EC 128K + RW_MRC_CACHE 64K + FMAP 4K + EFS @8519680 1M + PARTITIION @10M { + COREBOOT(CBFS) + } + BCOPY @13M { + COREBOOTB(CBFS) + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85648?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5eb4cc8a5a64f47a9a7fe2085e3b601fe7162ffb Gerrit-Change-Number: 85648 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd: Add A/B recovery support to AMD SOC
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

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