coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[XS] Change in coreboot[main]: src/soc/intel/cmn/blk/cse: Log cse sync information
by Dinesh Gehlot (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Kapil Porwal, Paul Menzel, Subrata Banik. Dinesh Gehlot has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/85219?usp=email ) Change subject: src/soc/intel/cmn/blk/cse: Log cse sync information ...................................................................... Patch Set 3: (2 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/85219/comment/dfb038c1_96e3ac50?us… : PS2, Line 809: elog_add_event_byte(ELOG_TYPE_FW_CSE_SYNC, CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)? > > `spaces required around that '?' (ctx:VxE)` […] Acknowledged https://review.coreboot.org/c/coreboot/+/85219/comment/ae23b270_02f42391?us… : PS2, Line 810: ELOG_FW_LATE_CSE_SYNC:ELOG_FW_EARLY_CSE_SYNC); > > `labels should not be indented` […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idece841c2b069d7688afc258470667ed2851a282 Gerrit-Change-Number: 85219 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 05:52:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

1 0

[S] Change in coreboot[main]: soc/intel: Log CSE Sync Early Sign of Life event from a better place
by Dinesh Gehlot (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik, Tarun. Dinesh Gehlot has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85111?usp=email ) Change subject: soc/intel: Log CSE Sync Early Sign of Life event from a better place ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/meteorlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85111/comment/cb02105e_676a7526?us… : PS4, Line 459: if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) { > Should we check here too whether CSE is in RO and not in RW, to avoid redundant ESOL_CSE_SYNC event […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7 Gerrit-Change-Number: 85111 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 05:52:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

1 0

[S] Change in coreboot[main]: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
by John Su (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85537?usp=email ) Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Re-upload to fix conflict. -- To view, visit https://review.coreboot.org/c/coreboot/+/85537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Gerrit-Change-Number: 85537 Gerrit-PatchSet: 8 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 18 Dec 2024 05:42:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
by John Su (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Hello Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85537?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+2 by Dtrain Hsu, Code-Review+2 by Eric Lai, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence ...................................................................... mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence Uldrenite supports the WWAN 5G device and uses variant.c to handle the power-on sequence according to the Rolling Wireless_RW350R-GL_Hardware Guide_Generic_V1.1. Due to no hardware access, the boot time is estimated to increase by 50 ms. At this stage, we do not yet have the board or key parts for verification. However, I still need to merge the CL to ensure that the WWAN functionality works. Once the motherboard is available, I will make adjustments to optimize and reduce the boot time. BUG=b:381393809, b:383212261 BRANCH=None TEST=emerge-nissa coreboot Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/Makefile.mk A src/mainboard/google/brya/variants/uldrenite/variant.c 2 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85537/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Gerrit-Change-Number: 85537 Gerrit-PatchSet: 8 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

[L] Change in coreboot[main]: temp. for build psp command
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85649?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: temp. for build psp command ...................................................................... temp. for build psp command Change-Id: Ibb077dcf0581a530751b356af5ba3d3fcd7e8c93 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_efs.c M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/psp_gen2.c M src/soc/amd/common/block/psp/psp_smm.c M src/soc/amd/common/block/psp/spl_fuse.c 8 files changed, 78 insertions(+), 319 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85649/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85649?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb077dcf0581a530751b356af5ba3d3fcd7e8c93 Gerrit-Change-Number: 85649 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[XS] Change in coreboot[main]: mb/google/rauru: Add pwrsel init in romstage
by Yidi Lin (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85620?usp=email ) Change subject: mb/google/rauru: Add pwrsel init in romstage ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I37c0fb905f99491ca99f04bc5bfa6abfb1c01059 Gerrit-Change-Number: 85620 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 04:48:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: soc/mediatek/mt8196: Add pwrsel driver
by Yidi Lin (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85613?usp=email ) Change subject: soc/mediatek/mt8196: Add pwrsel driver ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18 Gerrit-Change-Number: 85613 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 04:48:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: mb/google/brya/var/uldrenite: Enable PMC, HECI and SRAM devices
by Subrata Banik (Code Review) 18 Dec '24

18 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85597?usp=email ) Change subject: mb/google/brya/var/uldrenite: Enable PMC, HECI and SRAM devices ...................................................................... mb/google/brya/var/uldrenite: Enable PMC, HECI and SRAM devices Referencing the baseboard PnP settings for Uldrenite. BUG=b:380789023 TEST=emerge-nissa coreboot Change-Id: Icd537fd5b6bfa589931633b72477414098523b54 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85597 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index 38aedaa..7c8dddf 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -120,6 +120,10 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # FIXME: To be enabled in future based on PNP impact data. + # Disable Package C-state demotion for nissa baseboard. + register "disable_package_c_state_demotion" = "true" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -448,6 +452,9 @@ device generic 0 alias rp2_wwan on end end end # PCIE2 WWAN card + device ref shared_sram on end + device ref heci1 on end + device ref pmc hidden end device ref emmc on end device ref uart0 on end device ref pch_espi on -- To view, visit https://review.coreboot.org/c/coreboot/+/85597?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd537fd5b6bfa589931633b72477414098523b54 Gerrit-Change-Number: 85597 Gerrit-PatchSet: 7 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com>

1 0

[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682)
by Subrata Banik (Code Review) 18 Dec '24

18 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85600?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682) ...................................................................... mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682) 1. Enable HDA driver 2. Add spkr_tplg = max98360a 3. Add jack_tplg = rt5682 BUG=b:380789023 TEST=emerge-nissa coreboot Change-Id: I8f78a8641de23eadb03348a31574045702b40554 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85600 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/Makefile.mk M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 3 files changed, 18 insertions(+), 0 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index bc53fdf..aa7e643 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -616,6 +616,7 @@ select HAVE_PCIE_WWAN select HAVE_WWAN_POWER_SEQUENCE select DRIVERS_WWAN_FM350GL + select SOC_INTEL_COMMON_BLOCK_HDA_VERB config BOARD_GOOGLE_VELL select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk index 4c33dad..87f515a 100644 --- a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk +++ b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk @@ -4,3 +4,5 @@ romstage-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index 4e6a8b0..38aedaa 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -78,6 +78,13 @@ # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. register "tcss_aux_ori" = "0" + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + # Configure external V1P05/Vnn/VnnSx Rails register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, @@ -448,5 +455,13 @@ device pnp 0c09.0 on end end end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85600?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f78a8641de23eadb03348a31574045702b40554 Gerrit-Change-Number: 85600 Gerrit-PatchSet: 7 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure Network
by Subrata Banik (Code Review) 18 Dec '24

18 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85583?usp=email ) Change subject: mb/trulo/var/uldrenite: Configure Network ...................................................................... mb/trulo/var/uldrenite: Configure Network 1. Enable CNVi WiFI and BT 2. Enable WWAN driver BUG=b:380789023 TEST=emerge-nissa coreboot Change-Id: I2fd292550700817f15813dabfbaf9ccab3a907d8 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85583 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 3 files changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index d894f7f..bc53fdf 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -613,6 +613,9 @@ config BOARD_GOOGLE_ULDRENITE select BOARD_GOOGLE_BASEBOARD_TRULO select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION + select HAVE_PCIE_WWAN + select HAVE_WWAN_POWER_SEQUENCE + select DRIVERS_WWAN_FM350GL config BOARD_GOOGLE_VELL select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h index c4fe342..25edb0c 100644 --- a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h @@ -5,4 +5,10 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_H23 +#define WWAN_RST GPP_F12 +#define WWAN_PERST GPP_H13 +#define T1_OFF_MS 20 +#define T2_OFF_MS 10 + #endif diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index d225e19..4e6a8b0 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -9,6 +9,9 @@ register "tcc_offset" = "5" # TCC of 100 + # Enable CNVi BT + register "cnvi_bt_core" = "true" + # eMMC HS400 register "emmc_enable_hs400_mode" = "true" @@ -285,6 +288,14 @@ end end end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end device ref i2c0 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" @@ -405,6 +416,31 @@ device i2c 40 on end end # GTCH7502 end # I2C5 + device ref pcie_rp2 on + # Enable WWAN Card PCIE 2 using clk 2 + register "pch_pcie_rp[PCH_RP(2)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F13)" + register "reset_off_delay_ms" = "20" + register "srcclk_pin" = "2" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + device generic 0 alias rp2_rtd3 on end + end + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H23)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F12)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F13)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "add_acpi_dma_property" = "true" + use rp2_rtd3 as rtd3dev + device generic 0 alias rp2_wwan on end + end + end # PCIE2 WWAN card device ref emmc on end device ref uart0 on end device ref pch_espi on -- To view, visit https://review.coreboot.org/c/coreboot/+/85583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fd292550700817f15813dabfbaf9ccab3a907d8 Gerrit-Change-Number: 85583 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2024