coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: soc/amd/cezanne: Rename the setting name to AB recovery
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85646?usp=email to review the following change. Change subject: soc/amd/cezanne: Rename the setting name to AB recovery ...................................................................... soc/amd/cezanne: Rename the setting name to AB recovery Change-Id: Iaf092c4f7005f30ac12f5fffffa60c7c9f8f2ccb Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/85646/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 7b97ce7..c6846a1 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -408,7 +408,7 @@ help Add psp_verstage signature token to the build & PSP Directory Table -config PSP_RECOVERY_AB +config PSP_AB_RECOVERY bool "Use A/B Recovery scheme" default n help -- To view, visit https://review.coreboot.org/c/coreboot/+/85646?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf092c4f7005f30ac12f5fffffa60c7c9f8f2ccb Gerrit-Change-Number: 85646 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: abrecovery: Add setting boot status and corrupt type
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Julius Werner, Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85645?usp=email to review the following change. Change subject: abrecovery: Add setting boot status and corrupt type ...................................................................... abrecovery: Add setting boot status and corrupt type Change-Id: I55a379b9c9f85fabbd8a1f98fbef3f57d7d8118d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/lib/cbfs.c M src/lib/prog_loaders.c 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/85645/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 84ba894..703d709 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -182,8 +182,10 @@ && vboot_logic_executed()) vboot_fail_and_reboot(vboot_get_context(), VB2_RECOVERY_FW_BODY, rv); - if (CONFIG(PSP_AB_RECOVERY)) + if (CONFIG(PSP_AB_RECOVERY)) { + set_corrupt_entry(0x62); toggle_bootpartition(); + } return true; } } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 49056cc..f101ed7 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -14,6 +14,7 @@ #include <stage_cache.h> #include <symbols.h> #include <timestamp.h> +#include <soc/amd/common/block/psp/psp_def.h> void run_romstage(void) { @@ -191,6 +192,7 @@ /* Reset to booting from this image as late as possible */ boot_successful(); + set_boot_status(1); printk(BIOS_DEBUG, "Jumping to boot code at %p(%p)\n", prog_entry(payload), prog_entry_arg(payload)); -- To view, visit https://review.coreboot.org/c/coreboot/+/85645?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I55a379b9c9f85fabbd8a1f98fbef3f57d7d8118d Gerrit-Change-Number: 85645 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao

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[S] Change in coreboot[main]: cbfs: Add COREBOOTB as backup region for A/B recovery
by Bao Zheng (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Bao Zheng, Julius Werner, Zheng Bao. Hello Julius Werner, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85629?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: cbfs: Add COREBOOTB as backup region for A/B recovery ...................................................................... cbfs: Add COREBOOTB as backup region for A/B recovery Change-Id: I019af6fbeca46e0e35d739a028655051fb466b48 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/lib/cbfs.c M util/cbfstool/platform_fixups.c 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85629/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85629?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I019af6fbeca46e0e35d739a028655051fb466b48 Gerrit-Change-Number: 85629 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao

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[S] Change in coreboot[main]: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
by John Su (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85537?usp=email ) Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Could Reviwers help to submit this CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/85537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Gerrit-Change-Number: 85537 Gerrit-PatchSet: 7 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 18 Dec 2024 02:56:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Yidi Lin (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85630?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... Patch Set 3: (3 comments) File src/soc/mediatek/common/mt6316.c: https://review.coreboot.org/c/coreboot/+/85630/comment/24fa67cd_c34fb4f8?us… : PS2, Line 14: assert(pmif_arb); : pmif_arb->read(pmif_arb, slvid, reg, data); Please follow other PMICs' read/write semantic. ``` u16 data = 0; assert(pmif_arb); pmif_arb->read(pmif_arb, slvid, reg, &data); return data ``` File src/soc/mediatek/common/mt6316.c: https://review.coreboot.org/c/coreboot/+/85630/comment/909f11af_dfd702f8?us… : PS3, Line 164: 0x222 Is the mask correct ? Doesn't `pmif_arb->write` send one byte per call ? https://review.coreboot.org/c/coreboot/+/85630/comment/75f92109_663348cc?us… : PS3, Line 169: reg_val_6 We expect to read one byte back, right ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 18 Dec 2024 02:49:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: Add SD card configurations
by Yidi Lin (Code Review) 18 Dec '24

18 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85565?usp=email ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Add SD card configurations ...................................................................... mb/google/rauru: Add SD card configurations Rauru reference design has SD card interfaces, so we configure it in mainboard_init() in ramstage. BUG=b:317009620 TEST=Build pass. Check storage in depthcharge. firmware-shell: storage init * 0: UFS LUN 0 1: removable mtk_mmc Change-Id: Ia9f12df85c5f9f9d134990edcf82bf0df9ea995d Signed-off-by: Andy-ld Lu <andy-ld.lu(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85565 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/mainboard.c 2 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index a85f303..18a1699 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -30,6 +30,8 @@ select I2C_TPM if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT select TPM_GOOGLE_TI50 if VBOOT + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_MMC config MAINBOARD_DIR string diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c index 9c238c7..c1a4347 100644 --- a/src/mainboard/google/rauru/mainboard.c +++ b/src/mainboard/google/rauru/mainboard.c @@ -9,6 +9,7 @@ #include <soc/dpm_v2.h> #include <soc/gpio_common.h> #include <soc/i2c.h> +#include <soc/msdc.h> #include <soc/pcie.h> #include <soc/usb.h> @@ -55,6 +56,9 @@ power_on_fpmcu(); configure_audio(); + if (CONFIG(RAURU_SDCARD_INIT)) + mtk_msdc_configure_sdcard(); + if (dpm_init()) printk(BIOS_ERR, "dpm init failed, DVFS may not work\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/85565?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9f12df85c5f9f9d134990edcf82bf0df9ea995d Gerrit-Change-Number: 85565 Gerrit-PatchSet: 13 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add SD card configurations
by Yidi Lin (Code Review) 18 Dec '24

18 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85564?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add SD card configurations ...................................................................... soc/mediatek/mt8196: Add SD card configurations Rauru reference design has SD card interfaces, so we have to configure it in ramstage. Implement msdc.c (memory and SD Card controller) to place the SD card drivers. This implementation is based on chapter 10.3 in MT8196 Functional Specification. TEST=Build pass BUG=b:317009620 Change-Id: Ibb6a075d0f1b5a647e93a58b3ea1029b7676c765 Signed-off-by: Andy-ld Lu <andy-ld.lu(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85564 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/msdc.c 2 files changed, 37 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 2af541f..2e78e1a 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -47,6 +47,7 @@ ramstage-y += ../common/mcu.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += msdc.c ramstage-y += ../common/mt6363.c mt6363.c ramstage-y += ../common/mt6363_sdmadc.c ramstage-y += ../common/mt6373.c mt6373.c diff --git a/src/soc/mediatek/mt8196/msdc.c b/src/soc/mediatek/mt8196/msdc.c new file mode 100644 index 0000000..f787374 --- /dev/null +++ b/src/soc/mediatek/mt8196/msdc.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 10.3 + */ + +#include <gpio.h> +#include <soc/msdc.h> +#include <soc/regulator.h> + +static const struct pad_func sdcard_pins[] = { + PAD_FUNC_DOWN(MSDC1_CLK, MSDC1_CLK), + PAD_FUNC_UP(MSDC1_CMD, MSDC1_CMD), + PAD_FUNC_UP(MSDC1_DAT0, MSDC1_DAT0), + PAD_FUNC_UP(MSDC1_DAT1, MSDC1_DAT1), + PAD_FUNC_UP(MSDC1_DAT2, MSDC1_DAT2), + PAD_FUNC_UP(MSDC1_DAT3, MSDC1_DAT3), +}; + +void mtk_msdc_configure_sdcard(void) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(sdcard_pins); i++) { + gpio_set_mode(sdcard_pins[i].gpio, sdcard_pins[i].func); + gpio_set_pull(sdcard_pins[i].gpio, GPIO_PULL_ENABLE, sdcard_pins[i].select); + gpio_set_driving(sdcard_pins[i].gpio, GPIO_DRV_6_MA); + } + + /* enable SD card power */ + mainboard_enable_regulator(MTK_REGULATOR_VMCH, true); + mainboard_enable_regulator(MTK_REGULATOR_VMC, true); + mainboard_set_regulator_voltage(MTK_REGULATOR_VMCH, 3000000); + mainboard_set_regulator_voltage(MTK_REGULATOR_VMC, 3000000); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb6a075d0f1b5a647e93a58b3ea1029b7676c765 Gerrit-Change-Number: 85564 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Yidi Lin (Code Review) 18 Dec '24

18 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84929?usp=email ) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... soc/mediatek/mt8196: Add tracker driver Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. Rename VLPCFG_BASE to VLP_CFG_BASE. TEST=Build pass, When we encounter a bus hang and HW watchdog triggers a reset to the platform, the tracker will print the latched information: [INFO ] **Dump %s aw debug register start** [INFO ] xxxxxx, 0x1c600000, 0x0, 63 This means that the 63rd entry latch accessing 0x1c600000 has a bus timeout. BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84929 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/tracker.h A src/soc/mediatek/mt8196/tracker.c 5 files changed, 175 insertions(+), 1 deletion(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 13ba5c3..2af541f 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -19,6 +19,7 @@ bootblock-y += ../common/mmu_operations.c bootblock-y += mtcmos.c bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c +bootblock-y += tracker.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c index d675a5a..95555d1 100644 --- a/src/soc/mediatek/mt8196/bootblock.c +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -8,12 +8,14 @@ #include <soc/mmu_operations.h> #include <soc/pll.h> #include <soc/spm_mtcmos.h> +#include <soc/tracker.h> #include <soc/wdt.h> void bootblock_soc_init(void) { booker_init(); mtk_mmu_init(); + bustracker_init(); lastbus_init(); mtk_wdt_init(); mt_pll_init(); diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 3de16fd..dc21f60 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -143,7 +143,7 @@ APINFRA_SSR_AO_DEBUG_BASE = IO_PHYS + 0x080F1000, AUDIO_BASE = IO_PHYS + 0x0A110000, VLP_AO_BASE = IO_PHYS + 0x0C000000, - VLPCFG_BASE = IO_PHYS + 0x0C001000, + VLP_CFG_BASE = IO_PHYS + 0x0C001000, SPM_BASE = IO_PHYS + 0x0C004000, SPM_PBUS_BASE = IO_PHYS + 0x0C00D000, RGU_BASE = IO_PHYS + 0x0C010000, diff --git a/src/soc/mediatek/mt8196/include/soc/tracker.h b/src/soc/mediatek/mt8196/include/soc/tracker.h new file mode 100644 index 0000000..c82ee83 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/tracker.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef SOC_MEDIATEK_MT8196_TRACKER_H +#define SOC_MEDIATEK_MT8196_TRACKER_H + +#include <soc/tracker_common.h> +#include <stdint.h> + +#define BUS_DBG_CON 0x000 +#define BUS_TRACE_CON_AO_PRESCALE 0x8f8 +#define BUS_TRACE_CON_AO_1_PRESCALE 0x9f8 +#define VLP_TRACE_CON_AO_PRESCALE 0x114 +#define BUS_TRACE_CON_1 0x800 +#define BUS_TRACE_CON_AO_1 0x8FC +#define BUS_TRACE_CON_2 0x900 +#define BUS_TRACE_CON_AO_2 0x9FC +#define VLP_CON_AO 0x30C +#define BUS_TRACE_EN 16 + +#define SYS_TRACK_ENTRY 64 +#define INFRA_ENTRY_NUM 32 +#define VLP_ENTRY_NUM 4 + +#define AR_TRACK_LOG_OFFSET 0x0200 +#define AR_ENTRY_ID_OFFSET 0x0300 +#define AR_TRACK_L_OFFSET 0x0400 +#define AR_TRACK_H_OFFSET 0x0600 +#define AW_TRACK_LOG_OFFSET 0x0800 +#define AW_ENTRY_ID_OFFSET 0x0900 +#define AW_TRACK_L_OFFSET 0x0A00 +#define AW_TRACK_H_OFFSET 0x0C00 + +#define BUSTRACKER_TIMEOUT 0x300 + +enum { + TRACKER_SYSTRACKER = 0, + TRACKER_INFRATRACKER, + TRACKER_VLPSYSTRACKER, + TRACKER_NUM, +}; + +#endif diff --git a/src/soc/mediatek/mt8196/tracker.c b/src/soc/mediatek/mt8196/tracker.c new file mode 100644 index 0000000..1fc03b99 --- /dev/null +++ b/src/soc/mediatek/mt8196/tracker.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/bsd/helpers.h> +#include <console/console.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/tracker.h> + +/* + * for systracker: + * offset[0] dump from offset 0x100 ~ 0x2F8 + * offset[1] dump from offset 0x300 ~ 0x4FC + * + * for infra tracker: + * offset[0] dump from offset 0x100 ~ 0x1F8 + * offset[1] dump from offset 0x300 ~ 0x3FC + * + * for vlpsys tracker: + * offset[0] dump from offset 0x100 ~ 0x2F8 + * offset[1] dump from offset 0x300 ~ 0x4FC + */ + +static const u32 offsets[] = { + AR_TRACK_LOG_OFFSET, AR_ENTRY_ID_OFFSET, AR_TRACK_L_OFFSET, + AR_TRACK_H_OFFSET, AW_TRACK_LOG_OFFSET, AW_ENTRY_ID_OFFSET, + AW_TRACK_L_OFFSET, AW_TRACK_H_OFFSET, +}; + +struct tracker tracker_data[TRACKER_NUM] = { + [TRACKER_SYSTRACKER] = { + .base_addr = INFRA_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = SYS_TRACK_ENTRY, + .offsets = offsets, + .offsets_size = ARRAY_SIZE(offsets), + .str = "systracker", + }, + [TRACKER_INFRATRACKER] = { + .base_addr = INFRA_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = INFRA_ENTRY_NUM, + .offsets = offsets, + .offsets_size = ARRAY_SIZE(offsets), + .str = "infra_tracker", + }, + [TRACKER_VLPSYSTRACKER] = { + .base_addr = VLP_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = VLP_ENTRY_NUM, + .offsets = offsets, + .offsets_size = ARRAY_SIZE(offsets), + .str = "vlp_tracker", + }, +}; + +void tracker_setup(void) +{ + u32 val; + /* + * Set infra/peri tracker timeout. + * timeout = clock_in_mhz / 15 * timeout_in_us + * + * timeout: 10ms + * ap tracker clock: 26MHz + * infra tracker clock: 26MHz + * vlp tracker clock: 26MHz + */ + val = 26 / 15 * 10000; + + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_PRESCALE, val); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1_PRESCALE, val); + write32p(VLP_CFG_BASE + VLP_TRACE_CON_AO_PRESCALE, val); + /* + * Enable infra/peri tracker. + * bit[0] - BUS_DBG_EN + * bit[1] - TIMEOUT_EN + * bit[2] - SLV_ERR_EN + * bit[13] - HALT_ON_TIMEOUT_EN + * bit[14] - BUS_OT_WEN_CTRL + */ + val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); + write32p(VLP_AO_BASE + VLP_CON_AO, val); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1, val); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2, val); +} + +static void tracker_dump_data(void) +{ + u64 reg_entry; + int i, j; + uintptr_t reg_log, reg_id, reg_low, reg_high; + struct tracker *tra; + + for (j = 0; j < TRACKER_NUM; j++) { + tra = &tracker_data[j]; + + if (!(read32p(tra->base_addr) & tra->timeout)) + continue; + printk(BIOS_INFO, "**Dump %s ar debug register start**\n", tra->str); + for (i = 0; i < tra->entry; i++) { + reg_log = tra->base_addr + tra->offsets[0] + i * 4; + reg_id = tra->base_addr + tra->offsets[1] + i * 4; + reg_low = tra->base_addr + tra->offsets[2] + i * 4; + reg_high = tra->base_addr + tra->offsets[3] + i * 4; + reg_entry = ((u64)read32p(reg_high)) << 32 | read32p(reg_low); + printk(BIOS_INFO, "%#lx:%#x:%#x:%#x:%#x:%#llx\n", + reg_low, read32p(reg_log), read32p(reg_id), read32p(reg_low), + read32p(reg_high), reg_entry); + } + printk(BIOS_INFO, "**Dump %s aw debug register start**\n", tra->str); + for (i = 0; i < tra->entry; i++) { + reg_log = tra->base_addr + tra->offsets[4] + i * 4; + reg_id = tra->base_addr + tra->offsets[5] + i * 4; + reg_low = tra->base_addr + tra->offsets[6] + i * 4; + reg_high = tra->base_addr + tra->offsets[7] + i * 4; + reg_entry = ((u64)read32p(reg_high)) << 32 | read32p(reg_low); + printk(BIOS_INFO, "%#lx:%#x:%#x:%#x:%#x:%#llx\n", + reg_low, read32p(reg_log), read32p(reg_id), read32p(reg_low), + read32p(reg_high), reg_entry); + } + printk(BIOS_INFO, "**Dump %s debug register end**\n", tra->str); + } +} + +void bustracker_init(void) +{ + tracker_dump_data(); + tracker_setup(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 32 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MMinfra driver support
by Yidi Lin (Code Review) 18 Dec '24

18 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85188?usp=email ) Change subject: soc/mediatek/mt8196: Add MMinfra driver support ...................................................................... soc/mediatek/mt8196: Add MMinfra driver support MMinfra is the Multimedia Infrastructure. All the Multimedia modules depend on it. This file adds some initial settings for MMinfra. Test=Build pass BUG=b:317009620 Signed-off-by: Xueqi Zhang <xueqi.zhang(a)mediatek.corp-partner.google.com> Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85188 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/mminfra.h A src/soc/mediatek/mt8196/mminfra.c 5 files changed, 160 insertions(+), 1 deletion(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 9652a1e..13ba5c3 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -15,6 +15,7 @@ bootblock-y += ../common/bootblock.c bootblock.c bootblock-y += ../common/early_init.c bootblock-y += ../common/lastbus_v2.c lastbus.c +bootblock-y += mminfra.c bootblock-y += ../common/mmu_operations.c bootblock-y += mtcmos.c bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c index a864bff..d675a5a 100644 --- a/src/soc/mediatek/mt8196/bootblock.c +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -4,6 +4,7 @@ #include <bootblock_common.h> #include <soc/early_init.h> #include <soc/lastbus_v2.h> +#include <soc/mminfra.h> #include <soc/mmu_operations.h> #include <soc/pll.h> #include <soc/spm_mtcmos.h> @@ -17,6 +18,7 @@ mtk_wdt_init(); mt_pll_init(); mtcmos_init(); + mminfra_post_init(); mt_pll_post_init(); mtcmos_post_init(); early_init_clear(); diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index cc57292..3de16fd 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -142,6 +142,7 @@ SSR_TOP_BASE = IO_PHYS + 0x08000000, APINFRA_SSR_AO_DEBUG_BASE = IO_PHYS + 0x080F1000, AUDIO_BASE = IO_PHYS + 0x0A110000, + VLP_AO_BASE = IO_PHYS + 0x0C000000, VLPCFG_BASE = IO_PHYS + 0x0C001000, SPM_BASE = IO_PHYS + 0x0C004000, SPM_PBUS_BASE = IO_PHYS + 0x0C00D000, @@ -171,7 +172,13 @@ MMVOTE_CAM_MAIN_R1A_BASE = IO_PHYS + 0x1A000000, MMVOTE_CCU_MAIN_BASE = IO_PHYS + 0x1C800000, MMVOTE_DISP_VDISP_AO_CONFIG_BASE = IO_PHYS + 0x1E800000, - MMUP_AO_DEBUG_BASE = IO_PHYS + 0x21A22000, + MMINFRA_CONFIG = IO_PHYS + 0x20000000, + MMINFRA_SEC_CONFIG = IO_PHYS + 0x20010000, + MMINFRA_AO_CONFIG = IO_PHYS + 0x20080000, + MMINFRA_BUS_HRE_BASE = IO_PHYS + 0x200A0000, + MMINFRA_BUS_HRE2_BASE = IO_PHYS + 0x200B0000, + MMINFRA1_CONFIG = IO_PHYS + 0x20A00000, + MMUP_AO_DEBUG_BASE = IO_PHYS + 0x21A22000, MMVOTE_BASE = IO_PHYS + 0x21B00000, MMPC_BASE = IO_PHYS + 0x21B50000, MMSYS_CONFIG_BASE = IO_PHYS + 0x22000000, diff --git a/src/soc/mediatek/mt8196/include/soc/mminfra.h b/src/soc/mediatek/mt8196/include/soc/mminfra.h new file mode 100644 index 0000000..13a4e5c --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/mminfra.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MMINFRA_H__ +#define __SOC_MEDIATEK_MMINFRA_H__ + +/* mminfra_ao */ +#define MMINFRA_GCE_PROT_EN (MMINFRA_AO_CONFIG + 0x428) + +/* mminfra0 */ +#define MMINFRA_MM0_GALS_PROT_RX_EN (MMINFRA_CONFIG + 0x9C0) +#define MMINFRA_MM0_GALS_PROT_RX_RDY (MMINFRA_CONFIG + 0x9C4) +#define MMINFRA_MM0_GALS_PROT_TX_EN (MMINFRA_CONFIG + 0x9C8) +#define MMINFRA_MM0_GALS_PROT_TX_RDY (MMINFRA_CONFIG + 0x9CC) +#define MMINFRA_MM1_GALS_PROT_RX_EN (MMINFRA_CONFIG + 0x9D0) +#define MMINFRA_MM1_GALS_PROT_RX_RDY (MMINFRA_CONFIG + 0x9D4) +#define MMINFRA_MM1_GALS_PROT_TX_EN (MMINFRA_CONFIG + 0x9D8) +#define MMINFRA_MM1_GALS_PROT_TX_RDY (MMINFRA_CONFIG + 0x9DC) + +#define GCE_D_SLEEPPORT_RX_EN BIT(0) +#define GCE_D_HAND_SLEEPPORT_RX_EN BIT(1) +#define GCE_D_HAND_SLEEPPORT_TX_EN BIT(2) +#define GCE_M_SLEEPPORT_RX_EN BIT(8) +#define GCE_M_HAND_SLEEPPORT_RX_EN BIT(9) +#define GCE_M_HAND_SLEEPPORT_TX_EN BIT(10) + +#define VLP_AO_RSVD6 (VLP_AO_BASE + 0x918) + +/* mmpc */ +#define MMPC_PM_BOOT_UP_PWR_CON (MMPC_BASE + 0x1B8) +#define MM_INFRA0_PM_BOOT_UP BIT(16) +#define MM_INFRA1_PM_BOOT_UP BIT(17) + +void mminfra_post_init(void); + +#endif diff --git a/src/soc/mediatek/mt8196/mminfra.c b/src/soc/mediatek/mt8196/mminfra.c new file mode 100644 index 0000000..55ddf47 --- /dev/null +++ b/src/soc/mediatek/mt8196/mminfra.c @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/mminfra.h> +#include <soc/spm_mtcmos.h> +#include <stddef.h> +#include <string.h> +#include <timer.h> +#include <types.h> + +#define TIMEOUT_US 20 + +static void wait_for_write_done(u32 write_reg, u32 status_reg, u32 val) +{ + write32p(write_reg, val); + + if (!wait_us(TIMEOUT_US, read32p(status_reg) == val)) + die("Wait write done timeout\n"); +} + +static void mm_gce_lock_prot_en(void) +{ + setbits32p(MMINFRA_GCE_PROT_EN, + GCE_D_SLEEPPORT_RX_EN | GCE_D_HAND_SLEEPPORT_RX_EN | + GCE_D_HAND_SLEEPPORT_TX_EN | GCE_M_SLEEPPORT_RX_EN | + GCE_M_HAND_SLEEPPORT_RX_EN | GCE_M_HAND_SLEEPPORT_TX_EN); +} + +static void mm_gce_release_prot_en(void) +{ + write32p(MMINFRA_GCE_PROT_EN, 0); +} + +static void mm_infra0_lock_prot_en(void) +{ + wait_for_write_done(MMINFRA_MM0_GALS_PROT_TX_EN, + MMINFRA_MM0_GALS_PROT_TX_RDY, 0xff); + wait_for_write_done(MMINFRA_MM0_GALS_PROT_RX_EN, + MMINFRA_MM0_GALS_PROT_RX_RDY, 0xfffff); +} + +static void mm_infra0_release_prot_en(void) +{ + write32p(MMINFRA_MM0_GALS_PROT_RX_EN, 0); + write32p(MMINFRA_MM0_GALS_PROT_TX_EN, 0); +} + +static void mm_infra1_lock_prot_en(void) +{ + mm_gce_lock_prot_en(); + wait_for_write_done(MMINFRA_MM1_GALS_PROT_TX_EN, + MMINFRA_MM1_GALS_PROT_TX_RDY, 0x3f); + wait_for_write_done(MMINFRA_MM1_GALS_PROT_RX_EN, + MMINFRA_MM1_GALS_PROT_RX_RDY, 0xf); +} + +static void mm_infra1_release_prot_en(void) +{ + write32p(MMINFRA_MM1_GALS_PROT_RX_EN, 0); + write32p(MMINFRA_MM1_GALS_PROT_TX_EN, 0); + mm_gce_release_prot_en(); +} + +static int pd_mm_infra0_pre_on(void) +{ + setbits32p(MMPC_PM_BOOT_UP_PWR_CON, MM_INFRA0_PM_BOOT_UP | MM_INFRA1_PM_BOOT_UP); + return 0; +} + +static int pd_mm_infra0_post_on(void) +{ + mm_infra0_release_prot_en(); + return 0; +} + +static int pd_mm_infra0_pre_off(void) +{ + mm_infra0_lock_prot_en(); + return 0; +} + +static int pd_mm_infra1_post_on(void) +{ + mm_infra1_release_prot_en(); + write32p(VLP_AO_RSVD6, 0x1); + return 0; +} + +static int pd_mm_infra1_pre_off(void) +{ + mm_infra1_lock_prot_en(); + return 0; +} + +static struct mtcmos_cb mm_infra0_pb_cb = { + .pre_on = pd_mm_infra0_pre_on, + .post_on = pd_mm_infra0_post_on, + .pre_off = pd_mm_infra0_pre_off, +}; + +static struct mtcmos_cb mm_infra1_pb_cb = { + .post_on = pd_mm_infra1_post_on, + .pre_off = pd_mm_infra1_pre_off, +}; + +void mminfra_post_init(void) +{ + if (mtcmos_cb_register(MTCMOS_ID_MM_INFRA0, &mm_infra0_pb_cb)) + return; + + mtcmos_cb_register(MTCMOS_ID_MM_INFRA1, &mm_infra1_pb_cb); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75 Gerrit-Change-Number: 85188 Gerrit-PatchSet: 28 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Enable eMMC and DLL tuning parameters
by Dtrain Hsu (Code Review) 18 Dec '24

18 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, John Su, Nick Vaccaro, Subrata Banik. Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85579?usp=email ) Change subject: mb/trulo/var/uldrenite: Enable eMMC and DLL tuning parameters ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f0fdb31ce4eaad5537df36c4165c404239a7bd4 Gerrit-Change-Number: 85579 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 18 Dec 2024 02:39:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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