coreboot-gerrit January 2024

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[S] Change in coreboot[main]: vc/amd/opensil/genoa_poc: move configure_mpio call to setup_opensil
by Felix Held (Code Review) 22 Jan '24

22 Jan '24

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80148?usp=email ) Change subject: vc/amd/opensil/genoa_poc: move configure_mpio call to setup_opensil ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: still needs to be tested on harwdare -- To view, visit https://review.coreboot.org/c/coreboot/+/80148?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If37077c879e266763fd2748a1a8d71c63c94729b Gerrit-Change-Number: 80148 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 22 Jan 2024 17:44:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/genoa_poc: rely less on boot state hooks
by Felix Held (Code Review) 22 Jan '24

22 Jan '24

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79985?usp=email ) Change subject: soc/amd/genoa_poc: rely less on boot state hooks ...................................................................... Patch Set 2: (2 comments) This change is ready for review. Patchset: PS1: > hmm, this might cause some sequencing problems for the mpio config Done Patchset: PS2: still needs to be tested on hardware -- To view, visit https://review.coreboot.org/c/coreboot/+/79985?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic752635da5eaa9e333cfb927836f0d260d2ac049 Gerrit-Change-Number: 79985 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Comment-Date: Mon, 22 Jan 2024 17:43:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: [WIP] vc/amd/opensil/genoa_poc: add TODO
by Felix Held (Code Review) 22 Jan '24

22 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80149?usp=email ) Change subject: [WIP] vc/amd/opensil/genoa_poc: add TODO ...................................................................... [WIP] vc/amd/opensil/genoa_poc: add TODO When the device right below the MPIO chip driver has downstream devices without another chip in between, those downstream devices will also have their chip_ops entry set to vendorcode_amd_opensil_genoa_poc_mpio_ops resulting in non-expected behavior. This still needs to be addressed, but for now add a TODO. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6ba90fdc83ba089127e6722778bfef29dd480bb4 --- M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/80149/1 diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 28e529d..8174e2e 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -189,5 +189,7 @@ /* Find all devices with this chip */ for (struct device *dev = &dev_root; dev; dev = dev->next) if (dev->chip_ops == &vendorcode_amd_opensil_genoa_poc_mpio_ops) + /* TODO: add check to only run this for devices right below the MPIO + chip and not their child devices */ per_device_config(mpio_data, dev->bus->dev, dev->chip_info); } -- To view, visit https://review.coreboot.org/c/coreboot/+/80149?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ba90fdc83ba089127e6722778bfef29dd480bb4 Gerrit-Change-Number: 80149 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: vc/amd/opensil/genoa_poc: move configure_mpio call to setup_opensil
by Felix Held (Code Review) 22 Jan '24

22 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80148?usp=email ) Change subject: vc/amd/opensil/genoa_poc: move configure_mpio call to setup_opensil ...................................................................... vc/amd/opensil/genoa_poc: move configure_mpio call to setup_opensil Instead of calling configure_mpio from the init function of the MPIO chip struct for the first device that has this struct as chip_ops, call if from setup_opensil. This will allow to do the calls into openSIL from the SoC's chip_ops init function instead of having to rely on boot state hooks. configure_mpio needs to be call after the xSimAssignMemoryTp1 call which sets up the openSIL data structures, but before the opensil_entry(SIL_TP1) call for which the MPIO data structures need to be filled for it to be able to initialize the hardware accordingly. Since the vendorcode_amd_opensil_genoa_poc_mpio_ops struct now no longer assigns configure_mpio to the init function pointer, we have to check if the device's chip_ops pointer points to vendorcode_amd_opensil_genoa_poc_mpio_ops instead of checking if the chip_ops' init function is configure_mpio to match for the devices below the MPIO chips in the devicetree. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If37077c879e266763fd2748a1a8d71c63c94729b --- M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c M src/vendorcode/amd/opensil/genoa_poc/opensil.h M src/vendorcode/amd/opensil/genoa_poc/ramstage.c 3 files changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/80148/1 diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 49a8934..28e529d 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -7,6 +7,11 @@ #include <device/device.h> #include <device/pci_def.h> #include "chip.h" +#include "../opensil.h" + +struct chip_operations vendorcode_amd_opensil_genoa_poc_mpio_ops = { + CHIP_NAME("AMD GENOA MPIO") +}; static void nbio_config(void) { @@ -175,7 +180,7 @@ mpio_port++; } -static void configure_mpio(void *const config) +void configure_mpio(void) { MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0); mpio_global_config(mpio_data); @@ -183,11 +188,6 @@ /* Find all devices with this chip */ for (struct device *dev = &dev_root; dev; dev = dev->next) - if (dev->chip_ops->init == configure_mpio) + if (dev->chip_ops == &vendorcode_amd_opensil_genoa_poc_mpio_ops) per_device_config(mpio_data, dev->bus->dev, dev->chip_info); } - -struct chip_operations vendorcode_amd_opensil_genoa_poc_mpio_ops = { - CHIP_NAME("AMD GENOA MPIO") - .init = configure_mpio, -}; diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil.h b/src/vendorcode/amd/opensil/genoa_poc/opensil.h index b9caf73..fbf46b3 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/opensil.h +++ b/src/vendorcode/amd/opensil/genoa_poc/opensil.h @@ -11,4 +11,6 @@ // Fill in FADT from openSIL void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt); +void configure_mpio(void); + #endif diff --git a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c index 7c0bc5b..7d03b32 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c @@ -126,6 +126,7 @@ setup_rc_manager_default(); configure_usb(); configure_sata(); + configure_mpio(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, setup_opensil, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/80148?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If37077c879e266763fd2748a1a8d71c63c94729b Gerrit-Change-Number: 80148 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: vc/amd/opensil/genoa_poc/mpio: rename mpio_config to configure_mpio
by Felix Held (Code Review) 22 Jan '24

22 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80147?usp=email ) Change subject: vc/amd/opensil/genoa_poc/mpio: rename mpio_config to configure_mpio ...................................................................... vc/amd/opensil/genoa_poc/mpio: rename mpio_config to configure_mpio As a preparation for the following patch, rename mpio_config to configure_mpio to make it both a bit more descriptive and to match the naming scheme used for the functions that get called by setup_opensil. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic4b1aa6e964cbbb4affb89cacd33af8b24871bb6 --- M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/80147/1 diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index c268293..49a8934 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -175,7 +175,7 @@ mpio_port++; } -static void mpio_config(void *const config) +static void configure_mpio(void *const config) { MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0); mpio_global_config(mpio_data); @@ -183,11 +183,11 @@ /* Find all devices with this chip */ for (struct device *dev = &dev_root; dev; dev = dev->next) - if (dev->chip_ops->init == mpio_config) + if (dev->chip_ops->init == configure_mpio) per_device_config(mpio_data, dev->bus->dev, dev->chip_info); } struct chip_operations vendorcode_amd_opensil_genoa_poc_mpio_ops = { CHIP_NAME("AMD GENOA MPIO") - .init = mpio_config, + .init = configure_mpio, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/80147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4b1aa6e964cbbb4affb89cacd33af8b24871bb6 Gerrit-Change-Number: 80147 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: 3rdparty/fsp: Update submodule to upstream master
by Felix Singer (Code Review) 22 Jan '24

22 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80044?usp=email ) Change subject: 3rdparty/fsp: Update submodule to upstream master ...................................................................... 3rdparty/fsp: Update submodule to upstream master Updating from commit id bb12f17: 2023-10-31 16:00:43 +0800 - (Elkhart Lake MR7 FSP) to commit id 507ef01: 2024-01-11 10:49:14 +0800 - (IoT ADL-S MR6 (4115_09) FSP) This brings in 11 new commits: 507ef01 IoT ADL-S MR6 (4115_09) FSP 43f7092 IoT RPL-S MR2 (4415_02) FSP 848c499 Eagle Stream FSP 1.1.1.316 27e8376 Add Eagle Stream FSP 297e085 Add Third-Party Licenses 554f240 IoT RPL-S MR2 (4415_02) FSP 5b72773 IoT ADL-N MR3 (4413_00) 3ab4b5a IoT ADL-PS MR4 (4115_09) FSP 8267065 IoT ADL-PS MR3 (4081_07) FSP 5e8dae0 IoT ADL-N MR2 (4282_00) 8beacd5 WhitleyFspBinPkg: Fix warnings when building with GCC Change-Id: I03b32e52adcdcaa0ac7f919aca5d459ad53db3bf Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80044 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/3rdparty/fsp b/3rdparty/fsp index bb12f17..507ef01 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit bb12f17b07700a40c0033da345eae0c1cd487b73 +Subproject commit 507ef01cce16dc1e1af898e60de96dbb8e9d6d17 -- To view, visit https://review.coreboot.org/c/coreboot/+/80044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03b32e52adcdcaa0ac7f919aca5d459ad53db3bf Gerrit-Change-Number: 80044 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: cpu/x86: Add 1GiB pages for memory access up to 512GiB
by Jérémy Compostella (Code Review) 22 Jan '24

22 Jan '24

Attention is currently required from: Ashish Kumar Mishra, Subrata Banik, Wonkyu Kim. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80088?usp=email ) Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB ...................................................................... Patch Set 3: (2 comments) File src/cpu/x86/64bit/pt1G.S: https://review.coreboot.org/c/coreboot/+/80088/comment/83b06ebc_2b3d92c9 : PS3, Line 4: Page table attributes: WB, User+Supervisor, Present, Writeable, Accessed, Dirty : */ missing leading space on line 4 and 5. File src/cpu/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/80088/comment/fb50b153_a7cdb364 : PS3, Line 157: Select this option to access above 4GiB pagetable using 1GiB pages, upto : 512GiB, instead of the default access below 4GiB using 2MiB pages. What about: `USE_1G_PAGES_TLB` ? What about the following: `Enable access to up to 512 GiB of memory by using 1 GiB large pages.` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/80088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec Gerrit-Change-Number: 80088 Gerrit-PatchSet: 3 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 22 Jan 2024 17:19:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Makefile.inc: Compress DSDT file
by Jérémy Compostella (Code Review) 22 Jan '24

22 Jan '24

Attention is currently required from: Arthur Heymans, Martin L Roth, Subrata Banik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75905?usp=email ) Change subject: Makefile.inc: Compress DSDT file ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75905/comment/7c1b8df6_fcb6f307 : PS4, Line 9: dsdt `s/dsdt/DSDT ACPI table/` https://review.coreboot.org/c/coreboot/+/75905/comment/424ef62e_34d395eb : PS4, Line 11: 128K I believe you meant 64 KiB. File Makefile.inc: https://review.coreboot.org/c/coreboot/+/75905/comment/01e9aed2_4c27242e : PS4, Line 300: LZMA We have been using lower case for compression algorithm in most places according to `grep` so I would recommend to stick to lower case. -- To view, visit https://review.coreboot.org/c/coreboot/+/75905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f555b1761c7ef4943d8de447ab299684403214b Gerrit-Change-Number: 75905 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 22 Jan 2024 17:01:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cannonlake: Report correct latencies for C states
by Matt DeVillier (Code Review) 22 Jan '24

22 Jan '24

Attention is currently required from: Felix Singer, Nico Huber. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80167?usp=email ) Change subject: soc/intel/cannonlake: Report correct latencies for C states ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: what's the source for the corrected values? -- To view, visit https://review.coreboot.org/c/coreboot/+/80167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie01a53d6f06bc02a53d95e390e16e9963f4c65ee Gerrit-Change-Number: 80167 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 22 Jan 2024 16:53:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: 3rdparty/fsp: Update submodule to upstream master
by Matt DeVillier (Code Review) 22 Jan '24

22 Jan '24

Attention is currently required from: Felix Singer, Martin L Roth, Michał Żygowski. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80044?usp=email ) Change subject: 3rdparty/fsp: Update submodule to upstream master ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03b32e52adcdcaa0ac7f919aca5d459ad53db3bf Gerrit-Change-Number: 80044 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 22 Jan 2024 16:52:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2024