Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Maximilian Brune, Nico Huber, Paul Menzel, Tim Chu.
Hello Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Maximilian Brune, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78332?usp=email
to look at the new patch set (#20).
Change subject: soc/intel/xeon_sp: Scan and allocate resources on all stacks
......................................................................
soc/intel/xeon_sp: Scan and allocate resources on all stacks
The code can now deal with stacks that have no resources so just hook
them all up.
Intel XEON-SP FSP reports all report the state of its stacks, which
comprise of PCI root bridges and their respective resources, like PCI
busses, IO and MEM resources, via HOB. Parsing all of those into native
coreboot structures makes it possible to handle those in a more native
fashion like use PCI drivers, native helper functions, ... As opposed
parsing those structures again out of the HOB each time. This makes code
reuse across the tree more feasible.
An additional advantage is that Linux does not need to redo resource
allocation since the one done by coreboot will be valid, which
potentially decreases boot time.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Change-Id: Id72c6e4499e99df3b7ca821ab2893cbcc869dbcd
---
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/util.c
8 files changed, 27 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/78332/20
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Id72c6e4499e99df3b7ca821ab2893cbcc869dbcd
Gerrit-Change-Number: 78332
Gerrit-PatchSet: 20
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com>
Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Nico Huber <nico.h(a)gmx.de>
Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com>
Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>
Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>
Gerrit-MessageType: newpatchset
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80048?usp=email )
Change subject: mb/hp/snb_ivb_laptops: Convert remaining PCI numbers into references
......................................................................
mb/hp/snb_ivb_laptops: Convert remaining PCI numbers into references
Change-Id: I58e5dfa57856e80d1a5e4a6fab0b2523301fa8f2
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80048
Reviewed-by: Thomas Heijligen <src(a)posteo.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Riku Viitanen <riku.viitanen(a)protonmail.com>
---
M src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb
M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb
10 files changed, 119 insertions(+), 119 deletions(-)
Approvals:
Thomas Heijligen: Looks good to me, approved
Riku Viitanen: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb
index 8f35eee..433d798 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb
@@ -7,8 +7,8 @@
device domain 0 on
subsystemid 0x103c 0x1815 inherit
- device pci 01.0 off end # PCIe Bridge for discrete graphics
- device pci 02.0 on end # Internal graphics
+ device ref peg10 off end # PCIe Bridge for discrete graphics
+ device ref igd on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
# mailbox at 0x200/0x201 and PM1 at 0x220
@@ -24,17 +24,17 @@
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
- device pci 14.0 on end # USB 3.0 Controller
- device pci 16.0 on end # Management Engine KT
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 on end # PCIe Port #3, SD/MMC
- device pci 1c.3 on end # PCIe Port #4, WLAN
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 off end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1f.0 on # LPC bridge
+ device ref xhci on end # USB 3.0 Controller
+ device ref mei1 on end # Management Engine KT
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 off end # PCIe Port #2
+ device ref pcie_rp3 on end # PCIe Port #3, SD/MMC
+ device ref pcie_rp4 on end # PCIe Port #4, WLAN
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref lpc on # LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x62"
register "ec_cmd_port" = "0x66"
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb
index d69a21e..a7b36e8 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb
@@ -7,8 +7,8 @@
device domain 0 on
subsystemid 0x103c 0x162b inherit
- device pci 01.0 off end # PEG
- device pci 02.0 on end # iGPU
+ device ref peg10 off end # PEG
+ device ref igd on end # iGPU
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# mailbox at 0x200/0x201 and PM1 at 0x220
@@ -21,24 +21,24 @@
# HDD(0), ODD(1), eSATA(4), dock eSATA(5)
register "sata_port_map" = "0x33"
- device pci 1c.0 off end # PCIe Port #1
- device pci 1c.1 on # PCIe Port #2, ExpressCard
+ device ref pcie_rp1 off end # PCIe Port #1
+ device ref pcie_rp2 on # PCIe Port #2, ExpressCard
smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort"
"ExpressCard Slot" "SlotDataBusWidth1X"
end
- device pci 1c.2 on end # PCIe Port #3, SD/MMC Host Controller
- device pci 1c.3 on # PCIe Port #4, WLAN
+ device ref pcie_rp3 on end # PCIe Port #3, SD/MMC Host Controller
+ device ref pcie_rp4 on # PCIe Port #4, WLAN
smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
"SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
end
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 on # PCIe Port #7, WWAN
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 on # PCIe Port #7, WWAN
smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
"SlotLengthLong" "Mini PCIe" "SlotDataBusWidth1X"
end
- device pci 1c.7 off end # PCIe Port #8
- device pci 1f.0 on # LPC bridge
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref lpc on # LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x60"
register "ec_cmd_port" = "0x64"
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb
index d89492f..ced850a 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb
@@ -7,8 +7,8 @@
device domain 0 on
subsystemid 0x103c 0x17df inherit
- device pci 01.0 off end # PCIe Bridge for discrete graphics
- device pci 02.0 on end # Internal graphics
+ device ref peg10 off end # PCIe Bridge for discrete graphics
+ device ref igd on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# mailbox at 0x200/0x201 and PM1 at 0x220
@@ -23,16 +23,16 @@
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
- device pci 14.0 on end # USB 3.0 Controller
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #2, ExpressCard
- device pci 1c.2 on end # PCIe Port #3, SD/MMC
- device pci 1c.3 on end # PCIe Port #4, WLAN
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 off end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1f.0 on # LPC bridge
+ device ref xhci on end # USB 3.0 Controller
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 on end # PCIe Port #2, ExpressCard
+ device ref pcie_rp3 on end # PCIe Port #3, SD/MMC
+ device ref pcie_rp4 on end # PCIe Port #4, WLAN
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref lpc on # LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x62"
register "ec_cmd_port" = "0x66"
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb
index d911112..bd976bc 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb
@@ -7,8 +7,8 @@
device domain 0 on
subsystemid 0x103c 0x162a inherit
- device pci 01.0 off end # PCIe Bridge for discrete graphics
- device pci 02.0 on end # Internal graphics
+ device ref peg10 off end # PCIe Bridge for discrete graphics
+ device ref igd on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# mailbox at 0x200/0x201 and PM1 at 0x220
@@ -20,15 +20,15 @@
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
register "sata_port_map" = "0x21"
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #2, ExpressCard
- device pci 1c.2 on end # PCIe Port #3, SD/MMC
- device pci 1c.3 on end # WLAN
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 on end # PCIe Port #7, WWAN
- device pci 1c.7 off end # PCIe Port #8
- device pci 1f.0 on # LPC bridge
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 on end # PCIe Port #2, ExpressCard
+ device ref pcie_rp3 on end # PCIe Port #3, SD/MMC
+ device ref pcie_rp4 on end # WLAN
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 on end # PCIe Port #7, WWAN
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref lpc on # LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x60"
register "ec_cmd_port" = "0x64"
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb
index 02dc6a4..8d4d23f 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb
@@ -7,8 +7,8 @@
device domain 0 on
subsystemid 0x103c 0x161c inherit
- device pci 01.0 on end # PCIe Bridge for discrete graphics
- device pci 02.0 on end # Internal graphics
+ device ref peg10 on end # PCIe Bridge for discrete graphics
+ device ref igd on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# mailbox at 0x200/0x201 and PM1 at 0x220
@@ -21,16 +21,16 @@
# HDD(0), ODD(1), docking(3,5), eSATA(4)
register "sata_port_map" = "0x3b"
- device pci 16.3 on end # Management Engine KT
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #2, ExpressCard
- device pci 1c.2 on end # PCIe Port #3, SD/MMC
- device pci 1c.3 on end # PCIe Port #4, WLAN
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 on end # PCIe Port #7, WWAN
- device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller
- device pci 1f.0 on # LPC bridge
+ device ref me_kt on end # Management Engine KT
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 on end # PCIe Port #2, ExpressCard
+ device ref pcie_rp3 on end # PCIe Port #3, SD/MMC
+ device ref pcie_rp4 on end # PCIe Port #4, WLAN
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 on end # PCIe Port #7, WWAN
+ device ref pcie_rp8 on end # PCIe Port #8, NEC USB 3.0 Host Controller
+ device ref lpc on # LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x60"
register "ec_cmd_port" = "0x64"
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb
index 729db13..653c5ab 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb
@@ -7,8 +7,8 @@
device domain 0 on
subsystemid 0x103c 0x179b inherit
- device pci 01.0 on end # PCIe Bridge for discrete graphics
- device pci 02.0 on end # Internal graphics
+ device ref peg10 on end # PCIe Bridge for discrete graphics
+ device ref igd on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# mailbox at 0x200/0x201 and PM1 at 0x220
@@ -24,17 +24,17 @@
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
- device pci 14.0 on end # USB 3.0 Controller
- device pci 16.3 on end # Management Engine KT
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #2, ExpressCard
- device pci 1c.2 on end # PCIe Port #3, SD/MMC
- device pci 1c.3 on end # PCIe Port #4, WLAN
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 off end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1f.0 on # LPC bridge
+ device ref xhci on end # USB 3.0 Controller
+ device ref me_kt on end # Management Engine KT
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 on end # PCIe Port #2, ExpressCard
+ device ref pcie_rp3 on end # PCIe Port #3, SD/MMC
+ device ref pcie_rp4 on end # PCIe Port #4, WLAN
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref lpc on # LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x62"
register "ec_cmd_port" = "0x66"
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb
index 02ee795..548a70f 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb
@@ -5,11 +5,11 @@
device domain 0 on
subsystemid 0x103c 0x176c inherit
- device pci 01.0 on # PCIe Bridge for discrete graphics
+ device ref peg10 on # PCIe Bridge for discrete graphics
device pci 00.0 on end # GPU
device pci 00.1 on end # HDMI Audio on GPU
end
- device pci 02.0 off end # Internal graphics
+ device ref igd off end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "docking_supported" = "0"
@@ -25,16 +25,16 @@
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
- device pci 14.0 on end # USB 3.0 Controller
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #2
- device pci 1c.2 on end # Media Card and FireWire host controller
- device pci 1c.3 on end # Wireless LAN Adapter
- device pci 1c.4 on end # SATA Controller 2 for dock
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 off end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1f.0 on # LPC bridge
+ device ref xhci on end # USB 3.0 Controller
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 on end # PCIe Port #2
+ device ref pcie_rp3 on end # Media Card and FireWire host controller
+ device ref pcie_rp4 on end # Wireless LAN Adapter
+ device ref pcie_rp5 on end # SATA Controller 2 for dock
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref lpc on # LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x62"
register "ec_cmd_port" = "0x66"
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb
index 1eb9c4c..2f38cb6 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb
@@ -7,8 +7,8 @@
device domain 0 on
subsystemid 0x103c 0x18df inherit
- device pci 01.0 off end # PCIe Bridge for discrete graphics
- device pci 02.0 on end # Internal graphics
+ device ref peg10 off end # PCIe Bridge for discrete graphics
+ device ref igd on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# mailbox at 0x200/0x201 and PM1 at 0x220
@@ -23,16 +23,16 @@
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
- device pci 14.0 on end # USB 3.0 Controller
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 on end # PCIe Port #3 SDHCI
- device pci 1c.3 on end # PCIe Port #4 WLAN
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 off end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1f.0 on # LPC bridge
+ device ref xhci on end # USB 3.0 Controller
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 off end # PCIe Port #2
+ device ref pcie_rp3 on end # PCIe Port #3 SDHCI
+ device ref pcie_rp4 on end # PCIe Port #4 WLAN
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref lpc on # LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x62"
register "ec_cmd_port" = "0x66"
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb
index 3289588..16551d2 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb
@@ -6,8 +6,8 @@
device domain 0 on
subsystemid 0x103c 0x1621 inherit
- device pci 01.0 off end # PEG
- device pci 02.0 on end # iGPU
+ device ref peg10 off end # PEG
+ device ref igd on end # iGPU
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "gen1_dec" = "0x007c0201"
@@ -20,21 +20,21 @@
# FIXME: ports 3, 5 are untested
register "sata_port_map" = "0x3b"
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 on # PCIe Port #2, ExpressCard
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 on # PCIe Port #2, ExpressCard
smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort"
"ExpressCard Slot" "SlotDataBusWidth1X"
end
- device pci 1c.2 on end # PCIe Port #3, SD/MMC and FireWire
- device pci 1c.3 on # PCIe Port #4, WLAN
+ device ref pcie_rp3 on end # PCIe Port #3, SD/MMC and FireWire
+ device ref pcie_rp4 on # PCIe Port #4, WLAN
smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
"SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
end
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 on end # PCIe Port #7, WWAN
- device pci 1c.7 off end # PCIe Port #8
- device pci 1f.0 on
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 on end # PCIe Port #7, WWAN
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref lpc on
chip ec/hp/kbc1126
register "ec_data_port" = "0x60"
register "ec_cmd_port" = "0x64"
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb
index 68b6daa..6701733 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb
@@ -7,8 +7,8 @@
device domain 0 on
subsystemid 0x103c 0x18f8 inherit
- device pci 01.0 off end # PCIe Bridge for discrete graphics
- device pci 02.0 on end # Internal graphics
+ device ref peg10 off end # PCIe Bridge for discrete graphics
+ device ref igd on end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# mailbox at 0x200/0x201 and PM1 at 0x220
@@ -23,16 +23,16 @@
register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
- device pci 14.0 on end # USB 3.0 Controller
- device pci 1c.0 on end # PCIe Port #1
- device pci 1c.1 off end # PCIe Port #2
- device pci 1c.2 on end # PCIe Port #3
- device pci 1c.3 on end # PCIe Port #4
- device pci 1c.4 off end # PCIe Port #5
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 off end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1f.0 on # LPC bridge
+ device ref xhci on end # USB 3.0 Controller
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 off end # PCIe Port #2
+ device ref pcie_rp3 on end # PCIe Port #3
+ device ref pcie_rp4 on end # PCIe Port #4
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 off end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref lpc on # LPC bridge
chip ec/hp/kbc1126
register "ec_data_port" = "0x62"
register "ec_cmd_port" = "0x66"
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Change subject: mb/hp/snb_ivb_laptops: Convert remaining PCI numbers into references
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Change subject: mb/hp/snb_ivb_laptops: Remove superfluous comments about PCI devices
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Patch Set 3:
(1 comment)
Patchset:
PS3:
> Good riddance, one of those was outright inaccurate (2170p mei1 marked as me_kt).
Thank you for reviewing 😊
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Change subject: mb/hp/snb_ivb_laptops: Remove superfluous comments about PCI devices
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PS3:
Good riddance, one of those was outright inaccurate (2170p mei1 marked as me_kt).
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Change subject: mb/hp/snb_ivb_laptops: Convert remaining PCI numbers into references
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PS3:
Looks good to me.
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Change subject: lib/lzmadecode: Allow for 8 byte reads on 64bit
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Patch Set 3:
(1 comment)
File src/lib/lzmadecode.h:
https://review.coreboot.org/c/coreboot/+/70175/comment/1d29d782_1cff66ba :
PS3, Line 28: typedef unsigned long int SizeT;
also shouldn't this rather be size_t?
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