Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80145?usp=email )
Change subject: mb/google/brya: Create xol variant
......................................................................
mb/google/brya: Create xol variant
Create the xol variant of the brya0 reference board by copying the
template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:319506033
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_XOL
Change-Id: Id60c50b70c9ab53d62ad48cfc15462f2410f9f02
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80145
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/xol/include/variant/ec.h
A src/mainboard/google/brya/variants/xol/include/variant/gpio.h
A src/mainboard/google/brya/variants/xol/memory/Makefile.inc
A src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/xol/overridetree.cb
8 files changed, 48 insertions(+), 0 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index e2357f4..7b0d587 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -453,6 +453,10 @@
select DRIVERS_INTEL_MIPI_CAMERA
select INTEL_GMA_HAVE_VBT
+config BOARD_GOOGLE_XOL
+ select BOARD_GOOGLE_BASEBOARD_BRYA
+ select SOC_INTEL_RAPTORLAKE
+
config BOARD_GOOGLE_YAVIKS
select BOARD_GOOGLE_BASEBOARD_NISSA
select CHROMEOS_WIFI_SAR if CHROMEOS
@@ -661,6 +665,7 @@
default "Nokris" if BOARD_GOOGLE_NOKRIS
default "Dochi" if BOARD_GOOGLE_DOCHI
default "Anraggar" if BOARD_GOOGLE_ANRAGGAR
+ default "Xol" if BOARD_GOOGLE_XOL
config VARIANT_DIR
default "brya0" if BOARD_GOOGLE_BRYA0
@@ -714,6 +719,7 @@
default "nokris" if BOARD_GOOGLE_NOKRIS
default "dochi" if BOARD_GOOGLE_DOCHI
default "anraggar" if BOARD_GOOGLE_ANRAGGAR
+ default "xol" if BOARD_GOOGLE_XOL
config VBOOT
select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index efbdd1a..9c3baf0 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -152,3 +152,6 @@
config BOARD_GOOGLE_ANRAGGAR
bool "-> Anraggar"
+
+config BOARD_GOOGLE_XOL
+ bool "-> Xol"
diff --git a/src/mainboard/google/brya/variants/xol/include/variant/ec.h b/src/mainboard/google/brya/variants/xol/include/variant/ec.h
new file mode 100644
index 0000000..7a2a6ff
--- /dev/null
+++ b/src/mainboard/google/brya/variants/xol/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/xol/include/variant/gpio.h b/src/mainboard/google/brya/variants/xol/include/variant/gpio.h
new file mode 100644
index 0000000..c4fe342
--- /dev/null
+++ b/src/mainboard/google/brya/variants/xol/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/brya/variants/xol/memory/Makefile.inc b/src/mainboard/google/brya/variants/xol/memory/Makefile.inc
new file mode 100644
index 0000000..eace2e4
--- /dev/null
+++ b/src/mainboard/google/brya/variants/xol/memory/Makefile.inc
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder
diff --git a/src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/src/mainboard/google/brya/variants/xol/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt
new file mode 100644
index 0000000..9621137
--- /dev/null
+++ b/src/mainboard/google/brya/variants/xol/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb
new file mode 100644
index 0000000..4f2c04a
--- /dev/null
+++ b/src/mainboard/google/brya/variants/xol/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/alderlake
+
+ device domain 0 on
+ end
+
+end
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Id60c50b70c9ab53d62ad48cfc15462f2410f9f02
Gerrit-Change-Number: 80145
Gerrit-PatchSet: 2
Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: YH Lin <yueherngl(a)google.com>
Gerrit-MessageType: merged
Attention is currently required from: Cliff Huang, Lance Zhao, Subrata Banik, Tim Wawrzynczak.
Hello Cliff Huang, Lance Zhao, Subrata Banik, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80170?usp=email
to look at the new patch set (#3).
Change subject: Add MTCL function to ACPI SSDT tables
......................................................................
Add MTCL function to ACPI SSDT tables
The MTCL function provides a country list to the Linux kernel via an
ACPI function in SSDT tables for MediaTek chipsets that are capable of
operating on the 6GHz band. The country list is used to selectively
disable 6GHz and 5.9GHz operation based on the country the device is
operating in.
The function needs to read a binary file and send it as a package via
the MTCL method in SSDT for PCIe WiFi chips for MediaTek chipsets.
BUG=b:295544553
TEST=Add Kconfig entry USE_MTCL for pujjo
TEST=Add wifi_mtcl_defaults.hex blob to cbfs
TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage`
TEST=Verify that MTCL defined in the file is present:
TEST=`acpidump -b`
TEST=`iasl ssdt.dat`
TEST=`less ssdt.dsl`
TEST=Search for MTCL
Signed-off-by: David Ruth <druth(a)chromium.org>
Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350
---
M src/acpi/acpigen.c
M src/drivers/wifi/generic/Kconfig
M src/drivers/wifi/generic/Makefile.inc
M src/drivers/wifi/generic/acpi.c
M src/include/acpi/acpigen.h
M src/include/device/pci_ids.h
A src/include/mtcl.h
M src/vendorcode/google/chromeos/Makefile.inc
A src/vendorcode/google/chromeos/mtcl.c
9 files changed, 219 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/3
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350
Gerrit-Change-Number: 80170
Gerrit-PatchSet: 3
Gerrit-Owner: David Ruth <druth(a)chromium.org>
Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com>
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Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>
Gerrit-MessageType: newpatchset
David Ruth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80170?usp=email )
Change subject: Add MTCL function to ACPI SSDT tables.
......................................................................
Add MTCL function to ACPI SSDT tables.
The MTCL function provides a country list to the Linux kernel via an
ACPI function in SSDT tables for MediaTek chipsets that are capable of
operating on the 6GHz band. The country list is used to selectively
disable 6GHz and 5.9GHz operation based on the country the device is
operating in.
The function needs to read a binary file and send it as a package via
the MTCL method in SSDT for PCIe WiFi chips for MediaTek chipsets.
BUG=b:295544553
TEST=Add Kconfig entry USE_MTCL for pujjo
TEST=Add wifi_mtcl_defaults.hex blob to cbfs
TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage`
TEST=Verify that MTCL defined in the file is present:
TEST=`acpidump -b`
TEST=`iasl ssdt.dat`
TEST=`less ssdt.dsl`
TEST=Search for MTCL
Signed-off-by: David Ruth <druth(a)chromium.org>
Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350
---
M src/acpi/acpigen.c
M src/drivers/wifi/generic/Kconfig
M src/drivers/wifi/generic/Makefile.inc
M src/drivers/wifi/generic/acpi.c
M src/include/acpi/acpigen.h
M src/include/device/pci_ids.h
A src/include/mtcl.h
M src/vendorcode/google/chromeos/Makefile.inc
A src/vendorcode/google/chromeos/mtcl.c
9 files changed, 219 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/1
diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c
index 64ec734..372660a 100644
--- a/src/acpi/acpigen.c
+++ b/src/acpi/acpigen.c
@@ -1925,6 +1925,44 @@
acpigen_pop_len(); /* Method _DSM */
}
+/*
+ * Generate ACPI AML code for MTCL method.
+ * This function takes as input an array of bytes that correspond to the
+ * value map to be passed as a package, as well as the count of bytes
+ * to be written.
+ *
+ * AML code generate would look like:
+ * Method(MTCL, 0, Serialized)
+ * {
+ * Name (LIST, Package()
+ * {
+ * // data table
+ * })
+ * Return (LIST)
+ * }
+ */
+void acpigen_write_mtcl(uint8_t *bytes, size_t count)
+{
+ /* Method (MTCL, 0, Serialized) */
+ acpigen_write_method_serialized("MTCL", 0x0);
+
+ /* Name (LIST */
+ acpigen_write_name("LIST");
+
+ /* Package () */
+ acpigen_write_package(count);
+
+ /* Write the provided bytes. */
+ for (int i = 0; i < count; ++i)
+ acpigen_write_byte(bytes[i]);
+
+ acpigen_write_package_end(); /* Package */
+
+ /* Return MTCL */
+ acpigen_write_return_namestr("LIST");
+ acpigen_write_method_end(); /* Method MTCL */
+}
+
void acpigen_write_CPPC_package(const struct cppc_config *config)
{
u32 i;
diff --git a/src/drivers/wifi/generic/Kconfig b/src/drivers/wifi/generic/Kconfig
index 1d0e19f..18d9d84 100644
--- a/src/drivers/wifi/generic/Kconfig
+++ b/src/drivers/wifi/generic/Kconfig
@@ -14,6 +14,15 @@
When enabled, add identifiers in ACPI and SMBIOS tables to
make OS drivers work with certain Intel PCI-e WiFi chipsets.
+config DRIVERS_MTK_WIFI
+ bool "Support MediaTek PCI-e WiFi adapters"
+ depends on PCI
+ default y if PCIEXP_PLUGIN_SUPPORT
+ select DRIVERS_WIFI_GENERIC
+ help
+ When enabled, add identifiers in ACPI tables to make OS
+ drivers work with certain MediaTek PCI-e WiFi chipsets.
+
if DRIVERS_WIFI_GENERIC
config USE_SAR
@@ -50,3 +59,21 @@
There can be up to 3 optional SAR table sets.
endif # DRIVERS_WIFI_GENERIC
+
+if DRIVERS_MTK_WIFI
+
+config USE_MTCL
+ bool
+ default n
+ help
+ When enabled, adds the MTCL function for MediaTek
+ WiFi chipsets. This function supplies country list information
+ used to enable or disable operation on 5.9GHz and 6GHz
+ bands.
+
+config WIFI_MTCL_CBFS_FILEPATH
+ string "The cbfs file which has WIFI MTCL defaults"
+ depends on USE_MTCL
+ default ""
+
+endif # DRIVERS_MTK_WIFI
diff --git a/src/drivers/wifi/generic/Makefile.inc b/src/drivers/wifi/generic/Makefile.inc
index 337b8fe..82c2cd9 100644
--- a/src/drivers/wifi/generic/Makefile.inc
+++ b/src/drivers/wifi/generic/Makefile.inc
@@ -19,4 +19,14 @@
endif
+CONFIG_WIFI_MTCL_CBFS_FILEPATH := $(call strip_quotes,$(CONFIG_WIFI_MTCL_CBFS_FILEPATH))
+
+ifneq ($(CONFIG_WIFI_MTCL_CBFS_FILEPATH),)
+
+cbfs-files-$(CONFIG_USE_MTCL) += wifi_mtcl_defaults.hex
+wifi_mtcl_defaults.hex-file := $(CONFIG_WIFI_MTCL_CBFS_FILEPATH)
+wifi_mtcl_defaults.hex-type := raw
+
+endif
+
endif
diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c
index f37a084..3747aa8 100644
--- a/src/drivers/wifi/generic/acpi.c
+++ b/src/drivers/wifi/generic/acpi.c
@@ -5,6 +5,7 @@
#include <acpi/acpigen_pci.h>
#include <console/console.h>
#include <device/pci_ids.h>
+#include <mtcl.h>
#include <sar.h>
#include <stdlib.h>
#include <wrdd.h>
@@ -38,6 +39,11 @@
return -1;
}
+__weak int get_wifi_mtcl(uint8_t *mtcl_package)
+{
+ return -1;
+}
+
/*
* Function 1: Allow PC OEMs to set ETSI 5.8GHz SRD in Passive/Disabled ESTI SRD
* Channels: 149, 153, 157, 161, 165
@@ -576,7 +582,20 @@
acpigen_write_dsm_uuid_arr(dsm_ids, dsm_count);
- acpigen_pop_len(); /* Scope */
+ /*
+ * Fill MediaTek MTCL related ACPI structure iff the device type is PCI,
+ * the device has the MediaTek vendor ID, and the MTCL feature is
+ * configured.
+ */
+ if (dev->path.type == DEVICE_PATH_PCI &&
+ dev->vendor == PCI_VID_MEDIATEK && CONFIG(USE_MTCL)) {
+ uint8_t mtcl_package[sizeof(struct wifi_mtcl)];
+ size_t mtcl_size = get_wifi_mtcl(mtcl_package);
+ if (mtcl_size > 0)
+ acpigen_write_mtcl(mtcl_package, mtcl_size);
+ }
+
+ acpigen_write_scope_end(); /* Scope */
printk(BIOS_INFO, "%s: %s %s\n", scope, dev->chip_ops ? dev->chip_ops->name : "",
dev_path(dev));
diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h
index 7a5be51..0875fde 100644
--- a/src/include/acpi/acpigen.h
+++ b/src/include/acpi/acpigen.h
@@ -550,6 +550,13 @@
void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count);
/*
+ * Generate ACPI AML code for MTCL method.
+ * This function takes as input an array of bytes that correspond to the
+ * value map to be passed as a package, as well as the count of bytes
+ * to be written.
+ */
+void acpigen_write_mtcl(uint8_t *bytes, size_t count);
+/*
* Generate ACPI AML code for _CPC (Continuous Performance Control).
* Execute the package function once to create a global table, then
* execute the method function within each processor object to
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index ae74901..7e3910a 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4785,6 +4785,8 @@
#define PCI_DID_SIS_SIS968_PCIE 0x000a /* D6F0,D7F0 */
#define PCI_DID_SIS_SIS968_HD_AUDIO 0x7502 /* DfF0 */
+#define PCI_VID_MEDIATEK 0x14c3
+
/* OLD USAGE FOR COREBOOT */
#define PCI_VID_ACER 0x10b9
#define PCI_DID_ACER_M1535D 0x1533
diff --git a/src/include/mtcl.h b/src/include/mtcl.h
new file mode 100644
index 0000000..17db32a
--- /dev/null
+++ b/src/include/mtcl.h
@@ -0,0 +1,23 @@
+#ifndef _MTCL_H_
+#define _MTCL_H_
+
+#include <stdint.h>
+
+#define MAX_VERSION 2
+#define MAX_SUPPORT_STATE 2
+#define COUNTRY_LIST_SIZE 6
+#define NAME_SIZE 4
+#define MTCL_NAME "MTCL"
+
+struct wifi_mtcl {
+ uint8_t name[NAME_SIZE];
+ uint8_t revision;
+ uint8_t support_6ghz;
+ uint8_t country_list_6ghz[COUNTRY_LIST_SIZE];
+ uint8_t support_5p9ghz;
+ uint8_t country_list_5p9ghz[COUNTRY_LIST_SIZE];
+} __packed;
+
+int get_wifi_mtcl(uint8_t *mtcl);
+
+#endif /* _MTCL_H_ */
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index dce4d9c..b689829 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -8,6 +8,7 @@
ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c
ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c
ramstage-$(CONFIG_USE_SAR) += sar.c
+ramstage-$(CONFIG_USE_MTCL) += mtcl.c
ramstage-$(CONFIG_TPM_GOOGLE) += cr50_enable_update.c
ramstage-$(CONFIG_TPM_GOOGLE) += tpm_factory_config.c
diff --git a/src/vendorcode/google/chromeos/mtcl.c b/src/vendorcode/google/chromeos/mtcl.c
new file mode 100644
index 0000000..31a3c08
--- /dev/null
+++ b/src/vendorcode/google/chromeos/mtcl.c
@@ -0,0 +1,91 @@
+#include <cbfs.h>
+#include <mtcl.h>
+#include <string.h>
+
+#define WIFI_MTCL_CBFS_DEFAULT_FILENAME "wifi_mtcl.hex"
+
+/*
+ * Retrieve WiFi MTCL data from CBFS and decode it.
+ * Data is expected in the format:
+ * [Revision,
+ * 6GHz Support,
+ * 6GHz Country List,
+ * 5.9GHz Support,
+ * 5.9GHz Country List]
+ *
+ * The revision is expected to be "2".
+ *
+ * 6GHz support is a byte with the following states:
+ * - 0 - 6GHz operation disabled
+ * - 1 - 6GHz operation dictated by the country list and Operating System
+ * - 2 - 6GHz operation dictated by the Operating System
+ *
+ * 6GHz Country List is a set of 6 bytes that represent a bitmask of countries
+ * in which 6GHz operation is enabled.
+ *
+ * 5.9GHz Support is a byte with the following known states:
+ * - 0 - 5.9GHz operation disabled
+ * - 1 - 5.9GHz operation dictated by the country list and Operating System
+ * - 2 - 5.9GHz operation dictated by the Operating System
+ *
+ * 5.9GHz Country List is a set of 6 bytes that represent a bitmask of countries
+ * in which 5.9GHz operation is enabled
+ *
+ * Validation:
+ * - Verify that there are MTCL_SIZE bytes.
+ * - Verify that the name is MTCL_NAME.
+ * - Verify that the version is less than or equal to MAX_MTCL_VERSION.
+ * - Verify that the support bytes are less than or equal to the
+ * MAX_SUPPORT_STATE.
+ *
+ * Returns the number of bytes read.
+ */
+int get_wifi_mtcl(uint8_t *mtcl_package)
+{
+ size_t mtcl_bin_len;
+ uint8_t *mtcl_bin;
+ struct wifi_mtcl *mtcl;
+ int ret = -1;
+
+ mtcl_bin = cbfs_map(WIFI_MTCL_CBFS_DEFAULT_FILENAME, &mtcl_bin_len);
+ if (!mtcl_bin) {
+ printk(BIOS_ERR, "Failed to get the %s file size!\n",
+ WIFI_MTCL_CBFS_DEFAULT_FILENAME);
+ return ret;
+ }
+
+ if (mtcl_bin_len != sizeof(struct wifi_mtcl)) {
+ printk(BIOS_ERR, "Size of file read was: %lu, expected: %lu\n",
+ mtcl_bin_len, sizeof(struct wifi_mtcl));
+ goto error;
+ }
+
+ mtcl_package = memcpy(mtcl_package, mtcl_bin, sizeof(struct wifi_mtcl));
+ mtcl = (struct wifi_mtcl *)mtcl_package;
+
+ if (strncmp(((char *)mtcl->name), MTCL_NAME, NAME_SIZE)) {
+ printk(BIOS_ERR, "MTCL string not present but expected\n");
+ goto error;
+ }
+
+ if (mtcl->revision > MAX_VERSION) {
+ printk(BIOS_ERR, "MTCL version too high\n");
+ goto error;
+ }
+
+ if (mtcl->support_6ghz > MAX_SUPPORT_STATE) {
+ printk(BIOS_ERR, "MTCL 6GHz support state too high\n");
+ goto error;
+ }
+
+ if (mtcl->support_5p9ghz > MAX_SUPPORT_STATE) {
+ printk(BIOS_ERR, "MTCL 5.9GHz support state too high\n");
+ goto error;
+ }
+
+ ret = mtcl_bin_len;
+
+error:
+ cbfs_unmap(mtcl_bin);
+ return ret;
+}
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Change subject: ec/dell/mec5035: Hook up radio enables to option API
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> not 100% sure how that api behaves when there's a cmos option table that doesn't have those options, […]
Skimming the `drivers/pc80/rtc` code, it looks like `get_uint_option` returns the default value if `cmos_get_uint_option` can't find an entry in the option table.
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Change subject: ec/dell/mec5035: Hook up radio enables to option API
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Patchset:
PS4:
not 100% sure how that api behaves when there's a cmos option table that doesn't have those options, so i'll only +1 it, but apart from that one thing i'm not sure about, it looks good to me
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Change subject: ec/dell/mec5035: Add command to control radio state
......................................................................
Patch Set 10: Code-Review+2
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Change subject: mb/dell: Add Latitude E6430 (Ivy Bridge)
......................................................................
Patch Set 9:
(3 comments)
This change is ready for review.
Patchset:
PS6:
> A couple of nits, Feel free to fix them in a follow-on patch if you're going to fix them. […]
Ack. I think a lot of that is just the result of autoport, which often just dumps raw register values and doesn't attempt to decode them into macros. I'll probably fix some of them in a follow up patch that changes them across several boards
File src/mainboard/dell/e6430/cmos.layout:
https://review.coreboot.org/c/coreboot/+/77444/comment/10af68a1_83e4adc0 :
PS6, Line 28: 5
> nit: 414? Is there a reason to skip a bit here?
Fixed. That was just leftover from the T430 cmos.layout which I based mine off of, which uses bit 414 for a touchpad option, and I had removed that option in my layout.
File src/mainboard/dell/e6430/early_init.c:
https://review.coreboot.org/c/coreboot/+/77444/comment/a43122ac_016e6230 :
PS6, Line 29: PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f
> Nit: These could be macros to better show what's being initialized.
Done
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Change subject: mb/google/brox: Enable WLAN on root port 5
......................................................................
Patch Set 16:
(1 comment)
File src/mainboard/google/brox/variants/brox/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/79888/comment/ebc9c3ea_90fe1963 :
PS12, Line 185: PCIe 5 using clk 1
> Quite duplicated, isn't it? Please don't document the devicetree in comments.
Done
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Hello Eric Lai, Nick Vaccaro, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79888?usp=email
to look at the new patch set (#16).
The following approvals got outdated and were removed:
Code-Review+2 by Eric Lai, Code-Review+2 by Nick Vaccaro, Verified+1 by build bot (Jenkins)
Change subject: mb/google/brox: Enable WLAN on root port 5
......................................................................
mb/google/brox: Enable WLAN on root port 5
BUG=b:311450057,b:300690448
BRANCH=None
TEST=to be tested on device with lspci
Change-Id: I361bef13ebd073b6fccb729a1960d3832cf2681a
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/variants/brox/overridetree.cb
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/79888/16
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Change subject: vc/amd/opensil/genoa_poc: move configure_mpio call to setup_opensil
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> still needs to be tested on harwdare
*hardware
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