coreboot-gerrit January 2024

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[XL] Change in coreboot[main]: mb/ocp: Drop tiogapass
by Johnny Lin (Code Review) 23 Jan '24

23 Jan '24

Attention is currently required from: Marc Jones, Morgan Jang, Patrick Rudolph, Shuo Liu. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80171?usp=email ) Change subject: mb/ocp: Drop tiogapass ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Well I guess no one is planning to work on TiogaPass anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/80171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I838b9ea3955d31ea393494c2e726845fe234ef3a Gerrit-Change-Number: 80171 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Tue, 23 Jan 2024 08:20:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Find VTD devices by PCI DEV ID
by Arthur Heymans (Code Review) 23 Jan '24

23 Jan '24

Attention is currently required from: Christian Walter, Johnny Lin, Patrick Rudolph, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80092?usp=email ) Change subject: soc/intel/xeon_sp: Find VTD devices by PCI DEV ID ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/soc/intel/xeon_sp/memmap.c: https://review.coreboot.org/c/coreboot/+/80092/comment/2c794e6b_1ab872a1 : PS1, Line 71: PCI_VID_INTEL, MMAP_VTD_STACK_CFG_REG_DEVID > Isn't the MMAP_VTD_CFG_REG_DEVID case covered by VTD_DEV(0) which the other stacks are compared against? I guess it probably is. Aynway, the TXT error codes would be sufficiently clear. -- To view, visit https://review.coreboot.org/c/coreboot/+/80092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa96 Gerrit-Change-Number: 80092 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 23 Jan 2024 08:02:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Drop 1st Gen Xeon-SP
by Patrick Rudolph (Code Review) 23 Jan '24

23 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jérémy Compostella, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80172?usp=email ) Change subject: soc/intel/xeon_sp: Drop 1st Gen Xeon-SP ...................................................................... soc/intel/xeon_sp: Drop 1st Gen Xeon-SP The platform code depends on unreleased binary files and uses incomplete public header files. In order to reduce maintainance burden for the Xeon-SP platforms drop this old code. Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I12b092f00386cb71fac02d8d0b10375d3241abb3 --- M src/arch/x86/smbios.c M src/soc/intel/xeon_sp/Makefile.inc D src/soc/intel/xeon_sp/skx/Kconfig D src/soc/intel/xeon_sp/skx/Makefile.inc D src/soc/intel/xeon_sp/skx/chip.c D src/soc/intel/xeon_sp/skx/chip.h D src/soc/intel/xeon_sp/skx/cpu.c D src/soc/intel/xeon_sp/skx/hob_display.c D src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h D src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h D src/soc/intel/xeon_sp/skx/include/soc/soc_util.h D src/soc/intel/xeon_sp/skx/romstage.c D src/soc/intel/xeon_sp/skx/soc_acpi.c D src/soc/intel/xeon_sp/skx/soc_smihandler_util.c D src/soc/intel/xeon_sp/skx/soc_util.c D src/soc/intel/xeon_sp/skx/upd_display.c M src/soc/intel/xeon_sp/uncore_acpi.c 17 files changed, 2 insertions(+), 1,413 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/80172/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index a2038b6..085fe6a 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -56,8 +56,6 @@ return PROCESSOR_UPGRADE_SOCKET_LGA1700; if (CONFIG(SOC_INTEL_METEORLAKE)) return PROCESSOR_UPGRADE_OTHER; - if (CONFIG(SOC_INTEL_SKYLAKE_SP)) - return PROCESSOR_UPGRADE_SOCKET_LGA3647_1; if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) return PROCESSOR_UPGRADE_SOCKET_LGA4189; if (CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP)) diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index a732c78..4215d0d 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -2,7 +2,6 @@ ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y) -subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx lbg subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg subdirs-$(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP) += spr ebg diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig deleted file mode 100644 index 5d84387..0000000 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ /dev/null @@ -1,70 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -config SOC_INTEL_SKYLAKE_SP - bool - select XEON_SP_COMMON_BASE - select PLATFORM_USES_FSP2_0 - select NO_FSP_TEMP_RAM_EXIT - help - Intel Skylake-SP support - -if SOC_INTEL_SKYLAKE_SP - -config MAINBOARD_USES_FSP2_0 - bool - default y - -config FSP_HEADER_PATH - string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 - default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" - -config MAX_SOCKET - int - default 2 - -# For 2S config, the number of cpus could be as high as -# 2 threads * 20 cores * 2 sockets -config MAX_CPUS - int - default 80 - -config PCR_BASE_ADDRESS - hex - default 0xfd000000 - help - This option allows you to select MMIO Base Address of sideband bus. - -config DCACHE_RAM_BASE - hex - default 0xfe800000 - -config DCACHE_RAM_SIZE - hex - default 0x200000 - -config DCACHE_BSP_STACK_SIZE - hex - default 0x10000 - -config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff0fdc0 - -config CPU_MICROCODE_CBFS_LEN - hex - default 0x7C00 - -config IED_REGION_SIZE - hex - default 0x400000 - -config IFD_CHIPSET - string - default "lbg" - -config XEON_SP_HAVE_IIO_IOAPIC - bool - default y - -endif diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc deleted file mode 100644 index 0f75eec..0000000 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ /dev/null @@ -1,30 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -ifeq ($(CONFIG_SOC_INTEL_SKYLAKE_SP),y) - -subdirs-y += ../../../../cpu/intel/microcode -subdirs-y += ../../../../cpu/intel/turbo - -postcar-y += soc_util.c - -romstage-y += soc_util.c -romstage-y += romstage.c -romstage-y += soc_util.c -romstage-y += hob_display.c -romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c - -ramstage-y += soc_acpi.c -ramstage-y += chip.c -ramstage-y += soc_util.c -ramstage-y += cpu.c -ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c -ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -ramstage-y += hob_display.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += soc_smihandler_util.c - -CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx - -cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-04 - -endif ## CONFIG_SOC_INTEL_SKYLAKE_SP diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c deleted file mode 100644 index b468842..0000000 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <cbfs.h> -#include <console/console.h> -#include <device/pci.h> -#include <gpio.h> -#include <intelblocks/acpi.h> -#include <soc/acpi.h> -#include <soc/chip_common.h> -#include <soc/pch.h> -#include <soc/soc_pch.h> -#include <soc/ramstage.h> -#include <soc/soc_util.h> -#include <soc/util.h> - -#if CONFIG(HAVE_ACPI_TABLES) -const char *soc_acpi_name(const struct device *dev) -{ - if (dev->path.type == DEVICE_PATH_DOMAIN) - return "PC00"; - return NULL; -} -#endif - -static struct device_operations pci_domain_ops = { - .read_resources = iio_pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = iio_pci_domain_scan_bus, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = &northbridge_write_acpi_tables, - .acpi_name = soc_acpi_name -#endif -}; - -static struct device_operations cpu_bus_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .init = mp_cpu_bus_init, -#if CONFIG(HAVE_ACPI_TABLES) - /* defined in src/soc/intel/common/block/acpi/acpi.c */ - .acpi_fill_ssdt = generate_cpu_entries, -#endif -}; - -static void soc_enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - attach_iio_stacks(dev); - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_GPIO) { - block_gpio_enable(dev); - } -} - -static void soc_init(void *data) -{ - printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); - fsp_silicon_init(); - override_hpet_ioapic_bdf(); - pch_lock_dmictl(); -} - -static void soc_final(void *data) -{ - // Temp Fix - should be done by FSP, in 2S bios completion - // is not carried out on socket 2 - set_bios_init_completion(); -} - -void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) -{ - const struct microcode *microcode_file; - size_t microcode_len; - - microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len); - - if ((microcode_file) && (microcode_len != 0)) { - /* Update CPU Microcode patch base address/size */ - silupd->FspsConfig.PcdCpuMicrocodePatchBase = - (uint32_t)microcode_file; - silupd->FspsConfig.PcdCpuMicrocodePatchSize = - (uint32_t)microcode_len; - } - - mainboard_silicon_init_params(silupd); -} - -struct chip_operations soc_intel_xeon_sp_skx_ops = { - CHIP_NAME("Intel Skylake-SP") - .enable_dev = soc_enable_dev, - .init = soc_init, - .final = soc_final -}; - -struct pci_operations soc_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h deleted file mode 100644 index 0c05211..0000000 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SOC_CHIP_H_ -#define _SOC_CHIP_H_ - -#include <gpio.h> -#include <intelblocks/cfg.h> -#include <soc/acpi.h> -#include <soc/irq.h> -#include <stdint.h> - -struct soc_intel_xeon_sp_skx_config { - /* Common struct containing soc config data required by common code */ - struct soc_intel_common_config common_soc_config; - - /** - * Interrupt Routing configuration - * If bit7 is 1, the interrupt is disabled. - */ - uint8_t pirqa_routing; - uint8_t pirqb_routing; - uint8_t pirqc_routing; - uint8_t pirqd_routing; - uint8_t pirqe_routing; - uint8_t pirqf_routing; - uint8_t pirqg_routing; - uint8_t pirqh_routing; - - /** - * Device Interrupt Routing configuration - * Interrupt Pin x Route. - * 0h = PIRQA# - * 1h = PIRQB# - * 2h = PIRQC# - * 3h = PIRQD# - * 4h = PIRQE# - * 5h = PIRQF# - * 6h = PIRQG# - * 7h = PIRQH# - */ - - uint16_t ir00_routing; - uint16_t ir01_routing; - uint16_t ir02_routing; - uint16_t ir03_routing; - uint16_t ir04_routing; - - /** - * Device Interrupt Polarity Control - * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC - * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC - * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC - * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC - */ - uint32_t ipc0; - uint32_t ipc1; - uint32_t ipc2; - uint32_t ipc3; - - uint64_t turbo_ratio_limit; - uint64_t turbo_ratio_limit_cores; - - uint32_t pstate_req_ratio; - - uint32_t vtd_support; - uint32_t coherency_support; - uint32_t ats_support; - - /* Generic IO decode ranges */ - uint32_t gen1_dec; - uint32_t gen2_dec; - uint32_t gen3_dec; - uint32_t gen4_dec; - - /* TCC activation offset */ - uint32_t tcc_offset; - - enum acpi_cstate_mode cstate_states; -}; - -typedef struct soc_intel_xeon_sp_skx_config config_t; - -#endif diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c deleted file mode 100644 index 009527c..0000000 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ /dev/null @@ -1,252 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <console/console.h> -#include <console/debug.h> -#include <intelblocks/cpulib.h> -#include <cpu/cpu.h> -#include <cpu/intel/cpu_ids.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/mp.h> -#include <cpu/intel/turbo.h> -#include <soc/msr.h> -#include <soc/soc_util.h> -#include <soc/smmrelocate.h> -#include <soc/util.h> -#include <assert.h> -#include "chip.h" -#include <cpu/intel/smm_reloc.h> -#include <cpu/intel/em64t101_save_state.h> -#include <types.h> - -static const config_t *chip_config = NULL; - -bool cpu_soc_is_in_untrusted_mode(void) -{ - /* IA_UNTRUSTED_MODE is not supported in Skylake */ - return false; -} - -void cpu_soc_bios_done(void) -{ - /* IA_UNTRUSTED_MODE is not supported in Skylake */ -} - -static void xeon_configure_mca(void) -{ - msr_t msr; - struct cpuid_result cpuid_regs; - - /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE - * and CPUID.(EAX=1):EDX[14]==1 MCA*/ - cpuid_regs = cpuid(1); - if ((cpuid_regs.edx & (1<<7 | 1<<14)) != (1<<7 | 1<<14)) - return; - - msr = rdmsr(IA32_MCG_CAP); - if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) { - /* Enable all error logging */ - msr.lo = msr.hi = 0xffffffff; - wrmsr(IA32_MCG_CTL, msr); - } - - /* TODO(adurbin): This should only be done on a cold boot. Also, some - of these banks are core vs package scope. For now every CPU clears - every bank. */ - mca_configure(); -} - -static void xeon_sp_core_init(struct device *cpu) -{ - msr_t msr; - - printk(BIOS_INFO, "%s dev: %s, cpu: %lu, apic_id: 0x%x, package_id: 0x%x\n", - __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id, - cpu->path.apic.package_id); - assert(chip_config); - - /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/ - msr.hi = 0; - msr.lo = (PKG_CSTATE_NO_LIMIT | CFG_LOCK_ENABLE); - wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - - /* Enable Energy Perf Bias Access, Dynamic switching and lock MSR */ - msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (ENERGY_PERF_BIAS_ACCESS_ENABLE | PWR_PERF_TUNING_DYN_SWITCHING_ENABLE - | PROCHOT_LOCK_ENABLE); - wrmsr(MSR_POWER_CTL, msr); - - /* Set P-State ratio */ - msr = rdmsr(MSR_IA32_PERF_CTRL); - msr.lo &= ~PSTATE_REQ_MASK; - msr.lo |= (chip_config->pstate_req_ratio << PSTATE_REQ_SHIFT); - wrmsr(MSR_IA32_PERF_CTRL, msr); - - /* - * Set HWP base feature, EPP reg enumeration, lock thermal and msr - * TODO: Set LOCK_MISC_PWR_MGMT_MSR, Unexpected Exception if you - * lock & issue wrmsr on every thread - * This is package level MSR. Need to check if it updates correctly on - * multi-socket platform. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (!(msr.lo & LOCK_MISC_PWR_MGMT_MSR)) { /* if already locked skip update */ - msr.lo = (HWP_ENUM_ENABLE | HWP_EPP_ENUM_ENABLE | LOCK_MISC_PWR_MGMT_MSR | - LOCK_THERM_INT); - wrmsr(MSR_MISC_PWR_MGMT, msr); - } - - /* TODO MSR_VR_MISC_CONFIG */ - - /* Set current limit lock */ - msr = rdmsr(MSR_VR_CURRENT_CONFIG); - msr.lo |= CURRENT_LIMIT_LOCK; - wrmsr(MSR_VR_CURRENT_CONFIG, msr); - - /* Set Turbo Ratio Limits */ - msr.lo = chip_config->turbo_ratio_limit & 0xffffffff; - msr.hi = (chip_config->turbo_ratio_limit >> 32) & 0xffffffff; - wrmsr(MSR_TURBO_RATIO_LIMIT, msr); - - /* Set Turbo Ratio Limit Cores */ - msr.lo = chip_config->turbo_ratio_limit_cores & 0xffffffff; - msr.hi = (chip_config->turbo_ratio_limit_cores >> 32) & 0xffffffff; - wrmsr(MSR_TURBO_RATIO_LIMIT_CORES, msr); - - /* set Turbo Activation ratio */ - msr.hi = 0; - msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); - msr.lo |= MAX_NON_TURBO_RATIO; - wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); - - /* Enable Fast Strings */ - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= FAST_STRINGS_ENABLE_BIT; - wrmsr(IA32_MISC_ENABLE, msr); - - /* Set energy policy */ - msr_t msr1 = rdmsr(MSR_ENERGY_PERF_BIAS_CONFIG); - msr.lo = (msr1.lo & EPB_ENERGY_POLICY_MASK) >> EPB_ENERGY_POLICY_SHIFT; - msr.hi = 0; - wrmsr(MSR_IA32_ENERGY_PERF_BIAS, msr); - - /* Enable Turbo */ - enable_turbo(); - - /* Enable speed step. */ - if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= SPEED_STEP_ENABLE_BIT; - wrmsr(IA32_MISC_ENABLE, msr); - } - - /* Clear out pending MCEs */ - xeon_configure_mca(); -} - -static struct device_operations cpu_dev_ops = { - .init = xeon_sp_core_init, -}; - -static const struct cpu_device_id cpu_table[] = { - /* Skylake-SP A0/A1 CPUID 0x506f0*/ - {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_A0_A1, CPUID_EXACT_MATCH_MASK }, - /* Skylake-SP B0 CPUID 0x506f1*/ - {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_B0, CPUID_EXACT_MATCH_MASK }, - /* Skylake-SP 4 CPUID 0x50654*/ - {X86_VENDOR_INTEL, CPUID_SKYLAKE_SP_4, CPUID_EXACT_MATCH_MASK }, - CPU_TABLE_END -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; - -#define CPU_BCLK 100 - -static void set_max_turbo_freq(void) -{ - msr_t msr, perf_ctl; - - FUNC_ENTER(); - perf_ctl.hi = 0; - - /* Check for configurable TDP option */ - if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else if (cpu_config_tdp_levels()) { - /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - wrmsr(IA32_PERF_CTL, perf_ctl); - - printk(BIOS_DEBUG, "cpu: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); - FUNC_EXIT(); -} - -/* - * Do essential initialization tasks before APs can be fired up - * - * Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This - * creates the MTRR solution that the APs will use. Otherwise APs will try to - * apply the incomplete solution as the BSP is calculating it. - */ -static void pre_mp_init(void) -{ - printk(BIOS_DEBUG, "%s: entry\n", __func__); - - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - -static void post_mp_init(void) -{ - /* Set Max Ratio */ - set_max_turbo_freq(); - - if (CONFIG(HAVE_SMI_HANDLER)) - global_smi_enable(); -} - -/* - * CPU initialization recipe - * - * Note that no microcode update is passed to the init function. CSE updates - * the microcode on all cores before releasing them from reset. That means that - * the BSP and all APs will come up with the same microcode revision. - */ -static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, - .get_cpu_count = get_platform_thread_count, - .get_smm_info = get_smm_info, - .pre_mp_smm_init = smm_southbridge_clear_state, - .relocation_handler = smm_relocation_handler, - .post_mp_init = post_mp_init, -}; - -void mp_init_cpus(struct bus *bus) -{ - FUNC_ENTER(); - - /* - * This gets used in cpu device callback. Other than cpu 0, - * rest of the CPU devices do not have - * chip_info updated. Global chip_config is used as workaround - */ - chip_config = bus->dev->chip_info; - - config_reset_cpl3_csrs(); - - /* calls src/cpu/x86/mp_init.c */ - /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(bus, &mp_ops); - - FUNC_EXIT(); -} diff --git a/src/soc/intel/xeon_sp/skx/hob_display.c b/src/soc/intel/xeon_sp/skx/hob_display.c deleted file mode 100644 index bc65e64..0000000 --- a/src/soc/intel/xeon_sp/skx/hob_display.c +++ /dev/null @@ -1,220 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <console/console.h> -#include <fsp/util.h> -#include <lib.h> -#include <assert.h> -#include <hob_iiouds.h> -#include <hob_memmap.h> - -static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; -static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; - -struct guid_name_map { - const void *guid; - const char *name; -}; - -static const struct guid_name_map guid_names[] = { - { fsp_hob_iio_uds_guid, "FSP_HOB_IIO_UNIVERSAL_DATA_GUID" }, - { fsp_hob_memmap_guid, "FSP_SYSTEM_MEMORYMAP_HOB_GUID" }, -}; - -const char *soc_get_guid_name(const uint8_t *guid) -{ - size_t index; - - /* Compare the GUID values in this module */ - for (index = 0; index < ARRAY_SIZE(guid_names); index++) - if (fsp_guid_compare(guid, guid_names[index].guid)) - return guid_names[index].name; - - return NULL; -} - -void soc_display_hob(const struct hob_header *hob) -{ - const struct hob_resource *res; - - res = fsp_hob_header_to_resource(hob); - assert(res); - printk(BIOS_DEBUG, "\tResource type: 0x%x, attribute: 0x%x, addr: 0x%08llx, len: 0x%08llx\n", - res->type, res->attribute_type, res->addr, res->length); - printk(BIOS_DEBUG, "\tOwner GUID: "); - fsp_print_guid(BIOS_DEBUG, res->owner_guid); - printk(BIOS_DEBUG, " (%s)\n", fsp_get_guid_name(res->owner_guid)); - - if (fsp_guid_compare(res->owner_guid, fsp_hob_iio_uds_guid) == 0) - soc_display_iio_universal_data_hob(); - else if (fsp_guid_compare(res->owner_guid, fsp_hob_memmap_guid) == 0) - soc_display_memmap_hob(); - else - hexdump(hob, hob->length); -} - -void soc_display_memmap_hob(void) -{ - size_t hob_size = 0; - const struct SystemMemoryMapHob *hob = - fsp_find_extension_hob_by_guid(fsp_hob_memmap_guid, &hob_size); - assert(hob && hob_size != 0); - - printk(BIOS_DEBUG, "===================== MEMORY MAP HOB DATA =====================\n"); - printk(BIOS_DEBUG, "hob: %p, hob_size: 0x%zx, SystemMemoryMapHob size: 0x%zx, " - "MAX_SOCKET: %d, SAD_RULES: %d\n", - hob, hob_size, sizeof(struct SystemMemoryMapHob), MAX_SOCKET, SAD_RULES); - printk(BIOS_DEBUG, "\tlowMemBase: 0x%x, lowMemSize: 0x%x, highMemBase: 0x%x, " - "highMemSize: 0x%x\n", - hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize); - printk(BIOS_DEBUG, "\tasilLoMemBase: 0x%x, asilHiMemBase: 0x%x, asilLoMemSize: 0x%x, " - "asilHiMemSize: 0x%x\n", - hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize); - printk(BIOS_DEBUG, "\tmemSize: 0x%x, memFreq: 0x%x, memMode: 0x%x, volMemMode: 0x%x, " - "DimmType: 0x%x, DramType: 0x%x\n", - hob->memSize, hob->memFreq, hob->memMode, hob->volMemMode, - hob->DimmType, hob->DramType); - printk(BIOS_DEBUG, "\tNumChPerMC: 0x%x, numberEntries: 0x%x, maxIMC: 0x%x, maxCh: 0x%x\n", - hob->NumChPerMC, hob->numberEntries, hob->maxIMC, hob->maxCh); - - printk(BIOS_DEBUG, "\tSystemMemoryMapElement Entries: %d\n", hob->numberEntries); - for (int e = 0; e < hob->numberEntries; ++e) { - const struct SystemMemoryMapElement *mem_element = &hob->Element[e]; - printk(BIOS_DEBUG, "\t\tmemory_map %d BaseAddress: 0x%x, ElementSize: 0x%x, Type: 0x%x\n", - e, mem_element->BaseAddress, - mem_element->ElementSize, mem_element->Type); - } -} - -void soc_display_iio_universal_data_hob(void) -{ - size_t hob_size = 0; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_uds_guid, &hob_size); - - assert(hob && hob_size != 0); - - printk(BIOS_DEBUG, "===================== IIO_UDS HOB DATA =====================\n"); - - printk(BIOS_DEBUG, "\t===================== SYSTEM STATUS =====================\n"); - printk(BIOS_DEBUG, "\tcpuType: 0x%x\n", hob->SystemStatus.cpuType); - printk(BIOS_DEBUG, "\tcpuSubType: 0x%x\n", hob->SystemStatus.cpuSubType); - printk(BIOS_DEBUG, "\tSystemRasType: 0x%x\n", hob->SystemStatus.SystemRasType); - printk(BIOS_DEBUG, "\tnumCpus: 0x%x\n", hob->SystemStatus.numCpus); - for (int x = 0; x < MAX_SOCKET; ++x) { - printk(BIOS_DEBUG, "\tSocket %d FusedCores: 0x%x, ActiveCores: 0x%x, " - "MaxCoreToBusRatio: 0x%x, MinCoreToBusRatio: 0x%x\n", - x, hob->SystemStatus.FusedCores[x], hob->SystemStatus.ActiveCores[x], - hob->SystemStatus.MaxCoreToBusRatio[x], - hob->SystemStatus.MinCoreToBusRatio[x]); - } - printk(BIOS_DEBUG, "\tCurrentCoreToBusRatio: 0x%x\n", - hob->SystemStatus.CurrentCoreToBusRatio); - printk(BIOS_DEBUG, "\tIntelSpeedSelectCapable: 0x%x\n", - hob->SystemStatus.IntelSpeedSelectCapable); - printk(BIOS_DEBUG, "\tIssConfigTdpLevelInfo: 0x%x\n", - hob->SystemStatus.IssConfigTdpLevelInfo); - for (int x = 0; x < TDP_MAX_LEVEL; ++x) { - printk(BIOS_DEBUG, "\t\tTDL Level %d IssConfigTdpTdpInfo: 0x%x, " - "IssConfigTdpPowerInfo: 0x%x, IssConfigTdpCoreCount: 0x%x\n", - x, hob->SystemStatus.IssConfigTdpTdpInfo[x], - hob->SystemStatus.IssConfigTdpPowerInfo[x], - hob->SystemStatus.IssConfigTdpCoreCount[x]); - } - printk(BIOS_DEBUG, "\tsocketPresentBitMap: 0x%x\n", - hob->SystemStatus.socketPresentBitMap); - printk(BIOS_DEBUG, "\ttolmLimit: 0x%x\n", hob->SystemStatus.tolmLimit); - printk(BIOS_DEBUG, "\ttohmLimit: 0x%x\n", hob->SystemStatus.tohmLimit); - printk(BIOS_DEBUG, "\tmmCfgBase: 0x%x\n", hob->SystemStatus.mmCfgBase); - printk(BIOS_DEBUG, "\tnumChPerMC: 0x%x\n", hob->SystemStatus.numChPerMC); - printk(BIOS_DEBUG, "\tmaxCh: 0x%x\n", hob->SystemStatus.maxCh); - printk(BIOS_DEBUG, "\tmaxIMC: 0x%x\n", hob->SystemStatus.maxIMC); - - printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n"); - printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase); - printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit); - printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n", - hob->PlatformData.PlatGlobalMmiolBase); - printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n", - hob->PlatformData.PlatGlobalMmiolLimit); - printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n", - hob->PlatformData.PlatGlobalMmiohBase); - printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n", - hob->PlatformData.PlatGlobalMmiohLimit); - printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize); - printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize); - printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase); - printk(BIOS_DEBUG, "\tPciExpressSize: 0x%x\n", hob->PlatformData.PciExpressSize); - printk(BIOS_DEBUG, "\tMemTolm: 0x%x\n", hob->PlatformData.MemTolm); - printk(BIOS_DEBUG, "\tnumofIIO: 0x%x\n", hob->PlatformData.numofIIO); - printk(BIOS_DEBUG, "\tMaxBusNumber: 0x%x\n", hob->PlatformData.MaxBusNumber); - printk(BIOS_DEBUG, "\tIoGranularity: 0x%x\n", hob->PlatformData.IoGranularity); - printk(BIOS_DEBUG, "\tMmiolGranularity: 0x%x\n", hob->PlatformData.MmiolGranularity); - printk(BIOS_DEBUG, "\tMmiohGranularity: hi: 0x%x, lo:0x%x\n", - hob->PlatformData.MmiohGranularity.hi, hob->PlatformData.MmiohGranularity.lo); - - for (int s = 0; s < MAX_SOCKET; ++s) { - printk(BIOS_DEBUG, "\t============ Socket %d Info ================\n", s); - printk(BIOS_DEBUG, "\tSocketID: 0x%x\n", - hob->PlatformData.IIO_resource[s].SocketID); - printk(BIOS_DEBUG, "\tBusBase: 0x%x\n", - hob->PlatformData.IIO_resource[s].BusBase); - printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n", - hob->PlatformData.IIO_resource[s].BusLimit); - printk(BIOS_DEBUG, "\tPciResourceIoBase: 0x%x\n", - hob->PlatformData.IIO_resource[s].PciResourceIoBase); - printk(BIOS_DEBUG, "\tPciResourceIoLimit: 0x%x\n", - hob->PlatformData.IIO_resource[s].PciResourceIoLimit); - printk(BIOS_DEBUG, "\tIoApicBase: 0x%x\n", - hob->PlatformData.IIO_resource[s].IoApicBase); - printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n", - hob->PlatformData.IIO_resource[s].IoApicLimit); - printk(BIOS_DEBUG, "\tPciResourceMem32Base: 0x%x\n", - hob->PlatformData.IIO_resource[s].PciResourceMem32Base); - printk(BIOS_DEBUG, "\tPciResourceMem32Limit: 0x%x\n", - hob->PlatformData.IIO_resource[s].PciResourceMem32Limit); - printk(BIOS_DEBUG, "\tPciResourceMem64Base: 0x%llx\n", - hob->PlatformData.IIO_resource[s].PciResourceMem64Base); - printk(BIOS_DEBUG, "\tPciResourceMem64Limit: 0x%llx\n", - hob->PlatformData.IIO_resource[s].PciResourceMem64Limit); - - printk(BIOS_DEBUG, "\t============ Stack Info ================\n"); - for (int x = 0; x < MAX_IIO_STACK; ++x) { - const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; - printk(BIOS_DEBUG, "\t\t========== Stack %d ===============\n", x); - printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase); - printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit); - printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", - ri->PciResourceIoBase); - printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", - ri->PciResourceIoLimit); - printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase); - printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit); - printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n", - ri->PciResourceMem32Base); - printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n", - ri->PciResourceMem32Limit); - printk(BIOS_DEBUG, "\t\tPciResourceMem64Base: 0x%llx\n", - ri->PciResourceMem64Base); - printk(BIOS_DEBUG, "\t\tPciResourceMem64Limit: 0x%llx\n", - ri->PciResourceMem64Limit); - printk(BIOS_DEBUG, "\t\tVtdBarAddress: 0x%x\n", ri->VtdBarAddress); - } - - printk(BIOS_DEBUG, "\t============ PcieInfo ================\n"); - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[s]; - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { - printk(BIOS_DEBUG, "\t\tPort: %d, Device: 0x%x, Function: 0x%x\n", - p, iio_resource.PcieInfo.PortInfo[p].Device, - iio_resource.PcieInfo.PortInfo[p].Function); - } - } - - printk(BIOS_DEBUG, "\t============ Bus Bases ===============\n"); - for (int socket = 0; socket < MAX_SOCKET; ++socket) { - for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { - printk(BIOS_DEBUG, "socket: %d, stack: %d, busno: 0x%x\n", - socket, stack, - hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]); - } - } -} diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h deleted file mode 100644 index 3d518fa..0000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SOC_PCI_DEVS_H_ -#define _SOC_PCI_DEVS_H_ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <hob_iiouds.h> -#include <soc/pch_pci_devs.h> - -#define dump_csr(fmt, dev, reg) \ - printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \ - fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ - ((uint32_t)dev >> 12) & 0x07, \ - #reg, reg, pci_s_read_config32(dev, reg)) - -#define dump_csr64(fmt, dev, reg) \ - printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x%x\n", \ - fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \ - ((uint32_t)dev >> 12) & 0x07, #reg, reg, \ - pci_s_read_config32(dev, reg+4), pci_s_read_config32(dev, reg)) - -#define SAD_ALL_DEV 29 -#define SAD_ALL_FUNC 0 -#define SAD_ALL_PAM0123_CSR 0x40 -#define PAM_LOCK BIT(0) -#define SAD_ALL_PAM456_CSR 0x44 - -#if !defined(__SIMPLE_DEVICE__) -#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) -#else -#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) -#endif - -#define PCU_IIO_STACK 1 -#define PCU_DEV 30 -#define PCU_CR1_FUN 1 - -#define PCU_CR0_FUN 0 -#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) -#define PCU_CR0_PLATFORM_INFO 0xa8 -#define PCU_CR0_P_STATE_LIMITS 0xd8 -#define P_STATE_LIMITS_LOCK_SHIFT 31 -#define P_STATE_LIMITS_LOCK (1 << P_STATE_LIMITS_LOCK_SHIFT) -#define PCU_CR0_TEMPERATURE_TARGET 0xe4 -#define PCU_CR0_PACKAGE_RAPL_LIMIT 0xe8 -#define PCU_CR0_CURRENT_CONFIG 0xf8 -#define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ -#define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT) -#define PCU_CR0_PMAX 0xf0 -#define PMAX_LOCK BIT(31) - -#define PCU_CR1_BIOS_MB_DATA_REG 0x8c - -#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 -#define BIOS_MB_RUN_BUSY_MASK BIT(31) -#define BIOS_MB_CMD_MASK 0xff -#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 -#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 -#define BIOS_ERR_INVALID_CMD 0x01 - -#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 -#define RST_CPL1_MASK BIT(1) -#define RST_CPL2_MASK BIT(2) -#define RST_CPL3_MASK BIT(3) -#define RST_CPL4_MASK BIT(4) -#define PCODE_INIT_DONE1_MASK BIT(9) -#define PCODE_INIT_DONE2_MASK BIT(10) -#define PCODE_INIT_DONE3_MASK BIT(11) -#define PCODE_INIT_DONE4_MASK BIT(12) - -#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 -#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) - -#if !defined(__SIMPLE_DEVICE__) -#define _UBOX_DEV(func) pcidev_path_on_root_debug(PCI_DEVFN(UBOX_DEV, func), __func__) -#else -#define _UBOX_DEV(func) PCI_DEV(0, UBOX_DEV, func) -#endif - -#define UBOX_DEV 8 - -#define UBOX_PMON_BUS 0 -#define UBOX_PMON_DEV 8 -#define UBOX_PMON_FUNC 1 -#define UBOX_DEV_PMON _UBOX_DEV(UBOX_PMON_FUNC) -#define SMM_FEATURE_CONTROL 0x7c -#define SMM_CODE_CHK_EN BIT(2) -#define SMM_FEATURE_CONTROL_LOCK BIT(0) - -#define UBOX_DECS_BUS 0 -#define UBOX_DECS_DEV 8 -#define UBOX_DECS_FUNC 2 -#define UBOX_DECS_CPUBUSNO_CSR 0xcc -#define UBOX_DECS_CPUBUSNO1_CSR 0xd0 - -#define VTD_TOLM_CSR 0xd0 -#define VTD_TSEG_BASE_CSR 0xa8 -#define VTD_TSEG_LIMIT_CSR 0xac -#define VTD_EXT_CAP_LOW 0x10 -#define VTD_MMCFG_BASE_CSR 0x90 -#define VTD_MMCFG_LIMIT_CSR 0x98 -#define VTD_TOHM_CSR 0xd4 -#define VTD_MMIOL_CSR 0xdc -#define VTD_ME_BASE_CSR 0xf0 -#define VTD_ME_LIMIT_CSR 0xf8 -#define VTD_VERSION 0x00 -#define VTD_CAP 0x08 -#define VTD_CAP_LOW 0x08 -#define VTD_CAP_HIGH 0x0C -#define VTD_EXT_CAP_HIGH 0x14 -#define VTD_LTDPR 0x290 - -#define PCU_CR1_C2C3TT_REG 0xdc -#define PCU_CR1_PCIE_ILTR_OVRD 0xfc -#define PCU_CR1_SAPMCTL 0xb0 -#define SAPMCTL_LOCK_SHIFT 31 -#define SAPMCTL_LOCK_MASK (1 << SAPMCTL_LOCK_SHIFT) -#define PCU_CR1_MC_BIOS_REQ 0x98 - -#define PCU_CR2_FUN 2 -#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK 0x8c -#define PCIE_IN_PKGCSTATE_L1_MASK 0xFFFFFF /* 23:0 bits */ -#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2 0x90 -#define KTI_IN_PKGCSTATE_L1_MASK 0x7 /* 2:0 bits */ -#define PCU_CR2_DYNAMIC_PERF_POWER_CTL 0xdc -#define UNCORE_PLIMIT_OVERRIDE_BIT 20 -#define UNOCRE_PLIMIT_OVERRIDE_SHIFT (1 << UNCORE_PLIMIT_OVERRIDE_BIT) -#define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG 0xb0 -#define PROCHOT_RATIO 0xa /* bits 0:7 */ - -#define CHA_UTIL_ALL_DEV 29 -#define CHA_UTIL_ALL_FUNC 1 -#define CHA_UTIL_ALL_MMCFG_CSR 0xc0 - -#define MMAP_VTD_CFG_REG_DEVID 0x2024 -#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 -#define VTD_DEV_NUM 0x5 -#define VTD_FUNC_NUM 0x0 - -#if !defined(__SIMPLE_DEVICE__) -#define VTD_DEV(bus) pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)) -#else -#define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM) -#endif - -#define CBDMA_DEV_NUM 0x04 -#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function -#define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB - -#define VMD_DEV_NUM 0x05 -#define VMD_FUNC_NUM 0x05 - -#define APIC_DEV_NUM 0x05 -#define APIC_FUNC_NUM 0x00 - -// DMI3 B0D0F0 registers -#define DMI3_DEVID 0x2020 -#define DMIRCBAR 0x50 -#define ERRINJCON 0x1d8 - -// IIO DFX Global D7F7 registers -#define IIO_DFX_TSWCTL0 0x30c -#define IIO_DFX_LCK_CTL 0x504 - -pci_devfn_t soc_get_ubox_pmon_dev(void); - -#endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h deleted file mode 100644 index e524cea..0000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_msr.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SOC_MSR_SKX_H_ -#define _SOC_MSR_SKX_H_ - -/* MCA_ERROR_CONTROL */ -#define U2C_SMI_ENABLED (1 << 2) - -/* IA32_ERR_CTRL */ -#define CORE_ERR_DISABLE (1 << 5) -#define CMCI_DISABLE (1 << 4) -#define UCE_TO_CE_DOWNGRADE (1 << 2) - -/* MSR_PKG_CST_CONFIG_CONTROL */ -#define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT) - -/* MSR_POWER_CTL (SKX and CPX) */ -#define FAST_BRK_SNP_ENABLE_SHIFT 3 -#define FAST_BRK_SNP_ENABLE (1 << FAST_BRK_SNP_ENABLE_SHIFT) -#define FAST_BRK_INT_ENABLE_SHIFT 4 -#define FAST_BRK_INT_ENABLE (1 << FAST_BRK_INT_ENABLE_SHIFT) -#define PHOLD_CST_PREVENTION_INIT_SHIFT 6 -#define PHOLD_CST_PREVENTION_INIT_VALUE (1 << PHOLD_CST_PREVENTION_INIT_SHIFT) -#define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT 18 -#define ENERGY_PERF_BIAS_ACCESS_ENABLE (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT) -#define PROCHOT_OUTPUT_DISABLE_SHIFT 21 -#define PROCHOT_OUTPUT_DISABLE (1 << PROCHOT_OUTPUT_DISABLE_SHIFT) -#define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT 24 -#define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT) -#define PROCHOT_LOCK_SHIFT 27 -#define PROCHOT_LOCK_ENABLE (1 << PROCHOT_LOCK_SHIFT) -#define LTR_IIO_DISABLE_SHIFT 29 -#define LTR_IIO_DISABLE (1 << LTR_IIO_DISABLE_SHIFT) - -#endif /* _SOC_MSR_SKX_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h deleted file mode 100644 index 379cdc8..0000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_UTIL_H_ -#define _SOC_UTIL_H_ - -#include <hob_iiouds.h> -#include <hob_memmap.h> - -void config_reset_cpl3_csrs(void); - -const struct SystemMemoryMapHob *get_system_memory_map(void); - -uint8_t get_stack_busno(const uint8_t stack); -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); -uint32_t get_socket_ubox_busno(uint32_t socket); - -int soc_get_stack_for_port(int port); -uint8_t get_cxl_node_count(void); - -#endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c deleted file mode 100644 index a5c78f6..0000000 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/romstage.h> -#include <intelblocks/rtc.h> -#include <soc/romstage.h> -#include <soc/soc_util.h> - -#include "chip.h" - -void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -{ - const config_t *config = config_of_soc(); - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - - mupd->FspmUpdVersion = FSP_UPD_VERSION; - - // ErrorLevel - 0 (disable) to 8 (verbose) - m_cfg->PcdFspMrcDebugPrintErrorLevel = 0; - m_cfg->PcdFspKtiDebugPrintErrorLevel = 0; - - mainboard_memory_init_params(mupd); - - m_cfg->VTdConfig.VTdSupport = config->vtd_support; - m_cfg->VTdConfig.CoherencySupport = config->coherency_support; - m_cfg->VTdConfig.ATS = config->ats_support; -} diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c deleted file mode 100644 index dfbd878..0000000 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpigen.h> -#include <arch/smp/mpspec.h> -#include <arch/vga.h> -#include <assert.h> -#include <cpu/intel/turbo.h> -#include <device/mmio.h> -#include <device/pci.h> -#include <intelblocks/acpi.h> -#include <soc/acpi.h> -#include <soc/iomap.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <soc/pm.h> -#include <soc/soc_util.h> -#include <soc/util.h> - -int soc_madt_sci_irq_polarity(int sci) -{ - if (sci >= 20) - return MP_IRQ_POLARITY_LOW; - else - return MP_IRQ_POLARITY_HIGH; -} - -uint32_t soc_read_sci_irq_select(void) -{ - struct device *dev = PCH_DEV_PMC; - - if (!dev) - return 0; - - return pci_read_config32(dev, PMC_ACPI_CNT); -} - -void soc_fill_fadt(acpi_fadt_t *fadt) -{ - const uint16_t pmbase = ACPI_BASE_ADDRESS; - - /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ - fadt->flags &= ~(ACPI_FADT_SEALED_CASE); - fadt->flags |= ACPI_FADT_SLEEP_TYPE; - - fadt->pm2_cnt_blk = pmbase + PM2_CNT; - fadt->pm_tmr_blk = pmbase + PM1_TMR; - - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - /* PM Extended Registers */ - fill_fadt_extended_pm_io(fadt); -} - -void uncore_fill_ssdt(const struct device *device) -{ - const IIO_UDS *hob = get_iio_uds(); - - /* Only add RTxx entries once. */ - if (device->bus->secondary != 0) - return; - - for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) { - if (!soc_cpu_is_enabled(socket)) - continue; - iio++; - IIO_RESOURCE_INSTANCE iio_resource = - hob->PlatformData.IIO_resource[socket]; - for (int stack = 0; stack <= PSTACK2; ++stack) { - const STACK_RES *ri = &iio_resource.StackRes[stack]; - char rtname[16]; - - snprintf(rtname, sizeof(rtname), "\\_SB.PC%02x", socket * MAX_IIO_STACK + stack); - acpigen_write_scope(rtname); - - acpigen_write_name("_CRS"); - - printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", - rtname, socket, stack); - - acpigen_write_resourcetemplate_header(); - - /* bus resource */ - acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, - 0x0, (ri->BusLimit - ri->BusBase + 1)); - - // additional io resources on socket 0 bus 0 - if (socket == 0 && stack == 0) { - /* ACPI 6.4.2.5 I/O Port Descriptor */ - acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); - - /* IO decode CF8-CFF */ - acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, - 0, 0x03B0); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, - 0, 0x0918); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, - 0, 0x000C); - acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, - 0, 0x0020); - } - - /* IO resource */ - acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, - ri->PciResourceIoLimit, 0x0, - (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); - - // additional mem32 resources on socket 0 bus 0 - if (socket == 0 && stack == 0) { - acpigen_resource_dword(0, 0xc, 3, 0, VGA_MMIO_BASE, - VGA_MMIO_LIMIT, 0x0, VGA_MMIO_SIZE); - acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, - (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, - SPI_BASE_SIZE); - } - - /* Mem32 resource */ - acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, - ri->PciResourceMem32Limit, 0x0, - (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); - - /* Mem64 resource */ - acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, - ri->PciResourceMem64Limit, 0x0, - (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); - - acpigen_write_resourcetemplate_footer(); - - /* Scope */ - acpigen_pop_len(); - } - } -} - -void soc_power_states_generation(int core, int cores_per_package) -{ -} diff --git a/src/soc/intel/xeon_sp/skx/soc_smihandler_util.c b/src/soc/intel/xeon_sp/skx/soc_smihandler_util.c deleted file mode 100644 index 6f772cc..0000000 --- a/src/soc/intel/xeon_sp/skx/soc_smihandler_util.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/pci_devs.h> - -pci_devfn_t soc_get_ubox_pmon_dev(void) -{ - return UBOX_DEV_PMON; -} diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c deleted file mode 100644 index a5db8fd..0000000 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ /dev/null @@ -1,188 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <assert.h> -#include <console/console.h> -#include <device/pci.h> -#include <hob_iiouds.h> -#include <intelblocks/cpulib.h> -#include <intelblocks/pcr.h> -#include <soc/iomap.h> -#include <soc/msr.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> -#include <soc/soc_util.h> -#include <soc/util.h> - - -/* - * +-------------------------+ TOLM - * | System Management Mode | - * | code and data | - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ - -const struct SystemMemoryMapHob *get_system_memory_map(void) -{ - size_t hob_size; - const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; - const struct SystemMemoryMapHob *memmap_addr; - - memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); - assert(memmap_addr && hob_size != 0); - - return memmap_addr; -} - -bool is_pcie_iio_stack_res(const STACK_RES *res) -{ - return res->BusBase < res->BusLimit; -} - -uint8_t get_stack_busno(const uint8_t stack) -{ - if (stack >= MAX_IIO_STACK) { - printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack); - return 0; - } - const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC); - const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR; - return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff; -} - -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) -{ - const IIO_UDS *hob = get_iio_uds(); - - assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK); - - return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; -} - -uint32_t get_socket_ubox_busno(uint32_t socket) -{ - if (socket == 0) - return get_stack_busno(PCU_IIO_STACK); - - return get_socket_stack_busno(socket, PCU_IIO_STACK); -} - -void config_reset_cpl3_csrs(void) -{ - uint32_t data, plat_info, max_min_turbo_limit_ratio; - - for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - - /* configure PCU_CR0_FUN csrs */ - pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); - data = pci_s_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); - data |= P_STATE_LIMITS_LOCK; - pci_s_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); - - plat_info = pci_s_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); - dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO); - max_min_turbo_limit_ratio = - (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> - MAX_NON_TURBO_LIM_RATIO_SHIFT; - printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n", - plat_info, max_min_turbo_limit_ratio); - - /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - data = pci_s_read_config32(cr1_dev, PCU_CR1_SAPMCTL); - /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ - data &= 0x0fffffff; - data |= SAPMCTL_LOCK_MASK; - pci_s_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); - - /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); - - data = PCIE_IN_PKGCSTATE_L1_MASK; - pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); - - data = KTI_IN_PKGCSTATE_L1_MASK; - pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); - - data = PROCHOT_RATIO; - printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); - pci_s_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); - dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); - - data = pci_s_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); - data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; - pci_s_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); - } -} - -/* - * EX: SKX-SP - * Ports Stack Stack(HOB) IioConfigIou - * ========================================== - * 0 CSTACK stack 0 IOU0 - * 1A..1D PSTACKZ stack 1 IOU1 - * 2A..2D PSTACK1 stack 2 IOU2 - * 3A..3D PSTACK2 stack 3 IOU3 - * 5A..4D PSTACK3 stack 4 IOU4 - * 5A..5D PSTACK4 stack 5 IOU5 - */ -int soc_get_stack_for_port(int port) -{ - if (port == PORT_0) - return CSTACK; - else if (port >= PORT_1A && port <= PORT_1D) - return PSTACK0; - else if (port >= PORT_2A && port <= PORT_2D) - return PSTACK1; - else if (port >= PORT_3A && port <= PORT_3D) - return PSTACK2; - else if (port >= PORT_4A && port <= PORT_4D) - return PSTACK3; // MCP0 - else if (port >= PORT_5A && port <= PORT_5D) - return PSTACK4; // MCP1 - else - return -1; -} - -uint8_t soc_get_iio_ioapicid(int socket, int stack) -{ - uint8_t ioapic_id = socket ? 0xf : 0x9; - switch (stack) { - case CSTACK: - break; - case PSTACK0: - ioapic_id += 1; - break; - case PSTACK1: - ioapic_id += 2; - break; - case PSTACK2: - ioapic_id += 3; - break; - default: - return 0xff; - } - return ioapic_id; -} diff --git a/src/soc/intel/xeon_sp/skx/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c deleted file mode 100644 index c718a58..0000000 --- a/src/soc/intel/xeon_sp/skx/upd_display.c +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <console/console.h> -#include <fsp/util.h> -#include <lib.h> - -#define DUMP_UPD(old, new, field) \ - fsp_display_upd_value(#field, sizeof(old->field), old->field, new->field) - -/* Display the UPD parameters for MemoryInit */ -void soc_display_fspm_upd_params( - const FSPM_UPD *fspm_old_upd, - const FSPM_UPD *fspm_new_upd) -{ - const FSP_M_CONFIG *new; - const FSP_M_CONFIG *old; - - old = &fspm_old_upd->FspmConfig; - new = &fspm_new_upd->FspmConfig; - - printk(BIOS_DEBUG, "UPD values for MemoryInit:\n"); - - DUMP_UPD(old, new, PcdFspMrcDebugPrintErrorLevel); - DUMP_UPD(old, new, PcdFspKtiDebugPrintErrorLevel); - DUMP_UPD(old, new, PcdHsuartDevice); - - hexdump(fspm_new_upd, sizeof(*fspm_new_upd)); -} - -/* Display the UPD parameters for SiliconInit */ -void soc_display_fsps_upd_params( - const FSPS_UPD *fsps_old_upd, - const FSPS_UPD *fsps_new_upd) -{ - const FSP_S_CONFIG *new; - const FSP_S_CONFIG *old; - - old = &fsps_old_upd->FspsConfig; - new = &fsps_new_upd->FspsConfig; - - printk(BIOS_DEBUG, "UPD values for SiliconInit:\n"); - - DUMP_UPD(old, new, PcdBifurcationPcie0); - DUMP_UPD(old, new, PcdBifurcationPcie1); - DUMP_UPD(old, new, PcdActiveCoreCount); - DUMP_UPD(old, new, PcdCpuMicrocodePatchBase); - DUMP_UPD(old, new, PcdCpuMicrocodePatchSize); - DUMP_UPD(old, new, PcdEnablePcie0); - DUMP_UPD(old, new, PcdEnablePcie1); - DUMP_UPD(old, new, PcdEnableEmmc); - DUMP_UPD(old, new, PcdEnableGbE); - DUMP_UPD(old, new, PcdFiaMuxConfigRequestPtr); - DUMP_UPD(old, new, PcdPcieRootPort0DeEmphasis); - DUMP_UPD(old, new, PcdPcieRootPort1DeEmphasis); - DUMP_UPD(old, new, PcdPcieRootPort2DeEmphasis); - DUMP_UPD(old, new, PcdPcieRootPort3DeEmphasis); - DUMP_UPD(old, new, PcdPcieRootPort4DeEmphasis); - DUMP_UPD(old, new, PcdPcieRootPort5DeEmphasis); - DUMP_UPD(old, new, PcdPcieRootPort6DeEmphasis); - DUMP_UPD(old, new, PcdPcieRootPort7DeEmphasis); - DUMP_UPD(old, new, PcdEMMCDLLConfigPtr); - - hexdump(fsps_new_upd, sizeof(*fsps_new_upd)); -} diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index e2b47329..8376cf7 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -289,7 +289,7 @@ } /* SPR has no per stack IOAPIC or CBDMA devices */ -#if CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP) +#if CONFIG(SOC_INTEL_COOPERLAKE_SP) uint32_t enum_id; // Add IOAPIC entry enum_id = soc_get_iio_ioapicid(socket, stack); @@ -322,7 +322,7 @@ dev = dev->sibling; } -#if CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP) +#if CONFIG(SOC_INTEL_COOPERLAKE_SP) // Add VMD if (hob->PlatformData.VMDStackEnable[socket][stack] && stack >= PSTACK0 && stack <= PSTACK2) { @@ -606,10 +606,6 @@ dmar = (acpi_dmar_t *)current; enum dmar_flags flags = DMAR_INTR_REMAP; - /* SKX FSP doesn't support X2APIC, but CPX FSP does */ - if (CONFIG(SOC_INTEL_SKYLAKE_SP)) - flags |= DMAR_X2APIC_OPT_OUT; - printk(BIOS_DEBUG, "ACPI: * DMAR at %lx\n", current); printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", flags); acpi_create_dmar(dmar, flags, acpi_fill_dmar); -- To view, visit https://review.coreboot.org/c/coreboot/+/80172?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12b092f00386cb71fac02d8d0b10375d3241abb3 Gerrit-Change-Number: 80172 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[main]: mb/ocp: Drop tiogapass
by Patrick Rudolph (Code Review) 23 Jan '24

23 Jan '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80171?usp=email ) Change subject: mb/ocp: Drop tiogapass ...................................................................... mb/ocp: Drop tiogapass The platform code depends on unreleased binary files and uses incomplete public header files. In order to reduce maintainance burden for the Xeon-SP platforms drop this old code. Change-Id: I838b9ea3955d31ea393494c2e726845fe234ef3a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- D src/mainboard/ocp/tiogapass/Kconfig D src/mainboard/ocp/tiogapass/Kconfig.name D src/mainboard/ocp/tiogapass/Makefile.inc D src/mainboard/ocp/tiogapass/acpi/platform.asl D src/mainboard/ocp/tiogapass/acpi_tables.c D src/mainboard/ocp/tiogapass/board.fmd D src/mainboard/ocp/tiogapass/board_info.txt D src/mainboard/ocp/tiogapass/bootblock.c D src/mainboard/ocp/tiogapass/console.c D src/mainboard/ocp/tiogapass/devicetree.cb D src/mainboard/ocp/tiogapass/dsdt.asl D src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h D src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h D src/mainboard/ocp/tiogapass/ipmi.c D src/mainboard/ocp/tiogapass/ipmi.h D src/mainboard/ocp/tiogapass/ramstage.c D src/mainboard/ocp/tiogapass/romstage.c D src/mainboard/ocp/tiogapass/vpd.h 18 files changed, 0 insertions(+), 1,552 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/80171/1 diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig deleted file mode 100644 index 886743c..0000000 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -if BOARD_OCP_TIOGAPASS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_32768 - select HAVE_ACPI_TABLES - select IPMI_KCS - select IPMI_KCS_ROMSTAGE - select IPMI_OCP - select MAINBOARD_USES_FSP2_0 - select OCP_DMI - select SOC_INTEL_SKYLAKE_SP - select SUPERIO_ASPEED_AST2400 - select UART_OVERRIDE_BAUDRATE - select VPD - -config MAINBOARD_DIR - default "ocp/tiogapass" - -config MAINBOARD_PART_NUMBER - default "TiogaPass" - -config MAINBOARD_FAMILY - string - default "TiogaPass" - -config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" - -config UART_FOR_CONSOLE - int - default 1 - -config TTYS0_BAUD - default 57600 - -endif # BOARD_OCP_TIOGAPASS diff --git a/src/mainboard/ocp/tiogapass/Kconfig.name b/src/mainboard/ocp/tiogapass/Kconfig.name deleted file mode 100644 index e1bf821..0000000 --- a/src/mainboard/ocp/tiogapass/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_OCP_TIOGAPASS - bool "TiogaPass" diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc deleted file mode 100644 index bcf0e6c..0000000 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -bootblock-y += bootblock.c -romstage-y += ipmi.c -ramstage-y += ramstage.c ipmi.c - -all-y += console.c - -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/ocp/tiogapass/acpi/platform.asl b/src/mainboard/ocp/tiogapass/acpi/platform.asl deleted file mode 100644 index 1899de1..0000000 --- a/src/mainboard/ocp/tiogapass/acpi/platform.asl +++ /dev/null @@ -1,327 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* Enable ACPI _SWS methods */ -#include <soc/intel/common/acpi/acpi_wake_source.asl> - -Name (_S0, Package (0x04) // mandatory system state -{ - 0x00, 0x00, 0x00, 0x00 -}) - -Name (_S5, Package (0x04) // mandatory system state -{ - 0x07, 0x00, 0x00, 0x00 -}) - -/* The APM port can be used for generating software SMIs */ -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -#include <arch/x86/acpi/post.asl> - -OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400) -Field (PSYS, ByteAcc, NoLock, Preserve) -{ - PLAT, 32, // Platform ID - - // IOAPIC - APC0, 1, // PCH IOAPIC Enable - AP00, 1, // PC00 IOAPIC Enable - AP01, 1, // PC01 IOAPIC Enable - AP02, 1, // PC02 IOAPIC Enable - AP03, 1, // PC03 IOAPIC Enable - AP04, 1, // PC04 IOAPIC Enable - AP05, 1, // PC05 IOAPIC Enable - AP06, 1, // PC06 IOAPIC Enable - AP07, 1, // PC07 IOAPIC Enable - AP08, 1, // PC08 IOAPIC Enable - AP09, 1, // PC09 IOAPIC Enable - AP10, 1, // PC10 IOAPIC Enable - AP11, 1, // PC11 IOAPIC Enable - AP12, 1, // PC12 IOAPIC Enable - AP13, 1, // PC13 IOAPIC Enable - AP14, 1, // PC14 IOAPIC Enable - AP15, 1, // PC15 IOAPIC Enable - AP16, 1, // PC16 IOAPIC Enable - AP17, 1, // PC17 IOAPIC Enable - AP18, 1, // PC18 IOAPIC Enable - AP19, 1, // PC19 IOAPIC Enable - AP20, 1, // PC20 IOAPIC Enable - AP21, 1, // PC21 IOAPIC Enable - AP22, 1, // PC22 IOAPIC Enable - AP23, 1, // PC23 IOAPIC Enable - RESA, 7, - SKOV, 1, // Override Socket APIC Id - RES0, 7, - - // Power Management - TPME, 1, - CSEN, 1, - C3EN, 1, - C6EN, 1, - C7EN, 1, - MWOS, 1, - PSEN, 1, - EMCA, 1, - HWAL, 2, - KPRS, 1, - MPRS, 1, - TSEN, 1, - FGTS, 1, - OSCX, 1, - RESX, 1, - - // RAS - CPHP, 8, - IIOP, 8, - IIOH, 64, - PRBM, 32, - P0ID, 32, - P1ID, 32, - P2ID, 32, - P3ID, 32, - P4ID, 32, - P5ID, 32, - P6ID, 32, - P7ID, 32, - P0BM, 64, - P1BM, 64, - P2BM, 64, - P3BM, 64, - P4BM, 64, - P5BM, 64, - P6BM, 64, - P7BM, 64, - MEBM, 16, - MEBC, 16, - CFMM, 32, - TSSY, 32, // TODO: This is TSSZ in system booted from production FW - M0BS, 64, - M1BS, 64, - M2BS, 64, - M3BS, 64, - M4BS, 64, - M5BS, 64, - M6BS, 64, - M7BS, 64, - M0RN, 64, - M1RN, 64, - M2RN, 64, - M3RN, 64, - M4RN, 64, - M5RN, 64, - M6RN, 64, - M7RN, 64, - SMI0, 32, - SMI1, 32, - SMI2, 32, - SMI3, 32, - SCI0, 32, - SCI1, 32, - SCI2, 32, - SCI3, 32, - MADD, 64, - CUU0, 128, - CUU1, 128, - CUU2, 128, - CUU3, 128, - CUU4, 128, - CUU5, 128, - CUU6, 128, - CUU7, 128, - CPSP, 8, - ME00, 128, - ME01, 128, - ME10, 128, - ME11, 128, - ME20, 128, - ME21, 128, - ME30, 128, - ME31, 128, - ME40, 128, - ME41, 128, - ME50, 128, - ME51, 128, - ME60, 128, - ME61, 128, - ME70, 128, - ME71, 128, - MESP, 16, - LDIR, 64, - PRID, 32, - AHPE, 8, - - // VTD - DHRD, 192, - ATSR, 192, - RHSA, 192, - - // SR-IOV - WSIC, 8, - WSIS, 16, - WSIB, 8, - WSID, 8, - WSIF, 8, - WSTS, 8, - WHEA, 8, - - // BIOS Guard - BGMA, 64, - BGMS, 8, - BGIO, 16, - BGIL, 8, - CNBS, 8, - - // USB3 - XHMD, 8, - SBV1, 8, - SBV2, 8, - - // HWPM - HWEN, 2, - ACEN, 1, - HWPI, 1, - RES1, 4, - - // IIO - BB00, 8, - BB01, 8, - BB02, 8, - BB03, 8, - BB04, 8, - BB05, 8, - BB06, 8, - BB07, 8, - BB08, 8, - BB09, 8, - BB10, 8, - BB11, 8, - BB12, 8, - BB13, 8, - BB14, 8, - BB15, 8, - BB16, 8, - BB17, 8, - BB18, 8, - BB19, 8, - BB20, 8, - BB21, 8, - BB22, 8, - BB23, 8, - BB24, 8, - BB25, 8, - BB26, 8, - BB27, 8, - BB28, 8, - BB29, 8, - BB30, 8, - BB31, 8, - BB32, 8, - BB33, 8, - BB34, 8, - BB35, 8, - BB36, 8, - BB37, 8, - BB38, 8, - BB39, 8, - BB40, 8, - BB41, 8, - BB42, 8, - BB43, 8, - BB44, 8, - BB45, 8, - BB46, 8, - BB47, 8, - SGEN, 8, - SG00, 8, - SG01, 8, - SG02, 8, - SG03, 8, - SG04, 8, - SG05, 8, - SG06, 8, - SG07, 8, - - // Performance - CLOD, 8, - - // XTU - XTUB, 32, - XTUS, 32, - XMBA, 32, - DDRF, 8, - RT3S, 8, - RTP0, 8, - RTP3, 8, - - // FPGA - FBB0, 8, - FBB1, 8, - FBB2, 8, - FBB3, 8, - FBB4, 8, - FBB5, 8, - FBB6, 8, - FBB7, 8, - FBL0, 8, - FBL1, 8, - FBL2, 8, - FBL3, 8, - FBL4, 8, - FBL5, 8, - FBL6, 8, - FBL7, 8, - P0FB, 8, - P1FB, 8, - P2FB, 8, - P3FB, 8, - P4FB, 8, - P5FB, 8, - P6FB, 8, - P7FB, 8, - FMB0, 32, - FMB1, 32, - FMB2, 32, - FMB3, 32, - FMB4, 32, - FMB5, 32, - FMB6, 32, - FMB7, 32, - FML0, 32, - FML1, 32, - FML2, 32, - FML3, 32, - FML4, 32, - FML5, 32, - FML6, 32, - FML7, 32, - FKPB, 32, - FKB0, 8, - FKB1, 8, - FKB2, 8, - FKB3, 8, - FKB4, 8, - FKB5, 8, - FKB6, 8, - FKB7, 8 -} - -/* - * The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method (_PTS, 1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method (_WAK, 1) -{ - Return (Package (){ 0, 0 }) -} diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c deleted file mode 100644 index b6e3846..0000000 --- a/src/mainboard/ocp/tiogapass/acpi_tables.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> - -void mainboard_fill_fadt(acpi_fadt_t *fadt) -{ - fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; -} diff --git a/src/mainboard/ocp/tiogapass/board.fmd b/src/mainboard/ocp/tiogapass/board.fmd deleted file mode 100644 index 2ecce06..0000000 --- a/src/mainboard/ocp/tiogapass/board.fmd +++ /dev/null @@ -1,19 +0,0 @@ -FLASH 32M { - SI_ALL@0x0 0xa36000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0xa23000 - PLATFORM_DATA@0xa26000 0x10000 - } - SI_BIOS@0x1000000 0x1000000 { - MISC_RW@0x0 0x10000 { - RW_VPD(PRESERVE)@0x0 0x4000 - } - WP_RO@0x10000 0xff0000 { - RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0xfec000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x800 0xfeb800 - } - } - } -} diff --git a/src/mainboard/ocp/tiogapass/board_info.txt b/src/mainboard/ocp/tiogapass/board_info.txt deleted file mode 100644 index e86f78f..0000000 --- a/src/mainboard/ocp/tiogapass/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: TiogaPass -Category: server -ROM protocol: SPI -ROM socketed: yes -Release year: 2018 diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c deleted file mode 100644 index 6bcbfcc..0000000 --- a/src/mainboard/ocp/tiogapass/bootblock.c +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <intelblocks/pcr.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> -#include <superio/aspeed/ast2400/ast2400.h> -#include <superio/aspeed/common/aspeed.h> -#include <tp_pch_gpio.h> - -/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 -#define ASPEED_CONFIG_INDEX 0x2E -#define ASPEED_CONFIG_DATA 0x2F - -static void enable_espi_lpc_io_windows(void) -{ - /* - * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, - * one is connected to debug header (SUART1) and another is used as SOL (SUART2). - * For that end it is wired into BMC virtual port. - */ - - /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ - pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); - /* LPC I/O enable: com1 and com2 */ - pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); - - /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ - pci_s_write_config32(PCH_DEV_LPC, 0x80, - (1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4)); -} - -static uint8_t com_to_ast_sio(uint8_t com) -{ - switch (com) { - case 0: - return AST2400_SUART1; - case 1: - return AST2400_SUART2; - case 2: - return AST2400_SUART3; - case 4: - return AST2400_SUART4; - default: - return AST2400_SUART1; - } -} - -void bootblock_mainboard_early_init(void) -{ - /* pre-configure Lewisburg PCH GPIO pads */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - - /* Open IO windows */ - enable_espi_lpc_io_windows(); - - /* Configure appropriate physical port of SuperIO chip off BMC */ - const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX, - com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); - aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); - - /* Port 80h direct to GPIO for LED display */ - const pnp_devfn_t gpio_dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO); - aspeed_enable_port80_direct_gpio(gpio_dev, GPIOH); - - /* Enable UART function pin */ - aspeed_enable_uart_pin(serial_dev); -} diff --git a/src/mainboard/ocp/tiogapass/console.c b/src/mainboard/ocp/tiogapass/console.c deleted file mode 100644 index 2cbeb3d..0000000 --- a/src/mainboard/ocp/tiogapass/console.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/uart.h> - -unsigned int get_uart_baudrate(void) -{ - /* SOL console baud rate. */ - return 57600; -} diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb deleted file mode 100644 index fbf0662..0000000 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ /dev/null @@ -1,90 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-or-later - -chip soc/intel/xeon_sp/skx - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # configure device interrupt routing - register "ir00_routing" = "0x3210" # IR00, Dev31 - register "ir01_routing" = "0x3210" # IR01, Dev30 - register "ir02_routing" = "0x3210" # IR02, Dev29 - register "ir03_routing" = "0x3210" # IR03, Dev28 - register "ir04_routing" = "0x3210" # IR04, Dev27 - - # configure interrupt polarity control - register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow - register "ipc1" = "0x00000000" # IPC1 - register "ipc2" = "0x00000000" # IPC2 - register "ipc3" = "0x00000000" # IPC3 - - # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs - # FB production turbo_ratio_limit is 0x1f1f1f2022222325 - register "turbo_ratio_limit" = "0x1b1b1b1d20222325" - # FB production turbo_ratio_limit_cores is 0x1c1812100c080402 - register "turbo_ratio_limit_cores" = "0x1c1814100c080402" - - # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL - register "pstate_req_ratio" = "0xa" - - # configure VTD - register "vtd_support" = "1" - register "coherency_support" = "1" - register "ats_support" = "1" - - register "gen2_dec" = "0x000c0ca1" # IPMI KCS - - device cpu_cluster 0 on end - - device domain 0 on - device gpio 0 alias pch_gpio on end - device pci 00.0 on end # Host bridge - device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.2 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.3 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.4 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.5 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.6 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 04.7 on end # Intel Corporation SkyLake-E CBDMA Registers - device pci 05.0 on end # Intel Corporation SkyLake-E MM/Vt-d Configuration Registers - device pci 05.2 on end # Intel Corporation Device 2025 - device pci 05.4 on end # Intel Corporation Device 2026 - device pci 08.0 on end # Intel Corporation SkyLake-E Ubox Registers - device pci 08.1 on end # Intel Corporation SkyLake-E Ubox Registers - device pci 08.2 on end # Intel Corporation SkyLake-E Ubox Registers - device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0 - device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1 - device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode] - device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller - device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1 - device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2 - device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3 - device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode] - device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1 - device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5 - device pci 1f.0 on - chip drivers/ipmi # BMC KCS - device pnp ca2.0 on end - use pch_gpio as gpio_dev - register "bmc_i2c_address" = "0x20" - register "bmc_boot_timeout" = "90" - register "post_complete_gpio" = "GPP_B20" - register "post_complete_invert" = "1" - end - chip drivers/ipmi/ocp # OCP specific IPMI porting - device pnp ca2.1 on end - end - end # Intel Corporation C621 Series Chipset LPC/eSPI Controller - device pci 1f.1 hidden end # p2sb - device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller - device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus - device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller - end -end diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl deleted file mode 100644 index 06145c4..0000000 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - - -#include <acpi/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 -) -{ - #include <acpi/dsdt_top.asl> - #include "acpi/platform.asl" - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> - #include <cpu/intel/common/acpi/cpu.asl> - #include <soc/intel/xeon_sp/acpi/uncore.asl> - Scope (\_SB.PC00) - { - #include <soc/intel/xeon_sp/acpi/pch.asl> - } -} diff --git a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h b/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h deleted file mode 100644 index b66d773..0000000 --- a/src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SKXSP_TP_IIO_H_ -#define _SKXSP_TP_IIO_H_ - -#include <FspmUpd.h> -#include <soc/pci_devs.h> - -enum tp_iio_bifur_table_index { - Skt0_Iou0 = 0, - Skt0_Iou1, - Skt0_Iou2, - Skt0_Mcp0, - Skt0_Mcp1, - Skt1_Iou0, - Skt1_Iou1, - Skt1_Iou2, - Skt1_Mcp0, - Skt1_Mcp1 -}; - -/* - * Standard Tioga Pass Iio Bifurcation Table - * This is SS 2x16 config. As documented in OCP TP spec, there are - * 3 configs. SS 2x16 is the most common. - * TODO: figure out config through board SKU ID and through PCIe - * config GPIO setting (SLT_CFG0 / SLT_CFG1). - */ -static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = { - { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, /* 1A x16 */ - { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, /* 2A x16 */ - { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, /* 3A x16 */ - { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ - { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ - { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx }, /* no IOU0 */ - { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx }, /* no IOU1 */ - { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, /* 3A x8, 3C x8 */ - { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ - { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ -}; - -#define CFG_UPD_PORT(port, hide) \ - { \ - .PortIndex = port, \ - .HidePort = hide, \ - .DeEmphasis = 0x00, \ - .PortLinkSpeed = PcieAuto, \ - .MaxPayload = 0x00, \ - .DfxDnTxPreset = 0xFF, \ - .DfxRxPreset = 0xFF, \ - .DfxUpTxPreset = 0xFF, \ - .Sris = 0x00, \ - .PcieCommonClock = 0x00, \ - .NtbPpd = NTB_PORT_TRANSPARENT, \ - .NtbSplitBar = 0x00, \ - .NtbBarSizePBar23 = 0x16, \ - .NtbBarSizePBar4 = 0x16, \ - .NtbBarSizePBar5 = 0x16, \ - .NtbBarSizePBar45 = 0x16, \ - .NtbBarSizeSBar23 = 0x16, \ - .NtbBarSizeSBar4 = 0x16, \ - .NtbBarSizeSBar5 = 0x16, \ - .NtbBarSizeSBar45 = 0x16, \ - .NtbSBar01Prefetch = 0x00, \ - .NtbXlinkCtlOverride = 0x03, \ - } - -/* - * Standard Tioga Pass Iio PCIe Port Table - */ -static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = { - CFG_UPD_PORT(PORT_1A, NOT_HIDE), - CFG_UPD_PORT(PORT_1B, HIDE), - CFG_UPD_PORT(PORT_1C, HIDE), - CFG_UPD_PORT(PORT_1D, HIDE), - CFG_UPD_PORT(PORT_2A, NOT_HIDE), - CFG_UPD_PORT(PORT_2B, HIDE), - CFG_UPD_PORT(PORT_2C, HIDE), - CFG_UPD_PORT(PORT_2D, HIDE), - CFG_UPD_PORT(PORT_3A, NOT_HIDE), - CFG_UPD_PORT(PORT_3B, HIDE), - CFG_UPD_PORT(PORT_3C, NOT_HIDE), - CFG_UPD_PORT(PORT_3D, HIDE), -}; - -/* - * Standard Tioga Pass PCH PCIe Port Table - */ -static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[] = { - //PortIndex ; ForceEnable ; PortLinkSpeed - { 0x00, 0x00, PcieAuto }, - { 0x04, 0x00, PcieAuto }, - { 0x05, 0x00, PcieAuto }, -}; - -#endif /* _SKXSP_TP_IIO_H_ */ diff --git a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h deleted file mode 100644 index 59ab3e7..0000000 --- a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h +++ /dev/null @@ -1,543 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef CFG_PCH_GPIO_H -#define CFG_PCH_GPIO_H - -#include <soc/gpio.h> - -/* Pad configuration table for C621 Lewisburg PCH */ -static const struct pad_config gpio_table[] = { - /* ------- GPIO Community 0 ------- */ - /* ------- GPIO Group GPP_A ------- */ - /* GPP_A0 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A0, NONE, DEEP, OFF, DRIVER), - /* GPP_A1 - LAD0 */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - /* GPP_A2 - LAD1 */ - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - /* GPP_A3 - LAD2 */ - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - /* GPP_A4 - LAD3 */ - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - /* GPP_A5 - LFRAME# */ - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - /* GPP_A6 - SERIRQ */ - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - /* GPP_A7 - PIRQA# */ - PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), - /* GPP_A8 - CLKRUN# */ - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - /* GPP_A10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, DEEP, OFF, DRIVER), - /* GPP_A11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, DRIVER), - /* GPP_A12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, DRIVER), - /* GPP_A13 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, DEEP, OFF, DRIVER), - /* GPP_A14 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, DEEP, OFF, DRIVER), - /* GPP_A15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, DRIVER), - /* GPP_A16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A16, NONE, DEEP, OFF, DRIVER), - /* GPP_A17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, DEEP, OFF, DRIVER), - /* GPP_A18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, DEEP, OFF, DRIVER), - /* GPP_A19 - RESERVED */ - /* GPP_A20 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, DEEP, OFF, DRIVER), - /* GPP_A21 - GPIO */ - PAD_CFG_GPO(GPP_A21, 1, DEEP), - /* GPP_A22 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, DRIVER), - /* GPP_A23 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_A23, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Group GPP_B ------- */ - /* GPP_B0 - CORE_VID0 */ - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), - /* GPP_B1 - CORE_VID1 */ - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - /* GPP_B2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, DRIVER), - /* GPP_B3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, DEEP, OFF, DRIVER), - /* GPP_B4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, DRIVER), - /* GPP_B5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, DEEP, OFF, DRIVER), - /* GPP_B6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, DRIVER), - /* GPP_B7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, DRIVER), - /* GPP_B8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, DEEP, OFF, DRIVER), - /* GPP_B9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, DEEP, OFF, DRIVER), - /* GPP_B10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, DRIVER), - /* GPP_B11 - GPIO */ - PAD_CFG_GPO(GPP_B11, 1, DEEP), - /* GPP_B12 - GLB_RST_WARN_N# */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - /* GPP_B13 - PLTRST# */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* GPP_B14 - SPKR */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), - /* GPP_B15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, DRIVER), - /* GPP_B16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, DEEP, OFF, DRIVER), - /* GPP_B17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, DEEP, OFF, DRIVER), - /* GPP_B18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, DEEP, OFF, DRIVER), - /* GPP_B19 - GPIO */ - PAD_CFG_GPO(GPP_B19, 1, DEEP), - /* GPP_B20 - GPIO */ - PAD_CFG_GPO(GPP_B20, 1, DEEP), - /* GPP_B21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, DEEP, OFF, DRIVER), - /* GPP_B22 - GPIO */ - PAD_CFG_GPO(GPP_B22, 0, DEEP), - /* GPP_B23 - PCHHOT# */ - PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2), - - /* ------- GPIO Group GPP_F ------- */ - /* GPP_F0 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, DEEP, OFF, DRIVER), - /* GPP_F1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, DRIVER), - /* GPP_F2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, DEEP, OFF, DRIVER), - /* GPP_F3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, DRIVER), - /* GPP_F4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, DRIVER), - /* GPP_F5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, DEEP, OFF, DRIVER), - /* GPP_F6 - GPIO */ - PAD_CFG_GPO(GPP_F6, 0, PLTRST), - /* GPP_F7 - GPIO */ - PAD_CFG_GPO(GPP_F7, 0, PLTRST), - /* GPP_F8 - GPIO */ - PAD_CFG_GPO(GPP_F8, 0, PLTRST), - /* GPP_F9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, PLTRST, OFF, DRIVER), - /* GPP_F10 - SATA_SCLOCK */ - PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), - /* GPP_F11 - SATA_SLOAD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* GPP_F12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, DRIVER), - /* GPP_F13 - SATA_SDATAOUT2 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* GPP_F14 - SSATA_LED# */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF3), - /* GPP_F15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, DRIVER), - /* GPP_F16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, DRIVER), - /* GPP_F17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, DEEP, OFF, DRIVER), - /* GPP_F18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, DEEP, OFF, DRIVER), - /* GPP_F19 - LAN_SMBCLK */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* GPP_F20 - LAN_SMBDATA */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* GPP_F21 - LAN_SMBALRT# */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* GPP_F22 - SSATA_SCLOCK */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3), - /* GPP_F23 - SSATA_SLOAD */ - PAD_CFG_NF(GPP_F23, NONE, DEEP, NF3), - - /* ------- GPIO Community 1 ------- */ - /* ------- GPIO Group GPP_C ------- */ - /* GPP_C0 - RESERVED */ - /* GPP_C1 - RESERVED */ - /* GPP_C2 - SMBALERT# */ - PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), - /* GPP_C3 - RESERVED */ - /* GPP_C4 - RESERVED */ - /* GPP_C5 - GPIO */ - PAD_CFG_GPO(GPP_C5, 0, DEEP), - /* GPP_C6 - RESERVED */ - /* GPP_C7 - RESERVED */ - /* GPP_C8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, DEEP, OFF, DRIVER), - /* GPP_C9 - GPIO */ - PAD_CFG_GPO(GPP_C9, 1, DEEP), - /* GPP_C10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, EDGE_BOTH, ACPI), - /* GPP_C11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, DEEP, OFF, DRIVER), - /* GPP_C12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, DEEP, OFF, DRIVER), - /* GPP_C13 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, DEEP, OFF, DRIVER), - /* GPP_C14 - GPIO */ - PAD_CFG_GPI_SCI(GPP_C14, NONE, PLTRST, LEVEL, NONE), - /* GPP_C15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, DRIVER), - /* GPP_C16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C16, NONE, DEEP, OFF, DRIVER), - /* GPP_C17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, DEEP, OFF, DRIVER), - /* GPP_C18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, DEEP, OFF, DRIVER), - /* GPP_C19 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, DEEP, OFF, DRIVER), - /* GPP_C20 - RESERVED */ - /* GPP_C21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, DEEP, OFF, DRIVER), - /* GPP_C22 - GPIO */ - PAD_CFG_GPI_SMI(GPP_C22, NONE, PLTRST, LEVEL, NONE), - /* GPP_C23 - GPIO */ - PAD_CFG_GPI_SMI(GPP_C23, NONE, DEEP, LEVEL, INVERT), - - /* ------- GPIO Group GPP_D ------- */ - /* GPP_D0 - GPIO */ - PAD_CFG_GPI_SMI(GPP_D0, NONE, PLTRST, LEVEL, INVERT), - /* GPP_D1 - GPIO */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* GPP_D2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, DRIVER), - /* GPP_D3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, DRIVER), - /* GPP_D4 - GPIO */ - PAD_CFG_GPO(GPP_D4, 1, DEEP), - /* GPP_D5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D5, NONE, DEEP, OFF, DRIVER), - /* GPP_D6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, DRIVER), - /* GPP_D7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, DRIVER), - /* GPP_D8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, DEEP, OFF, DRIVER), - /* GPP_D9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, OFF, DRIVER), - /* GPP_D10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, DRIVER), - /* GPP_D11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, OFF, DRIVER), - /* GPP_D12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, OFF, DRIVER), - /* GPP_D13 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, DEEP, OFF, DRIVER), - /* GPP_D14 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, DEEP, OFF, DRIVER), - /* GPP_D15 - SSATA_SDATAOUT0 */ - PAD_CFG_NF(GPP_D15, NONE, DEEP, NF3), - /* GPP_D16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, DEEP, OFF, DRIVER), - /* GPP_D17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, DRIVER), - /* GPP_D18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, DRIVER), - /* GPP_D19 - GPIO */ - PAD_CFG_GPO(GPP_D19, 1, DEEP), - /* GPP_D20 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, DEEP, OFF, DRIVER), - /* GPP_D21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, DEEP, OFF, DRIVER), - /* GPP_D22 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, DEEP, OFF, DRIVER), - /* GPP_D23 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Group GPP_E ------- */ - /* GPP_E0 - GPIO */ - PAD_CFG_GPI_SMI(GPP_E0, NONE, DEEP, LEVEL, NONE), - /* GPP_E1 - GPIO */ - PAD_CFG_GPI_SMI(GPP_E1, NONE, DEEP, LEVEL, NONE), - /* GPP_E2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, DRIVER), - /* GPP_E3 - CPU_GP0 */ - PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), - /* GPP_E4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, DRIVER), - /* GPP_E5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, DRIVER), - /* GPP_E6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, DRIVER), - /* GPP_E7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, DRIVER), - /* GPP_E8 - SATA_LED# */ - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), - /* GPP_E9 - USB_OC0# */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* GPP_E10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, DRIVER), - /* GPP_E11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, DRIVER), - /* GPP_E12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Community 2 ------- */ - /* -------- GPIO Group GPD -------- */ - /* GPD0 - RESERVED */ - /* GPD1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, RSMRST, OFF, ACPI), - /* GPD2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, RSMRST, OFF, ACPI), - /* GPD3 - PWRBTN# */ - PAD_CFG_NF(GPD3, NONE, RSMRST, NF1), - /* GPD4 - SLP_S3# */ - PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), - /* GPD5 - SLP_S4# */ - PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), - /* GPD6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), - /* GPD7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI), - /* GPD8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), - /* GPD9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, RSMRST, OFF, ACPI), - /* GPD10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPD10, NONE, RSMRST, OFF, ACPI), - /* GPD11 - GBEPHY */ - PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), - - /* ------- GPIO Community 3 ------- */ - /* ------- GPIO Group GPP_I ------- */ - /* GPP_I0 - LAN_TDO */ - PAD_CFG_NF(GPP_I0, NONE, DEEP, NF2), - /* GPP_I1 - LAN_TCK */ - PAD_CFG_NF(GPP_I1, NONE, DEEP, NF2), - /* GPP_I2 - LAN_TMS */ - PAD_CFG_NF(GPP_I2, NONE, DEEP, NF2), - /* GPP_I3 - LAN_TDI */ - PAD_CFG_NF(GPP_I3, NONE, DEEP, NF2), - /* GPP_I4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, DEEP, OFF, DRIVER), - /* GPP_I5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, DEEP, OFF, DRIVER), - /* GPP_I6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, DEEP, OFF, DRIVER), - /* GPP_I7 - LAN_TRST_IN */ - PAD_CFG_NF(GPP_I7, NONE, DEEP, NF2), - /* GPP_I8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, DEEP, OFF, DRIVER), - /* GPP_I9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, DEEP, OFF, DRIVER), - /* GPP_I10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Community 4 ------- */ - /* ------- GPIO Group GPP_J ------- */ - /* GPP_J0 - LAN_LED_P0_0 */ - PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), - /* GPP_J1 - LAN_LED_P0_1 */ - PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), - /* GPP_J2 - LAN_LED_P1_0 */ - PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), - /* GPP_J3 - LAN_LED_P1_1 */ - PAD_CFG_NF(GPP_J3, NONE, DEEP, NF1), - /* GPP_J4 - LAN_LED_P2_0 */ - PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), - /* GPP_J5 - LAN_LED_P2_1 */ - PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), - /* GPP_J6 - LAN_LED_P3_0 */ - PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), - /* GPP_J7 - LAN_LED_P3_1 */ - PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), - /* GPP_J8 - LAN_I2C_SCL_MDC_P0 */ - PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), - /* GPP_J9 - LAN_I2C_SDA_MDIO_P0 */ - PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), - /* GPP_J10 - LAN_I2C_SCL_MDC_P1 */ - PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), - /* GPP_J11 - LAN_I2C_SDA_MDIO_P1 */ - PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), - /* GPP_J12 - LAN_I2C_SCL_MDC_P2 */ - PAD_CFG_NF(GPP_J12, NONE, DEEP, NF1), - /* GPP_J13 - LAN_I2C_SDA_MDIO_P2 */ - PAD_CFG_NF(GPP_J13, NONE, DEEP, NF1), - /* GPP_J14 - LAN_I2C_SCL_MDC_P3 */ - PAD_CFG_NF(GPP_J14, NONE, DEEP, NF1), - /* GPP_J15 - LAN_I2C_SDA_MDIO_P3 */ - PAD_CFG_NF(GPP_J15, NONE, DEEP, NF1), - /* GPP_J16 - LAN_SDP_P0_0 */ - PAD_CFG_NF(GPP_J16, NONE, DEEP, NF1), - /* GPP_J17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_J17, NONE, DEEP, OFF, DRIVER), - /* GPP_J18 - LAN_SDP_P1_0 */ - PAD_CFG_NF(GPP_J18, NONE, DEEP, NF1), - /* GPP_J19 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_J19, NONE, DEEP, OFF, DRIVER), - /* GPP_J20 - LAN_SDP_P2_0 */ - PAD_CFG_NF(GPP_J20, NONE, DEEP, NF1), - /* GPP_J21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_J21, NONE, DEEP, OFF, DRIVER), - /* GPP_J22 - LAN_SDP_P3_0 */ - PAD_CFG_NF(GPP_J22, NONE, DEEP, NF1), - /* GPP_J23 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_J23, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Group GPP_K ------- */ - /* GPP_K0 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, DEEP, OFF, DRIVER), - /* GPP_K1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, DEEP, OFF, DRIVER), - /* GPP_K2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, DEEP, OFF, DRIVER), - /* GPP_K3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, DEEP, OFF, DRIVER), - /* GPP_K4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, DEEP, OFF, DRIVER), - /* GPP_K5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, DEEP, OFF, DRIVER), - /* GPP_K6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, DRIVER), - /* GPP_K7 - RESERVED */ - PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1), - /* GPP_K8 - LAN_NCSI_ARB_IN */ - PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), - /* GPP_K9 - LAN_NCSI_ARB_OUT */ - PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), - /* GPP_K10 - PE_RST# */ - PAD_CFG_NF(GPP_K10, NONE, DEEP, NF1), - - /* ------- GPIO Community 5 ------- */ - /* ------- GPIO Group GPP_G ------- */ - /* GPP_G0 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, DRIVER), - /* GPP_G1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, DRIVER), - /* GPP_G2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, DRIVER), - /* GPP_G3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, DRIVER), - /* GPP_G4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, DEEP, OFF, DRIVER), - /* GPP_G5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, DEEP, OFF, DRIVER), - /* GPP_G6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, DEEP, OFF, DRIVER), - /* GPP_G7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, DRIVER), - /* GPP_G8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G8, NONE, DEEP, OFF, DRIVER), - /* GPP_G9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G9, NONE, DEEP, OFF, DRIVER), - /* GPP_G10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G10, NONE, DEEP, OFF, DRIVER), - /* GPP_G11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, DRIVER), - /* GPP_G12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, DEEP, OFF, DRIVER), - /* GPP_G13 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, DRIVER), - /* GPP_G14 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, DEEP, OFF, DRIVER), - /* GPP_G15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, DEEP, OFF, DRIVER), - /* GPP_G16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, DEEP, OFF, DRIVER), - /* GPP_G17 - ADR_COMPLETE */ - PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), - /* GPP_G18 - NMI# */ - PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), - /* GPP_G19 - SMI# */ - PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), - /* GPP_G20 - RESERVED */ - /* GPP_G21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G21, NONE, DEEP, OFF, DRIVER), - /* GPP_G22 - GPIO */ - PAD_CFG_GPO(GPP_G22, 1, DEEP), - /* GPP_G23 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_G23, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Group GPP_H ------- */ - /* GPP_H0 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, DEEP, OFF, DRIVER), - /* GPP_H1 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, DEEP, OFF, DRIVER), - /* GPP_H2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, DEEP, OFF, DRIVER), - /* GPP_H3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, DEEP, OFF, DRIVER), - /* GPP_H4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, DEEP, OFF, DRIVER), - /* GPP_H5 - RESERVED */ - /* GPP_H6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, DEEP, OFF, DRIVER), - /* GPP_H7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, DEEP, OFF, DRIVER), - /* GPP_H8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, DEEP, OFF, DRIVER), - /* GPP_H9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, DEEP, OFF, DRIVER), - /* GPP_H10 - RESERVED */ - /* GPP_H11 - RESERVED */ - /* GPP_H12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, DEEP, OFF, DRIVER), - /* GPP_H13 - RESERVED */ - /* GPP_H14 - RESERVED */ - /* GPP_H15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, DRIVER), - /* GPP_H16 - RESERVED */ - /* GPP_H17 - RESERVED */ - /* GPP_H18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, DEEP, OFF, DRIVER), - /* GPP_H19 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, DRIVER), - /* GPP_H20 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, DEEP, OFF, DRIVER), - /* GPP_H21 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, DEEP, OFF, DRIVER), - /* GPP_H22 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, DEEP, OFF, DRIVER), - /* GPP_H23 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, DEEP, OFF, DRIVER), - - /* ------- GPIO Group GPP_L ------- */ - /* GPP_L0 - RESERVED */ - /* GPP_L1 - CSME_INTR_OUT */ - PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1), - /* GPP_L2 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, DRIVER), - /* GPP_L3 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, DEEP, OFF, DRIVER), - /* GPP_L4 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L4, NONE, DEEP, OFF, DRIVER), - /* GPP_L5 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, DEEP, OFF, DRIVER), - /* GPP_L6 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, DEEP, OFF, DRIVER), - /* GPP_L7 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L7, NONE, DEEP, OFF, DRIVER), - /* GPP_L8 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L8, NONE, DEEP, OFF, DRIVER), - /* GPP_L9 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L9, NONE, DEEP, OFF, DRIVER), - /* GPP_L10 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L10, NONE, DEEP, OFF, DRIVER), - /* GPP_L11 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L11, NONE, DEEP, OFF, DRIVER), - /* GPP_L12 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L12, NONE, DEEP, OFF, DRIVER), - /* GPP_L13 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L13, NONE, DEEP, OFF, DRIVER), - /* GPP_L14 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L14, NONE, DEEP, OFF, DRIVER), - /* GPP_L15 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L15, NONE, DEEP, OFF, DRIVER), - /* GPP_L16 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L16, NONE, DEEP, OFF, DRIVER), - /* GPP_L17 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L17, NONE, DEEP, OFF, DRIVER), - /* GPP_L18 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L18, NONE, DEEP, OFF, DRIVER), - /* GPP_L19 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_L19, NONE, DEEP, OFF, DRIVER), -}; - -#endif /* CFG_PCH_GPIO_H */ diff --git a/src/mainboard/ocp/tiogapass/ipmi.c b/src/mainboard/ocp/tiogapass/ipmi.c deleted file mode 100644 index e97341b..0000000 --- a/src/mainboard/ocp/tiogapass/ipmi.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <drivers/ipmi/ipmi_if.h> -#include <drivers/ipmi/ipmi_ops.h> -#include <drivers/ipmi/ocp/ipmi_ocp.h> -#include <drivers/vpd/vpd.h> -#include <string.h> - -#include "ipmi.h" -#include "vpd.h" - -void init_frb2_wdt(void) -{ - char val[VPD_LEN]; - /* Enable FRB2 timer by default. */ - u8 enable = 1; - uint16_t countdown; - - if (vpd_get_bool(FRB2_TIMER, VPD_RW_THEN_RO, &enable)) { - if (!enable) { - printk(BIOS_DEBUG, "Disable FRB2 timer\n"); - ipmi_stop_bmc_wdt(CONFIG_BMC_KCS_BASE); - return; - } - } - if (enable) { - if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW_THEN_RO)) { - countdown = (uint16_t)atol(val); - printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d ms\n", - countdown * 100); - } else { - printk(BIOS_DEBUG, "FRB2 timer use default value: %d ms\n", - DEFAULT_COUNTDOWN * 100); - countdown = DEFAULT_COUNTDOWN; - } - ipmi_init_and_start_bmc_wdt(CONFIG_BMC_KCS_BASE, countdown, - TIMEOUT_HARD_RESET); - } -} diff --git a/src/mainboard/ocp/tiogapass/ipmi.h b/src/mainboard/ocp/tiogapass/ipmi.h deleted file mode 100644 index 93101c2..0000000 --- a/src/mainboard/ocp/tiogapass/ipmi.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef TIOGAPASS_IPMI_H -#define TIOGAPASS_IPMI_H -#include <types.h> - -void init_frb2_wdt(void); -#endif diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c deleted file mode 100644 index c69322b..0000000 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ /dev/null @@ -1,182 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <drivers/ipmi/ipmi_ops.h> -#include <drivers/ocp/dmi/ocp_dmi.h> -#include <soc/ramstage.h> - -extern struct fru_info_str fru_strings; - -static const struct port_information SMBIOS_type8_info[] = { - /* - * Port Information fields: - * Internal Reference Designator, - * Internal Connector Type, - * External Reference Designator, - * External Connector_Type, - * Port Type - */ - { - "J7F5 - BMC JTAG HEADER", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - "J8A1 - MINISAS1", - CONN_SAS_SATA, - NULL, - CONN_NONE, - TYPE_SAS - }, - { - "J8A2 - MINISAS2", - CONN_SAS_SATA, - NULL, - CONN_NONE, - TYPE_SAS - }, - { - "J8A3 - SATA CONBINE1", - CONN_SAS_SATA, - NULL, - CONN_NONE, - TYPE_SAS - }, - { - "J8B1 - ME_DBG", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - "J8D1 - VR_DBG", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - "J8E1 - TPM_MODULE", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - "J8F1 - M.2 CONNECTOR", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - "J9A1 - SATA RAID KEY", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - NULL, - CONN_NONE, - "J9A2 - DEBUG 80 PORT", - CONN_OTHER, - TYPE_OTHER_PORT - }, - { - "J9A3 - CPU & PCH XDP", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - NULL, - CONN_NONE, - "J9A5 - USB conn", - CONN_ACCESS_BUS_USB, - TYPE_USB - }, - { - "J9B1 - BMC_DBG", - CONN_OTHER, - NULL, - CONN_NONE, - TYPE_OTHER_PORT - }, - { - NULL, - CONN_NONE, - "J9D1 - USB3.0 TYPE C", - CONN_ACCESS_BUS_USB, - TYPE_USB - }, - { - NULL, - CONN_NONE, - "J9E1 - VGA", - CONN_OTHER, - TYPE_OTHER_PORT - }, - { - NULL, - CONN_NONE, - "JA9G1 - ETH0", - CONN_RJ_45, - TYPE_NETWORK_PORT - }, -}; - -void mainboard_silicon_init_params(FSPS_UPD *params) -{ -} - -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) -{ - int len = 0; - - // add port information - len += smbios_write_type8( - current, handle, - SMBIOS_type8_info, - ARRAY_SIZE(SMBIOS_type8_info) - ); - - return len; -} -#endif - -static void tp_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) -{ - /* OEM string 1 to 6 */ - ocp_oem_smbios_strings(dev, t); - - /* OEM string 7 */ - if (fru_strings.board_info.custom_count > 1 && - *(fru_strings.board_info.board_custom + 1) != NULL) - t->count = smbios_add_oem_string(t->eos, - *(fru_strings.board_info.board_custom + 1)); - else - t->count = smbios_add_oem_string(t->eos, TBF); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->get_smbios_strings = tp_oem_smbios_strings; - read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings); -#if CONFIG(GENERATE_SMBIOS_TABLES) - dev->ops->get_smbios_data = mainboard_smbios_data; -#endif -} - -static void mainboard_final(void *chip_info) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, - .final = mainboard_final, -}; diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c deleted file mode 100644 index d3063c6..0000000 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <fsp/api.h> -#include <FspmUpd.h> -#include <drivers/ipmi/ipmi_if.h> -#include <drivers/ipmi/ocp/ipmi_ocp.h> -#include <soc/romstage.h> -#include <string.h> -#include <gpio.h> -#include <soc/gpio_soc_defs.h> -#include <skxsp_tp_iio.h> - -#include "ipmi.h" - -static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]; - -static void oem_update_iio(FSPM_UPD *mupd) -{ - /* Read GPIO to decide IIO bifurcation at run-time. */ - int slot_config0 = gpio_get(GPP_C15); - int slot_config1 = gpio_get(GPP_C16); - - /* It's a single side 3 slots riser card, to tell which AICs are on each slot requires - reading the GPIO expander PCA9555 via SMBUS, and then configure the bifurcation - accordingly is left for future work. */ - if (!slot_config0 && slot_config1) - mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable[Skt0_Iou0].Bifurcation - = IIO_BIFURCATE_xxx8xxx8; -} - -static void mainboard_config_iio(FSPM_UPD *mupd) -{ - memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table)); - mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable = - (UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf; - mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries = - ARRAY_SIZE(tp_iio_bifur_table); - - mupd->FspmConfig.IioPciConfig.ConfigurationTable = - (UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0; - mupd->FspmConfig.IioPciConfig.NumberOfEntries = - ARRAY_SIZE(tp_iio_pci_port_skt0); - - mupd->FspmConfig.PchPciConfig.PciPortConfig = - (UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0; - mupd->FspmConfig.PchPciConfig.NumberOfEntries = - ARRAY_SIZE(tp_pch_pci_port_skt0); - - mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00; - mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00; - oem_update_iio(mupd); -} - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - /* It's better to run get BMC selftest result first */ - if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { - ipmi_set_post_start(CONFIG_BMC_KCS_BASE); - init_frb2_wdt(); - } - mainboard_config_iio(mupd); - - /* do not configure GPIO controller inside FSP-M */ - mupd->FspmConfig.GpioConfig.GpioTable = NULL; - mupd->FspmConfig.GpioConfig.NumberOfEntries = 0; -} diff --git a/src/mainboard/ocp/tiogapass/vpd.h b/src/mainboard/ocp/tiogapass/vpd.h deleted file mode 100644 index 63a92f6..0000000 --- a/src/mainboard/ocp/tiogapass/vpd.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef TIOGAPASS_VPD_H -#define TIOGAPASS_VPD_H - -/* VPD variable for enabling/disabling FRB2 timer. */ -#define FRB2_TIMER "frb2_timer" -/* VPD variable for setting FRB2 timer countdown value. */ -#define FRB2_COUNTDOWN "frb2_countdown" -#define VPD_LEN 10 -/* Default countdown is 15 minutes. */ -#define DEFAULT_COUNTDOWN 9000 - -#endif /* TIOGAPASS_VPD_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I838b9ea3955d31ea393494c2e726845fe234ef3a Gerrit-Change-Number: 80171 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/rex/var/rex: Set TCC to 100°C
by Subrata Banik (Code Review) 23 Jan '24

23 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Sumeet R Pawnikar, Tarun, yunhao wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79992?usp=email ) Change subject: mb/google/rex/var/rex: Set TCC to 100°C ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79992?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9012984016ab3213102214025d6d8dc07c5d8974 Gerrit-Change-Number: 79992 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yunhao wang <wangyunhao(a)huaqin.corp-partner.google.com> Gerrit-Attention: yunhao wang <wangyunhao(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 23 Jan 2024 06:42:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/rex: Set TCC to 100°C
by Sumeet R Pawnikar (Code Review) 23 Jan '24

23 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, yunhao wang. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), yunhao wang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79992?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rex/var/rex: Set TCC to 100°C ...................................................................... mb/google/rex/var/rex: Set TCC to 100°C Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for rex. BUG=b:270664854 TEST=Build, boot and test on rex with value under sysfs /sys/bus/pci/devices/0000:00:04.0/tcc_offset_degree_celsius Change-Id: I9012984016ab3213102214025d6d8dc07c5d8974 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/79992/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79992?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9012984016ab3213102214025d6d8dc07c5d8974 Gerrit-Change-Number: 79992 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yunhao wang <wangyunhao(a)huaqin.corp-partner.google.com> Gerrit-Attention: yunhao wang <wangyunhao(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Set TCC to 100°C
by Sumeet R Pawnikar (Code Review) 23 Jan '24

23 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, yunhao wang. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79992?usp=email ) Change subject: soc/intel/meteorlake: Set TCC to 100°C ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79992/comment/6f168e28_8ee1d6e7 : PS1, Line 9: Set tcc_offset value to 10 in devicetree for Thermal Control : Circuit (TCC) activation feature for rex. > > We are seeing the same issue on Screebo mentioned on this bug. […] as per the response received from ODM on bug: b:309569030#comment13, not planning to change tcc_offset for Screebo. I suggest to change this tcc_offset for Rex variant and going to submit patch set #3 now with bug details. Rex ODM is aligned with this change as per bug b:270664854#comment54 File src/soc/intel/meteorlake/chipset.cb: https://review.coreboot.org/c/coreboot/+/79992/comment/af8c28e1_4d545918 : PS2, Line 30: register "tcc_offset" = "10" > note: tcc_offset value for Ovis, Karis etc as part of the override now matches with `10` hence, you […] No need this change for Ovis and Karis. Checked with Screebo ODM and not changing this as per bug b:309569030#comment13 -- To view, visit https://review.coreboot.org/c/coreboot/+/79992?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9012984016ab3213102214025d6d8dc07c5d8974 Gerrit-Change-Number: 79992 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yunhao wang <wangyunhao(a)huaqin.corp-partner.google.com> Gerrit-Attention: yunhao wang <wangyunhao(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 23 Jan 2024 06:06:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Move cnvi to overridetree
by Shelley Chen (Code Review) 23 Jan '24

23 Jan '24

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79898?usp=email ) Change subject: mb/google/brox: Move cnvi to overridetree ...................................................................... mb/google/brox: Move cnvi to overridetree We need to disable the cnvi device when pcie wifi is enabled, so need to use the FW_CONFIG defined in the overridetree for this. BUG=b:311450057,b:300690448,b:319188820 BRANCH=None TEST=This will be tested on the device when received Change-Id: If9e861db37e321fd69c09f9b4aafa2e212f92caa Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79898 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brox/variants/brox/overridetree.cb 2 files changed, 9 insertions(+), 7 deletions(-) Approvals: Nick Vaccaro: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 5589bbe..fd2c8ed 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -161,13 +161,6 @@ device ref tcss_dma1 on end device ref xhci on end device ref shared_sram on end - device ref cnvi_wifi on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - register "add_acpi_dma_property" = "true" - device generic 0 on end - end - end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index dc18663..af7c84c 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -195,6 +195,15 @@ end probe WIFI WIFI_PCIE end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + probe WIFI WIFI_CNVI + end device ref ish on chip drivers/intel/ish register "add_acpi_dma_property" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/79898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9e861db37e321fd69c09f9b4aafa2e212f92caa Gerrit-Change-Number: 79898 Gerrit-PatchSet: 19 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/brox: Enable WLAN on root port 5
by Shelley Chen (Code Review) 23 Jan '24

23 Jan '24

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79888?usp=email ) Change subject: mb/google/brox: Enable WLAN on root port 5 ...................................................................... mb/google/brox: Enable WLAN on root port 5 BUG=b:311450057,b:300690448,b:319188820 BRANCH=None TEST=test on device with lspci & make sure can see the Intel Network controller Change-Id: I361bef13ebd073b6fccb729a1960d3832cf2681a Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79888 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brox/variants/brox/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index 1962279..dc18663 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -181,6 +181,20 @@ }" probe STORAGE STORAGE_NVME end + device ref pcie_rp5 on + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "1" + device generic 0 on end + end + probe WIFI WIFI_PCIE + end device ref ish on chip drivers/intel/ish register "add_acpi_dma_property" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/79888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I361bef13ebd073b6fccb729a1960d3832cf2681a Gerrit-Change-Number: 79888 Gerrit-PatchSet: 18 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/brox: Move cnvi to overridetree
by Nick Vaccaro (Code Review) 23 Jan '24

23 Jan '24

Attention is currently required from: Shelley Chen. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79898?usp=email ) Change subject: mb/google/brox: Move cnvi to overridetree ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9e861db37e321fd69c09f9b4aafa2e212f92caa Gerrit-Change-Number: 79898 Gerrit-PatchSet: 18 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Tue, 23 Jan 2024 04:47:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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