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Subrata Banik has uploaded a new patch set (#8) to the change originally created by Shelley Chen. ( https://review.coreboot.org/c/coreboot/+/79775?usp=email )
The following approvals got outdated and were removed:
Code-Review+1 by Subrata Banik, Verified+1 by build bot (Jenkins)
Change subject: Choose Correct FW splash screen at runtime
......................................................................
Choose Correct FW splash screen at runtime
This CL uses the factory config that is retrieved by the TPM in order
to determine if the device is a chromebook or a chromebook plus device
at runtime. From this it will dynamically choose the correct FW
splash screen to display at boot time.
This CL also introduces three new Kconfigs:
CHROMEOS_FW_SPLASH_SCREEN
CB_LOGO_PATH
CB_PLUS_LOGO_PATH
which allow users to enable the fw splash screen feature in the
vendorcode. Previously, we were using the BMP_LOGO Kconfig in
drivers/intel/fsp2_0, but we didn't want the top level Kconfigs to be
located inside the architecture specific files.
BUG=b:317880956
BRANCH=None
TEST=emerge-rex coreboot chromeos-bootimage
verify that FW splash screen appears
Change-Id: I56613d1e7e81e25b31ad034edae0f716c94c4960
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/drivers/intel/fsp2_0/Makefile.inc
M src/include/bootsplash.h
M src/lib/Kconfig
M src/lib/bmp_logo.c
M src/vendorcode/google/chromeos/Kconfig
M src/vendorcode/google/chromeos/Makefile.inc
A src/vendorcode/google/chromeos/splash.c
7 files changed, 68 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/79775/8
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Change subject: mb/intel/mtlrvp: define a new config for Chrome EC
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
Can someone please approve the changes.
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Change subject: soc/mediatek: Add common implmentation to configure display
......................................................................
Patch Set 2:
(1 comment)
File src/soc/mediatek/common/display.c:
https://review.coreboot.org/c/coreboot/+/79776/comment/20cba7f8_4bbaabed :
PS1, Line 42: if (panel->get_edid && panel->get_edid(panel) < 0)
> > And s can also be removed from panel. […]
I think we just need a local variable to store panel_serializable_data.
```
struct edid edid;
if (DISP_PATH_EDP) {
...
} else {
panel_serializable_data mipi_data = {0};
if (panel->get_edid) {
panel->get_edid(panel, &edid); // Fills edid
} else {
get_mipi_panel_from_cbfs(&mipi_data);
edid = mipi_data.edid; // Or use pointer
}
mtk_dsi_init(..., mipi_data->init);
}
```
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Change subject: soc/mediatek: Add common implmentation to configure display
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/geralt/panel.h:
https://review.coreboot.org/c/coreboot/+/79776/comment/8aecc54f_6736e923 :
PS1, Line 23: struct panel_description *get_active_panel(void);
> If so, do you suggest passing `struct panel_description panl` to `mtk_display_init` (configure_displ […]
That's a good question. I admit I didn't think of that. For now, I have no strong opinion, so I'm fine with your existing patchset. It's up to you (if the declaration is kept here, then I think we'll need to pass `panel` to `mtk_display_init()`).
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Change subject: soc/mediatek: Add common implmentation to configure display
......................................................................
Patch Set 2:
(1 comment)
File src/soc/mediatek/common/display.c:
https://review.coreboot.org/c/coreboot/+/79776/comment/21ebe970_335086bc :
PS1, Line 42: if (panel->get_edid && panel->get_edid(panel) < 0)
> And s can also be removed from panel.
I think we still need `s` for `mtk_dsi_init()`.
In MIPI panel cases, `s->init` is retrieved from CBFS.
In eDP bridge cases, `s->init` is initialized as NULL.
`mtk_dsi_init()` will call `mipi_panel_parse_init_commands()` depending on the value of `s->init`.
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Change subject: Resolve GPI/GPIO dysphoria
......................................................................
Patch Set 6: Code-Review-1
(2 comments)
Patchset:
PS6:
GPIO is often how this is referred to in the datasheet.
File src/southbridge/intel/ibexpeak/pch.h:
https://review.coreboot.org/c/coreboot/+/67919/comment/efc2e96f_c97a09ae :
PS6, Line 112: GPIO_ROUT
This is actually how the registers is called in datasheet.
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Change subject: mb/ibm/sbp1: Set FSP loglevel
......................................................................
Patch Set 2: Code-Review+2
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