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Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80239?usp=email )
Change subject: include/device/device.h: Remove CHIP_NAME() macro
......................................................................
Patch Set 3: Code-Review+1
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Attention is currently required from: Ashish Kumar Mishra, Jérémy Compostella, Paul Menzel, Subrata Banik, Wonkyu Kim.
Hello Arthur Heymans, Jérémy Compostella, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80088?usp=email
to look at the new patch set (#6).
Change subject: cpu/x86: Add 1GiB pages for memory access up to 512GiB
......................................................................
cpu/x86: Add 1GiB pages for memory access up to 512GiB
Current pagetable implementation allows memory access up to 4GiB using
2MiB pages. If user wants to access more than 4GiB with a 2MiB page it
will require more pagetable entries. By using a 1GiB page table, users
can access more than 4GiB of memory while reducing the number of
pagetable entries. This patch enables memory access up to 512GiB through
1GiB pages by selecting USE_1G_PAGES_TLB in Kconfig.
TEST: Verified in 64bit mode boot and access above 4GiB
Change-Id: Id569ae5b50abf5b72e4db33b5e4cd802399e76ec
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
---
M src/cpu/x86/64bit/Makefile.mk
A src/cpu/x86/64bit/pt1G.S
M src/cpu/x86/Kconfig
3 files changed, 43 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/80088/6
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78330?usp=email )
Change subject: device/device.h: Rename busses for clarity
......................................................................
Patch Set 25: -Code-Review
(1 comment)
File src/device/root_device.c:
https://review.coreboot.org/c/coreboot/+/78330/comment/f7d94b79_c1f1c56d :
PS24, Line 89: if (dev_root.downstream)
: scan_bridges(bus->downstream);
> culprit...
Done. Things work fine now
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Attention is currently required from: Angel Pons, Caveh Jalali, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Felix Held, Forest Mittelberg, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Jason Nien, Jeff Daly, Jincheng Li, Johnny Lin, Jérémy Compostella, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Varshit Pandya, Werner Zeh.
Hello Angel Pons, Caveh Jalali, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Felix Held, Forest Mittelberg, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Jason Nien, Jeff Daly, Jincheng Li, Johnny Lin, Jérémy Compostella, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Varshit Pandya, Werner Zeh, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78330?usp=email
to look at the new patch set (#25).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: device/device.h: Rename busses for clarity
......................................................................
device/device.h: Rename busses for clarity
This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
---
M src/acpi/acpi.c
M src/acpi/device.c
M src/arch/x86/mpspec.c
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/device/cardbus_device.c
M src/device/device.c
M src/device/device_const.c
M src/device/device_util.c
M src/device/i2c_bus.c
M src/device/mdio.c
M src/device/oprom/realmode/x86.c
M src/device/oprom/realmode/x86_interrupts.c
M src/device/oprom/yabel/device.c
M src/device/oprom/yabel/interrupt.c
M src/device/pci_device.c
M src/device/pci_rom.c
M src/device/pciexp_device.c
M src/device/pcix_device.c
M src/device/pnp_device.c
M src/device/resource_allocator_v4.c
M src/device/root_device.c
M src/drivers/i2c/ptn3460/ptn3460.c
M src/drivers/intel/dptf/dptf.c
M src/drivers/intel/ish/ish.c
M src/drivers/intel/mipi_camera/camera.c
M src/drivers/intel/soundwire/soundwire.c
M src/drivers/net/phy/m88e1512/m88e1512.c
M src/drivers/net/r8168.c
M src/drivers/nxp/uwb/uwb.c
M src/drivers/pcie/generic/generic.c
M src/drivers/spi/acpi/acpi.c
M src/drivers/usb/hub/acpi.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/smbios.c
M src/drivers/wwan/fm/acpi_fm350gl.c
M src/ec/google/chromeec/ec_acpi.c
M src/include/device/device.h
M src/include/device/pci_ops.h
M src/lib/smbios.c
M src/mainboard/aopen/dxplplusu/acpi_tables.c
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/google/brox/mainboard.c
M src/mainboard/google/brya/mainboard.c
M src/mainboard/google/kahlee/variants/careena/mainboard.c
M src/mainboard/google/kahlee/variants/treeya/audio.c
M src/mainboard/google/octopus/mainboard.c
M src/mainboard/google/rex/mainboard.c
M src/mainboard/google/zork/variants/baseboard/ramstage_common.c
M src/mainboard/ibase/mb899/mptable.c
M src/mainboard/kontron/986lcd-m/mptable.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/mainboard/roda/rk9/ti_pci7xx1.c
M src/mainboard/siemens/fa_ehl/mainboard.c
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/e7505/northbridge.c
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/pineview/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/northbridge.c
M src/soc/amd/cezanne/xhci.c
M src/soc/amd/common/block/acpi/ivrs.c
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/genoa_poc/domain.c
M src/soc/amd/glinda/xhci.c
M src/soc/amd/mendocino/xhci.c
M src/soc/amd/phoenix/xhci.c
M src/soc/amd/picasso/xhci.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/cavium/cn81xx/ecam0.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/common/block/acpi/pep.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
M src/soc/intel/common/block/usb4/pcie.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/meteorlake/fsp_params.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/skx/soc_acpi.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/uncore.c
M src/soc/intel/xeon_sp/uncore_acpi.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/superio/common/generic.c
M src/superio/common/ssdt.c
M src/superio/nuvoton/npcd378/superio.c
M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c
M util/sconfig/main.c
104 files changed, 343 insertions(+), 348 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/78330/25
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Change subject: device/device.h: Rename busses for clarity
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Patch Set 24:
(1 comment)
File src/device/root_device.c:
https://review.coreboot.org/c/coreboot/+/78330/comment/9e85bb83_8cd15b20 :
PS24, Line 89: if (dev_root.downstream)
: scan_bridges(bus->downstream);
culprit...
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Change subject: include/device/device.h: Remove CHIP_NAME() macro
......................................................................
Patch Set 3:
(1 comment)
File src/southbridge/intel/i82801dx/i82801dx.c:
https://review.coreboot.org/c/coreboot/+/80239/comment/f84ec537_5cc9f013 :
PS1, Line 68:
> would you like to take the chance to fix this indentation?
That's a bit too ugly, fixed it. 👍
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Change subject: device/device.h: Rename busses for clarity
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Patch Set 24: Code-Review-2
(1 comment)
Patchset:
PS24:
This seems to break some boards. I'll try not changing the order of things in the struct and see where binary changes.
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Attention is currently required from: Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nicholas Sudsgaard, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, ron minnich.
Hello Alexander Couzens, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Dinesh Gehlot, Eran Mitrani, Felix Held, Forest Mittelberg, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Jeremy Soller, Johnny Lin, Julius Werner, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nicholas Chin, Nick Vaccaro, Philipp Hug, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Crawford, Vanessa Eusebio, Werner Zeh, Xi Chen, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80239?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Code-Review+1 by Yidi Lin, Verified+1 by build bot (Jenkins)
Change subject: include/device/device.h: Remove CHIP_NAME() macro
......................................................................
include/device/device.h: Remove CHIP_NAME() macro
Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M src/cpu/amd/pi/00730F01/chip_name.c
M src/cpu/intel/haswell/acpi.c
M src/cpu/intel/model_1067x/model_1067x_init.c
M src/cpu/intel/model_2065x/acpi.c
M src/cpu/intel/model_206ax/acpi.c
M src/cpu/intel/slot_1/slot_1.c
M src/cpu/power9/power9.c
M src/cpu/qemu-power8/qemu.c
M src/cpu/qemu-x86/qemu.c
M src/drivers/acpi/thermal_zone/thermal_zone.c
M src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c
M src/drivers/crb/tis.c
M src/drivers/generic/adau7002/adau7002.c
M src/drivers/generic/alc1015/alc1015.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/generic/gpio_keys/gpio_keys.c
M src/drivers/generic/max98357a/max98357a.c
M src/drivers/generic/nau8315/nau8315.c
M src/drivers/genesyslogic/gl9750/gl9750.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/gfx/generic/generic.c
M src/drivers/i2c/at24rf08c/at24rf08c.c
M src/drivers/i2c/ck505/ck505.c
M src/drivers/i2c/cs35l53/cs35l53.c
M src/drivers/i2c/cs42l42/cs42l42.c
M src/drivers/i2c/da7219/da7219.c
M src/drivers/i2c/generic/generic.c
M src/drivers/i2c/gpiomux/bus/bus.c
M src/drivers/i2c/gpiomux/mux/mux.c
M src/drivers/i2c/hid/hid.c
M src/drivers/i2c/lm96000/lm96000.c
M src/drivers/i2c/max98373/max98373.c
M src/drivers/i2c/max98390/max98390.c
M src/drivers/i2c/max98396/max98396.c
M src/drivers/i2c/max98927/max98927.c
M src/drivers/i2c/nau8825/nau8825.c
M src/drivers/i2c/nct7802y/nct7802y.c
M src/drivers/i2c/pca9538/pca9538.c
M src/drivers/i2c/pcf8523/pcf8523.c
M src/drivers/i2c/pi608gp/pi608gp.c
M src/drivers/i2c/ptn3460/ptn3460.c
M src/drivers/i2c/rt1011/rt1011.c
M src/drivers/i2c/rt5663/rt5663.c
M src/drivers/i2c/rtd2132/rtd2132.c
M src/drivers/i2c/rv3028c7/rv3028c7.c
M src/drivers/i2c/rx6110sa/rx6110sa.c
M src/drivers/i2c/sx9310/sx9310.c
M src/drivers/i2c/sx9324/sx9324.c
M src/drivers/i2c/sx9360/sx9360.c
M src/drivers/i2c/tas5825m/tas5825m.c
M src/drivers/i2c/tpm/chip.c
M src/drivers/intel/dptf/dptf.c
M src/drivers/intel/ish/ish.c
M src/drivers/intel/mipi_camera/camera.c
M src/drivers/intel/pmc_mux/conn/conn.c
M src/drivers/intel/pmc_mux/mux.c
M src/drivers/intel/soundwire/soundwire.c
M src/drivers/intel/usb4/retimer/retimer.c
M src/drivers/ipmi/ipmi_kcs_ops.c
M src/drivers/ipmi/ocp/ipmi_ocp.c
M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c
M src/drivers/net/atl1e.c
M src/drivers/net/phy/m88e1512/m88e1512.c
M src/drivers/net/r8168.c
M src/drivers/nxp/uwb/uwb.c
M src/drivers/pc80/tpm/tis.c
M src/drivers/pcie/generic/generic.c
M src/drivers/pcie/rtd3/device/chip.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/secunet/dmi/smbios.c
M src/drivers/sof/sof.c
M src/drivers/soundwire/alc1308/alc1308.c
M src/drivers/soundwire/alc5682/alc5682.c
M src/drivers/soundwire/alc711/alc711.c
M src/drivers/soundwire/cs42l42/cs42l42.c
M src/drivers/soundwire/max98363/max98363.c
M src/drivers/soundwire/max98373/max98373.c
M src/drivers/spi/acpi/acpi.c
M src/drivers/uart/acpi/acpi.c
M src/drivers/usb/acpi/usb_acpi.c
M src/drivers/usb/hub/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wwan/fm/acpi_fm350gl.c
M src/ec/51nb/npce985la0dx/npce985la0dx.c
M src/ec/clevo/it5570e/ec.c
M src/ec/compal/ene932/ec.c
M src/ec/dell/mec5035/mec5035.c
M src/ec/google/chromeec/audio_codec/audio_codec.c
M src/ec/google/chromeec/ec_lpc.c
M src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c
M src/ec/google/chromeec/mux/conn/conn.c
M src/ec/google/chromeec/mux/mux.c
M src/ec/google/wilco/chip.c
M src/ec/hp/kbc1126/ec.c
M src/ec/kontron/it8516e/ec.c
M src/ec/kontron/kempld/kempld.c
M src/ec/lenovo/h8/h8.c
M src/ec/lenovo/pmh7/pmh7.c
M src/ec/quanta/ene_kb3940q/ec.c
M src/ec/quanta/it8518/ec.c
M src/ec/roda/it8518/ec.c
M src/ec/smsc/mec1308/ec.c
M src/ec/starlabs/merlin/ite.c
M src/ec/starlabs/merlin/nuvoton.c
M src/include/device/device.h
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/supermicro/x10slm-f/mainboard.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/e7505/northbridge.c
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/northbridge.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/x4x/northbridge.c
M src/soc/amd/cezanne/chip.c
M src/soc/amd/genoa_poc/chip.c
M src/soc/amd/glinda/chip.c
M src/soc/amd/mendocino/chip.c
M src/soc/amd/phoenix/chip.c
M src/soc/amd/picasso/chip.c
M src/soc/amd/stoneyridge/chip.c
M src/soc/cavium/cn81xx/soc.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/chip.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/baytrail/chip.c
M src/soc/intel/braswell/chip.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/pch.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/pcie.c
M src/soc/intel/denverton_ns/chip.c
M src/soc/intel/elkhartlake/chip.c
M src/soc/intel/jasperlake/chip.c
M src/soc/intel/meteorlake/chip.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/tigerlake/chip.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/skx/chip.c
M src/soc/intel/xeon_sp/spr/chip.c
M src/soc/mediatek/mt8173/soc.c
M src/soc/mediatek/mt8183/soc.c
M src/soc/mediatek/mt8186/soc.c
M src/soc/mediatek/mt8188/soc.c
M src/soc/mediatek/mt8192/soc.c
M src/soc/mediatek/mt8195/soc.c
M src/soc/nvidia/tegra124/soc.c
M src/soc/nvidia/tegra210/soc.c
M src/soc/qualcomm/ipq40xx/soc.c
M src/soc/qualcomm/ipq806x/soc.c
M src/soc/qualcomm/qcs405/soc.c
M src/soc/qualcomm/sc7180/soc.c
M src/soc/qualcomm/sc7280/soc.c
M src/soc/rockchip/rk3288/soc.c
M src/soc/rockchip/rk3399/soc.c
M src/soc/samsung/exynos5250/cpu.c
M src/soc/samsung/exynos5420/cpu.c
M src/soc/sifive/fu540/chip.c
M src/soc/ti/am335x/soc.c
M src/soc/ucb/riscv/chip.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/i82371eb/i82371eb.c
M src/southbridge/intel/i82801dx/i82801dx.c
M src/southbridge/intel/i82801gx/i82801gx.c
M src/southbridge/intel/i82801ix/i82801ix.c
M src/southbridge/intel/i82801jx/i82801jx.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/pch.c
M src/southbridge/intel/lynxpoint/pch.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/southbridge/ti/pci7420/cardbus.c
M src/superio/aspeed/ast2400/superio.c
M src/superio/common/generic.c
M src/superio/fintek/f71808a/superio.c
M src/superio/fintek/f71859/superio.c
M src/superio/fintek/f71863fg/superio.c
M src/superio/fintek/f71869ad/superio.c
M src/superio/fintek/f81803a/superio.c
M src/superio/fintek/f81865f/superio.c
M src/superio/fintek/f81866d/superio.c
M src/superio/ite/it8528e/superio.c
M src/superio/ite/it8613e/superio.c
M src/superio/ite/it8623e/superio.c
M src/superio/ite/it8712f/superio.c
M src/superio/ite/it8718f/superio.c
M src/superio/ite/it8720f/superio.c
M src/superio/ite/it8721f/superio.c
M src/superio/ite/it8728f/superio.c
M src/superio/ite/it8772f/superio.c
M src/superio/ite/it8783ef/superio.c
M src/superio/ite/it8784e/superio.c
M src/superio/ite/it8786e/superio.c
M src/superio/nsc/pc87382/superio.c
M src/superio/nsc/pc87384/superio.c
M src/superio/nsc/pc87392/superio.c
M src/superio/nsc/pc87417/superio.c
M src/superio/nuvoton/nct5104d/superio.c
M src/superio/nuvoton/nct5539d/superio.c
M src/superio/nuvoton/nct5572d/superio.c
M src/superio/nuvoton/nct6687d/superio.c
M src/superio/nuvoton/nct6776/superio.c
M src/superio/nuvoton/nct6779d/superio.c
M src/superio/nuvoton/nct6791d/superio.c
M src/superio/nuvoton/npcd378/superio.c
M src/superio/nuvoton/wpcm450/superio.c
M src/superio/renesas/m3885x/superio.c
M src/superio/smsc/fdc37n972/superio.c
M src/superio/smsc/kbc1100/superio.c
M src/superio/smsc/lpc47m10x/superio.c
M src/superio/smsc/lpc47m15x/superio.c
M src/superio/smsc/lpc47n217/superio.c
M src/superio/smsc/lpc47n227/superio.c
M src/superio/smsc/mec1308/superio.c
M src/superio/smsc/sch5545/superio.c
M src/superio/smsc/sch555x/ramstage.c
M src/superio/smsc/sio1036/superio.c
M src/superio/smsc/sio10n268/superio.c
M src/superio/smsc/smscsuperio/superio.c
M src/superio/winbond/w83627dhg/superio.c
M src/superio/winbond/w83627ehg/superio.c
M src/superio/winbond/w83627hf/superio.c
M src/superio/winbond/w83627thg/superio.c
M src/superio/winbond/w83627uhg/superio.c
M src/superio/winbond/w83667hg-a/superio.c
M src/superio/winbond/w83977tf/superio.c
M src/superio/winbond/wpcd376i/superio.c
M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c
236 files changed, 238 insertions(+), 239 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/80239/3
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Attention is currently required from: Angel Pons, Caveh Jalali, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Felix Held, Forest Mittelberg, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Jason Nien, Jeff Daly, Jincheng Li, Johnny Lin, Jérémy Compostella, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Varshit Pandya, Werner Zeh.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78330?usp=email )
Change subject: device/device.h: Rename busses for clarity
......................................................................
Patch Set 24:
(1 comment)
Patchset:
PS23:
> would be good if you can rebase this one to see if it still works, since i'm not sure if there have been any changes in the meantime that would result in breakage in combination with this patch. when that's done, i'll +2
Done. Let's see if Jenkins is happy.
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Gerrit-Comment-Date: Tue, 30 Jan 2024 08:58:05 +0000
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Attention is currently required from: Christian Walter, Felix Held, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80091?usp=email )
Change subject: soc/intel/xeon_sp: Attach more stacks
......................................................................
Patch Set 6: Code-Review+2
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Gerrit-Project: coreboot
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