coreboot-gerrit January 2024

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[XS] Change in coreboot[main]: mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock
by Tyler Wang (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Paul Menzel, Subrata Banik, Sumeet R Pawnikar, Tarun. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80000?usp=email ) Change subject: mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80000/comment/e9dda004_1e2532d0 : PS5, Line 10: Set SOC_TCHSCR_RST to output low in bootblock. > It's related to CB:79571. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Gerrit-Change-Number: 80000 Gerrit-PatchSet: 7 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Jan 2024 12:34:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/rex/var/karis: Toggle NVMe PWR pin to reset SSD
by Felix Held (Code Review) 30 Jan '24

30 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80213?usp=email ) Change subject: mb/google/rex/var/karis: Toggle NVMe PWR pin to reset SSD ...................................................................... mb/google/rex/var/karis: Toggle NVMe PWR pin to reset SSD Follow reference design rex0, toggles NVMe PWR pin as soon as in early stage to make NVMe ready sooner. BUG=none TEST=Build karis and try warm reboot from OS console. Check the DUT with WD SSD boots to OS again. Change-Id: I24a702f02278355c4f2137f0d05c8a9da7cb3c1c Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80213 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/karis/gpio.c 1 file changed, 8 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/karis/gpio.c b/src/mainboard/google/rex/variants/karis/gpio.c index 69921a8..8c0f929 100644 --- a/src/mainboard/google/rex/variants/karis/gpio.c +++ b/src/mainboard/google/rex/variants/karis/gpio.c @@ -367,6 +367,11 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 1, DEEP), + /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ @@ -393,9 +398,6 @@ /* GPP_E13 : [] ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* GPP_A20 : [] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_A20, 0, DEEP), - /* GPP_H10 : [] ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), @@ -404,6 +406,9 @@ }; static const struct pad_config romstage_gpio_table[] = { + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* GPP_B11 : [] ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* A20 : [] ==> SSD_PERST_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24a702f02278355c4f2137f0d05c8a9da7cb3c1c Gerrit-Change-Number: 80213 Gerrit-PatchSet: 7 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: MAINTAINERS: Add Sapphire Rapids FSP headers into scope of INTEL Xeon...
by Lean Sheng Tan (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held, Patrick Rudolph, Paul Menzel, Shuo Liu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80241?usp=email ) Change subject: MAINTAINERS: Add Sapphire Rapids FSP headers into scope of INTEL Xeon Sacalable Processor Family ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20ad4bc325d5cfe7a9d5f8b349eeea3d6218452b Gerrit-Change-Number: 80241 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 30 Jan 2024 12:29:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Update maintainers list for INTEL Xeon Scalable Processo...
by Lean Sheng Tan (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held, Patrick Rudolph, Paul Menzel, Shuo Liu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80240?usp=email ) Change subject: MAINTAINERS: Update maintainers list for INTEL Xeon Scalable Processor Family ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide3aa87fca69be6b0f1ffe0b18d7ffb410e5c563 Gerrit-Change-Number: 80240 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 30 Jan 2024 12:28:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/geralt: Increase VM18 LDO voltage to 1.9V for Ciri
by Felix Held (Code Review) 30 Jan '24

30 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80198?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/geralt: Increase VM18 LDO voltage to 1.9V for Ciri ...................................................................... mb/google/geralt: Increase VM18 LDO voltage to 1.9V for Ciri The current panel voltage measured at mainboard side is 1.79V and the voltage at panel side is 1.74V. Since the panel requires 1.8V or more, increase the circuit voltage to 1.9V to meet the panel requirement. After adjustment mainboard side voltage is 1.89V and panel side is 1.84V. BUG=b:322080023 TEST=Check ciri vm18 ldo voltage BRANCH=None Change-Id: I6d6193d45409f53c0b656890c44ddaef253c5e01 Signed-off-by: Cong Yang <yangcong5(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80198 Reviewed-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/geralt/panel_ciri.c M src/mainboard/google/geralt/regulator.c 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Ruihai Zhou: Looks good to me, but someone else must approve Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/geralt/panel_ciri.c b/src/mainboard/google/geralt/panel_ciri.c index 3d01183..4d31711 100644 --- a/src/mainboard/google/geralt/panel_ciri.c +++ b/src/mainboard/google/geralt/panel_ciri.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <soc/i2c.h> +#include <soc/regulator.h> #include "gpio.h" #include "panel.h" @@ -23,6 +24,7 @@ .settings = reg_settings, .setting_counts = ARRAY_SIZE(reg_settings), }; + mainboard_set_regulator_voltage(MTK_REGULATOR_VDD18, 1900000); power_on_mipi_panel(&cfg); } diff --git a/src/mainboard/google/geralt/regulator.c b/src/mainboard/google/geralt/regulator.c index f3b4407..8f0d7cb 100644 --- a/src/mainboard/google/geralt/regulator.c +++ b/src/mainboard/google/geralt/regulator.c @@ -38,6 +38,8 @@ if (id == MT6359P_SIM1) mt6359p_set_vsim1_voltage(voltage_uv); + else if (id == MT6359P_VM18) + mt6359p_set_vm18_voltage(voltage_uv); else mt6359p_buck_set_voltage(id, voltage_uv); } -- To view, visit https://review.coreboot.org/c/coreboot/+/80198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d6193d45409f53c0b656890c44ddaef253c5e01 Gerrit-Change-Number: 80198 Gerrit-PatchSet: 7 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: MAINTAINERS: Add Sapphire Rapids FSP headers into scope of INTEL Xeon...
by Shuo Liu (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: Lean Sheng Tan, Patrick Rudolph. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80241?usp=email ) Change subject: MAINTAINERS: Add Sapphire Rapids FSP headers into scope of INTEL Xeon Sacalable Processor Family ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Leansheng, could you please add others for review? -- To view, visit https://review.coreboot.org/c/coreboot/+/80241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20ad4bc325d5cfe7a9d5f8b349eeea3d6218452b Gerrit-Change-Number: 80241 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 30 Jan 2024 12:27:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: security/intel: Use write{64,32,16,8}p and read{64,32,16,8}p
by Felix Held (Code Review) 30 Jan '24

30 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80194?usp=email ) Change subject: security/intel: Use write{64,32,16,8}p and read{64,32,16,8}p ...................................................................... security/intel: Use write{64,32,16,8}p and read{64,32,16,8}p Change-Id: I4bdfcd0cc0e2d9b5f884ea7275659c12488715e0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80194 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/security/intel/txt/common.c M src/security/intel/txt/logging.c M src/security/intel/txt/ramstage.c M src/security/intel/txt/romstage.c M src/security/intel/txt/txtlib.c 5 files changed, 57 insertions(+), 57 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index b78394a..6fba958 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -100,7 +100,7 @@ void intel_txt_log_spad(void) { - const uint64_t acm_status = read64((void *)TXT_SPAD); + const uint64_t acm_status = read64p(TXT_SPAD); printk(BIOS_INFO, "TXT-STS: ACM verification "); @@ -138,8 +138,8 @@ if (!CONFIG(INTEL_TXT)) return false; - ret = (read8((void *)TXT_ESTS) & TXT_ESTS_WAKE_ERROR_STS) || - (read64((void *)TXT_E2STS) & TXT_E2STS_SECRET_STS); + ret = (read8p(TXT_ESTS) & TXT_ESTS_WAKE_ERROR_STS) || + (read64p(TXT_E2STS) & TXT_E2STS_SECRET_STS); if (ret) printk(BIOS_CRIT, "TXT-STS: Secrets in memory!\n"); @@ -154,10 +154,10 @@ * Chapter B.1.7 and B.1.9 * Intel TXT Software Development Guide (Document: 315168-015) */ - uint32_t reg = read32((void *)TXT_VER_FSBIF); + uint32_t reg = read32p(TXT_VER_FSBIF); if (reg == 0 || reg == UINT32_MAX) - reg = read32((void *)TXT_VER_QPIIF); + reg = read32p(TXT_VER_QPIIF); return (reg & TXT_VER_PRODUCTION_FUSED) ? true : false; } @@ -320,11 +320,11 @@ return; /* FIXME: Do we need to program these two? */ - //write32((void *)MCU_BASE_ADDR, 0xffe1a990); - //write32((void *)APINIT_ADDR, 0xfffffff0); + //write32p(MCU_BASE_ADDR, 0xffe1a990); + //write32p(APINIT_ADDR, 0xfffffff0); - write32((void *)BIOACM_ADDR, (uintptr_t)acm_data); - write32((void *)SEMAPHORE, 0); + write32p(BIOACM_ADDR, (uintptr_t)acm_data); + write32p(SEMAPHORE, 0); /* * The time SCLEAN will take depends on the installed RAM size. @@ -364,14 +364,14 @@ cbfs_unmap(acm_data); - const uint64_t acm_status = read64((void *)TXT_SPAD); + const uint64_t acm_status = read64p(TXT_SPAD); if (acm_status & ACMERROR_TXT_VALID) { printk(BIOS_ERR, "TEE-TXT: FATAL ACM launch error !\n"); /* * WARNING ! * To clear TXT.BIOSACM.ERRORCODE you must issue a cold reboot! */ - intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + intel_txt_log_acm_error(read32p(TXT_BIOSACM_ERRORCODE)); return -1; } @@ -460,7 +460,7 @@ if ((eax & 0x7d) != 0x7d) failure = true; - const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) { printk(BIOS_INFO, "TEE-TXT: TXT disabled by BIOS policy in FIT.\n"); diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index 6485b86..e1692cf 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -35,7 +35,7 @@ */ static void log_txt_error(const char *phase) { - const uint64_t txt_error = read64((void *)TXT_ERROR); + const uint64_t txt_error = read64p(TXT_ERROR); if (txt_error & ACMERROR_TXT_VALID) { printk(BIOS_ERR, "%s: Error occurred\n", phase); @@ -63,9 +63,9 @@ printk(BIOS_INFO, "TEE-TXT: State of ACM and ucode update:\n"); - bios_acm_error = read32((void *)TXT_BIOSACM_ERRORCODE); - acm_status = read64((void *)TXT_SPAD); - txt_error = read64((void *)TXT_ERROR); + bios_acm_error = read32p(TXT_BIOSACM_ERRORCODE); + acm_status = read64p(TXT_SPAD); + txt_error = read64p(TXT_ERROR); /* Errors by BIOS ACM or FIT */ if ((txt_error & ACMERROR_TXT_VALID) && @@ -81,10 +81,10 @@ } /* Check for fatal ACM error and TXT reset */ - uint8_t error = read8((void *)TXT_ESTS); + uint8_t error = read8p(TXT_ESTS); if (error & TXT_ESTS_TXT_RESET_STS) { printk(BIOS_CRIT, "TXT-STS: Intel TXT reset detected\n"); - intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + intel_txt_log_acm_error(read32p(TXT_ERROR)); } } @@ -178,12 +178,12 @@ { printk(BIOS_INFO, "TEE-TXT: Chipset Key Hash 0x"); for (int i = 0; i < TXT_ACM_KEY_HASH_LEN; i++) { - printk(BIOS_INFO, "%llx", read64((void *)TXT_ACM_KEY_HASH + + printk(BIOS_INFO, "%llx", read64p(TXT_ACM_KEY_HASH + (i * sizeof(uint64_t)))); } printk(BIOS_INFO, "\n"); - printk(BIOS_INFO, "TEE-TXT: DIDVID 0x%x\n", read32((void *)TXT_DIDVID)); + printk(BIOS_INFO, "TEE-TXT: DIDVID 0x%x\n", read32p(TXT_DIDVID)); printk(BIOS_INFO, "TEE-TXT: production fused chipset: %s\n", intel_txt_chipset_is_production_fused() ? "true" : "false"); } @@ -199,18 +199,18 @@ uint64_t reg64; - reg64 = read64((void *)TXT_HEAP_BASE); + reg64 = read64p(TXT_HEAP_BASE); if ((reg64 != 0 && reg64 != ~0UL) && - (read64((void *)(uintptr_t)reg64) >= (sizeof(*bdr) + sizeof(uint64_t)))) + (read64p((uintptr_t)reg64) >= (sizeof(*bdr) + sizeof(uint64_t)))) bdr = (void *)((uintptr_t)reg64 + sizeof(uint64_t)); printk(BIOS_DEBUG, "TEE-TXT: TSEG 0x%lx, size %zu MiB\n", tseg_base, tseg_size / MiB); - printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.BASE 0x%llx\n", read64((void *)TXT_HEAP_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.SIZE 0x%llx\n", read64((void *)TXT_HEAP_SIZE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.BASE 0x%llx\n", read64((void *)TXT_SINIT_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.SIZE 0x%llx\n", read64((void *)TXT_SINIT_SIZE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.BASE 0x%llx\n", read64((void *)TXT_MSEG_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.SIZE 0x%llx\n", read64((void *)TXT_MSEG_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.BASE 0x%llx\n", read64p(TXT_HEAP_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.SIZE 0x%llx\n", read64p(TXT_HEAP_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.BASE 0x%llx\n", read64p(TXT_SINIT_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.SIZE 0x%llx\n", read64p(TXT_SINIT_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.BASE 0x%llx\n", read64p(TXT_MSEG_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.SIZE 0x%llx\n", read64p(TXT_MSEG_SIZE)); if (bdr) { printk(BIOS_DEBUG, "TEE-TXT: BiosDataRegion.bios_sinit_size 0x%x\n", diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 8a266a4..5c03da9 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -20,8 +20,8 @@ /* FIXME: Seems to work only on some platforms */ static void log_ibb_measurements(void) { - const uint64_t mseg_size = read64((void *)TXT_MSEG_SIZE); - uint64_t mseg_base = read64((void *)TXT_MSEG_BASE); + const uint64_t mseg_size = read64p(TXT_MSEG_SIZE); + uint64_t mseg_base = read64p(TXT_MSEG_BASE); if (!mseg_size || !mseg_base || mseg_size <= mseg_base) return; @@ -34,14 +34,14 @@ printk(BIOS_INFO, "TEE-TXT: IBB Hash 0x"); for (; mseg_base < mseg_size; mseg_base++) - printk(BIOS_INFO, "%02X", read8((void *)(uintptr_t)mseg_base)); + printk(BIOS_INFO, "%02X", read8p((uintptr_t)mseg_base)); printk(BIOS_INFO, "\n"); } void bootmem_platform_add_ranges(void) { - uint64_t status = read64((void *)TXT_SPAD); + uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) return; @@ -67,7 +67,7 @@ BM_MEM_RESERVED); const union dpr_register dpr = { - .raw = read32((void *)TXT_DPR), + .raw = read32p(TXT_DPR), }; const uint32_t dpr_base = dpr.top - dpr.size * MiB; @@ -78,13 +78,13 @@ static bool get_wake_error_status(void) { - const uint8_t error = read8((void *)TXT_ESTS); + const uint8_t error = read8p(TXT_ESTS); return !!(error & TXT_ESTS_WAKE_ERROR_STS); } static void check_secrets_txt(void *unused) { - uint64_t status = read64((void *)TXT_SPAD); + uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) return; @@ -102,7 +102,7 @@ intel_txt_run_bios_acm(ACMINPUT_CLEAR_SECRETS); /* Should never reach this point ... */ - intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + intel_txt_log_acm_error(read32p(TXT_BIOSACM_ERRORCODE)); die("Waiting for platform reset...\n"); } } @@ -121,7 +121,7 @@ */ static void init_intel_txt(void *unused) { - const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD); if (status & ACMSTS_TXT_DISABLED) return; @@ -250,10 +250,10 @@ txt_heap_fill_common_bdr(&data.bdr); txt_heap_fill_bios_spec(&data.spec); - void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + void *sinit_base = (void *)(uintptr_t)read64p(TXT_SINIT_BASE); data.bdr.bios_sinit_size = cbfs_load(CONFIG_INTEL_TXT_CBFS_SINIT_ACM, sinit_base, - read64((void *)TXT_SINIT_SIZE)); + read64p(TXT_SINIT_SIZE)); /* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; @@ -295,9 +295,9 @@ txt_heap_fill_common_bdr(&data.bdr); txt_heap_fill_bios_spec(&data.spec); - void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + void *sinit_base = (void *)(uintptr_t)read64p(TXT_SINIT_BASE); /* Clear SINIT ACM memory */ - memset(sinit_base, 0, read64((void *)TXT_SINIT_SIZE)); + memset(sinit_base, 0, read64p(TXT_SINIT_SIZE)); /* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; @@ -318,7 +318,7 @@ static void txt_initialize_heap(void) { /* Fill TXT.HEAP.BASE with 4 subregions */ - u8 *heap_struct = (void *)((uintptr_t)read64((void *)TXT_HEAP_BASE)); + u8 *heap_struct = (void *)((uintptr_t)read64p(TXT_HEAP_BASE)); /* * Since we may have either BIOS ACM or both BIOS and SINIT ACMs in @@ -365,7 +365,7 @@ if (skip_intel_txt_lockdown()) return; - const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD); uint32_t txt_feature_flags = 0; uintptr_t tseg_base; @@ -401,7 +401,7 @@ * Chapter 5.5.6.1 DMA Protection Memory Region */ - const u8 dpr_capable = !!(read64((void *)TXT_CAPABILITIES) & + const u8 dpr_capable = !!(read64p(TXT_CAPABILITIES) & TXT_CAPABILITIES_DPR); printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable); @@ -443,28 +443,28 @@ dpr.prs = 0; dpr.epm = 0; - write64((void *)TXT_DPR, dpr.raw); + write64p(TXT_DPR, dpr.raw); printk(BIOS_INFO, "TEE-TXT: TXT.DPR 0x%08x\n", - read32((void *)TXT_DPR)); + read32p(TXT_DPR)); } /* * Document Number: 558294 * Chapter 5.5.6.3 Intel TXT Heap Memory Region */ - write64((void *)TXT_HEAP_SIZE, CONFIG_INTEL_TXT_HEAP_SIZE); - write64((void *)TXT_HEAP_BASE, - ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096)); + write64p(TXT_HEAP_SIZE, CONFIG_INTEL_TXT_HEAP_SIZE); + write64p(TXT_HEAP_BASE, + ALIGN_DOWN(tseg_base - read64p(TXT_HEAP_SIZE), 4096)); /* * Document Number: 558294 * Chapter 5.5.6.2 SINIT Memory Region */ - write64((void *)TXT_SINIT_SIZE, CONFIG_INTEL_TXT_SINIT_SIZE); - write64((void *)TXT_SINIT_BASE, - ALIGN_DOWN(read64((void *)TXT_HEAP_BASE) - - read64((void *)TXT_SINIT_SIZE), 4096)); + write64p(TXT_SINIT_SIZE, CONFIG_INTEL_TXT_SINIT_SIZE); + write64p(TXT_SINIT_BASE, + ALIGN_DOWN(read64p(TXT_HEAP_BASE) - + read64p(TXT_SINIT_SIZE), 4096)); /* * FIXME: Server-TXT capable platforms need to install an STM in SMM and set up MSEG. @@ -474,8 +474,8 @@ * Chapter 5.10.1 SMM in the Intel TXT for Servers Environment * Disable MSEG. */ - write64((void *)TXT_MSEG_SIZE, 0); - write64((void *)TXT_MSEG_BASE, 0); + write64p(TXT_MSEG_SIZE, 0); + write64p(TXT_MSEG_BASE, 0); /* Only initialize the heap on regular boots */ if (!acpi_is_wakeup_s3()) diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index aa7cc2c..643e7a9 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -63,7 +63,7 @@ return; } - const uint8_t txt_ests = read8((void *)TXT_ESTS); + const uint8_t txt_ests = read8p(TXT_ESTS); const bool establishment = is_establishment_bit_asserted(); const bool is_wake_error = !!(txt_ests & TXT_ESTS_WAKE_ERROR_STS); diff --git a/src/security/intel/txt/txtlib.c b/src/security/intel/txt/txtlib.c index 5478206..6ce86a3 100644 --- a/src/security/intel/txt/txtlib.c +++ b/src/security/intel/txt/txtlib.c @@ -20,7 +20,7 @@ stopwatch_init_msecs_expire(&timer, 50); while (true) { - access = read8((void *)TPM_ACCESS_REG); + access = read8p(TPM_ACCESS_REG); /* Register returns all ones if TPM is missing */ if (access == 0xff) -- To view, visit https://review.coreboot.org/c/coreboot/+/80194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bdfcd0cc0e2d9b5f884ea7275659c12488715e0 Gerrit-Change-Number: 80194 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: security/intel: Use write{64,32,16,8}p and read{64,32,16,8}p
by Felix Held (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80194?usp=email ) Change subject: security/intel: Use write{64,32,16,8}p and read{64,32,16,8}p ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bdfcd0cc0e2d9b5f884ea7275659c12488715e0 Gerrit-Change-Number: 80194 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 30 Jan 2024 12:27:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Update maintainers list for INTEL Xeon Scalable Processo...
by Shuo Liu (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: Lean Sheng Tan, Patrick Rudolph. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80240?usp=email ) Change subject: MAINTAINERS: Update maintainers list for INTEL Xeon Scalable Processor Family ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Leansheng, could you please add others for review? -- To view, visit https://review.coreboot.org/c/coreboot/+/80240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide3aa87fca69be6b0f1ffe0b18d7ffb410e5c563 Gerrit-Change-Number: 80240 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 30 Jan 2024 12:27:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Sapphire Rapids FSP headers into scope of INTEL Xeon...
by Shuo Liu (Code Review) 30 Jan '24

30 Jan '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80241?usp=email ) Change subject: MAINTAINERS: Add Sapphire Rapids FSP headers into scope of INTEL Xeon Sacalable Processor Family ...................................................................... MAINTAINERS: Add Sapphire Rapids FSP headers into scope of INTEL Xeon Sacalable Processor Family Change-Id: I20ad4bc325d5cfe7a9d5f8b349eeea3d6218452b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M MAINTAINERS 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/80241/1 diff --git a/MAINTAINERS b/MAINTAINERS index 8b4f26d..d093071 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -948,6 +948,7 @@ F: src/soc/intel/xeon_sp/ F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/ F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/ +F: src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/ MEDIATEK SOCS M: Hung-Te Lin <hungte(a)chromium.org> -- To view, visit https://review.coreboot.org/c/coreboot/+/80241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20ad4bc325d5cfe7a9d5f8b349eeea3d6218452b Gerrit-Change-Number: 80241 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

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