coreboot-gerrit January 2024

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[XS] Change in coreboot[main]: mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock
by Subrata Banik (Code Review) 30 Jan '24

30 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80000?usp=email ) Change subject: mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock ...................................................................... mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock Check MTL EDS2, SOC_TCHSCR_RST(GPP_C01) default setting is NF1. Set SOC_TCHSCR_RST to output low in early_gpio_table. BUG=none TEST=Build and test on karis, touchscreen function works Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80000 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/rex/variants/karis/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/karis/gpio.c b/src/mainboard/google/rex/variants/karis/gpio.c index 8c0f929..6bd23ca 100644 --- a/src/mainboard/google/rex/variants/karis/gpio.c +++ b/src/mainboard/google/rex/variants/karis/gpio.c @@ -403,6 +403,8 @@ /* GPP_C00 : [] ==> EN_TCHSCR_PWR */ PAD_CFG_GPO(GPP_C00, 1, DEEP), + /* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */ + PAD_CFG_GPO(GPP_C01, 0, DEEP), }; static const struct pad_config romstage_gpio_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/80000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Gerrit-Change-Number: 80000 Gerrit-PatchSet: 9 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock
by Subrata Banik (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Paul Menzel, Sumeet R Pawnikar, Tarun, Tyler Wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80000?usp=email ) Change subject: mb/google/rex/var/karis: Set SOC_TCHSCR_RST output low in bootblock ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieebd3cf3c320bc895d036c372f792ec7b5d7ebf9 Gerrit-Change-Number: 80000 Gerrit-PatchSet: 8 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Jan 2024 14:41:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Sapphire Rapids FSP headers to Xeon SP
by Felix Singer (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held, Patrick Rudolph, Paul Menzel, Shuo Liu. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80241?usp=email ) Change subject: MAINTAINERS: Add Sapphire Rapids FSP headers to Xeon SP ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20ad4bc325d5cfe7a9d5f8b349eeea3d6218452b Gerrit-Change-Number: 80241 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 30 Jan 2024 14:40:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Update maintainers list for Xeon SP
by Felix Singer (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held, Patrick Rudolph, Paul Menzel, Shuo Liu. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80240?usp=email ) Change subject: MAINTAINERS: Update maintainers list for Xeon SP ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide3aa87fca69be6b0f1ffe0b18d7ffb410e5c563 Gerrit-Change-Number: 80240 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 30 Jan 2024 14:40:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: src/device/oprom/include/x86emu/regs.h: Fix checkpatch errors Add spa...
by Simon Glass (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: Aryan Arora. Simon Glass has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80185?usp=email ) Change subject: src/device/oprom/include/x86emu/regs.h: Fix checkpatch errors Add space after keywords, scope with a do-while loop for a multiline macro and split a single line if-else to multiline. ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80185/comment/9d4cf417_67611e1c : PS1, Line 6: > `A patch subject line should describe the change not the tool that found it` Please fix. https://review.coreboot.org/c/coreboot/+/80185/comment/0ee11043_5e43190b : PS1, Line 6: > `Possible long commit subject (prefer a maximum 65 characters)` Please fix. Patchset: PS1: This seems OK to me. I wonder if it is OK to use the ({ ... }) construct? -- To view, visit https://review.coreboot.org/c/coreboot/+/80185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia66aed706469c9f077a1d5eb6b4af662341c913c Gerrit-Change-Number: 80185 Gerrit-PatchSet: 1 Gerrit-Owner: Aryan Arora <aryanarora.w1(a)gmail.com> Gerrit-CC: Simon Glass <sjg(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aryan Arora <aryanarora.w1(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Jan 2024 14:27:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/phoenix/chip: make FSP-S call conditional
by Varshit Pandya (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80242?usp=email ) Change subject: soc/amd/phoenix/chip: make FSP-S call conditional ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80242?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2666f1ac0f0354146ffe005b3ce99484defda7a8 Gerrit-Change-Number: 80242 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 30 Jan 2024 14:22:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Drop unused MACROs
by Felix Held (Code Review) 30 Jan '24

30 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Patrick Rudolph, Tim Chu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80096?usp=email ) Change subject: soc/intel/xeon_sp: Drop unused MACROs ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/80096/comment/5022b9c2_726af967 : PS8, Line 79: #define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) that line should probably also be removed -- To view, visit https://review.coreboot.org/c/coreboot/+/80096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4067a1940f6cb3ee6d40c784877d7906495251a4 Gerrit-Change-Number: 80096 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 30 Jan 2024 13:37:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/phoenix/chip: make FSP-S call conditional
by Felix Held (Code Review) 30 Jan '24

30 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80242?usp=email ) Change subject: soc/amd/phoenix/chip: make FSP-S call conditional ...................................................................... soc/amd/phoenix/chip: make FSP-S call conditional Only call amd_fsp_silicon_init if PLATFORM_USES_FSP2_0 is selected in Kconfig. I'm not 100% sure about the data_fabric_set_mmio_np call yet, but since it doesn't depend on PLATFORM_USES_FSP2_0 to compile, I'll look into that one later. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2666f1ac0f0354146ffe005b3ce99484defda7a8 --- M src/soc/amd/phoenix/chip.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/80242/1 diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index 173b220..591df1f8 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -39,7 +39,8 @@ { default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables; - amd_fsp_silicon_init(); + if (CONFIG(PLATFORM_USES_FSP2_0)) + amd_fsp_silicon_init(); data_fabric_set_mmio_np(); -- To view, visit https://review.coreboot.org/c/coreboot/+/80242?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2666f1ac0f0354146ffe005b3ce99484defda7a8 Gerrit-Change-Number: 80242 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel: Unify the definition of TCO registers
by Felix Held (Code Review) 30 Jan '24

30 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80005?usp=email ) Change subject: soc/intel: Unify the definition of TCO registers ...................................................................... soc/intel: Unify the definition of TCO registers Move the definition of the TCO registers used in most boards to a separate file and use it consistently. Do not unify TCO for older incompatible platforms. BUG=b:314260167 TEST=none Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Signed-off-by: Marek Maslanka <mmaslanka(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Jakub Czapiga <czapiga(a)google.com> --- M src/soc/intel/apollolake/elog.c M src/soc/intel/apollolake/include/soc/smbus.h M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/pch/include/intelpch/smbus.h A src/soc/intel/common/tco.h M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/xeon_sp/include/soc/smbus.h M src/southbridge/intel/common/tco.h M src/southbridge/intel/common/watchdog.c 11 files changed, 64 insertions(+), 79 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve Jakub Czapiga: Looks good to me, approved diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index f500b93..e5e00dd 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -76,7 +76,7 @@ /* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco1_sts & TCO_TIMEOUT) + ps->tco1_sts & TCO1_STS_TIMEOUT) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index a87211a..067879b 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -3,19 +3,7 @@ #ifndef _SOC_APOLLOLAKE_SMBUS_H_ #define _SOC_APOLLOLAKE_SMBUS_H_ -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) +#include <soc/intel/common/tco.h> #define SMBUS_SLAVE_ADDR 0x24 diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1f1a85c..9045343 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -56,7 +56,7 @@ /* TCO Lock down */ tcocnt = tco_read_reg(TCO1_CNT); - tcocnt |= TCO_LOCK; + tcocnt |= TCO1_LOCK; tco_write_reg(TCO1_CNT, tcocnt); } @@ -83,7 +83,7 @@ /* Program TCO timer halt */ tcocnt = tco_read_reg(TCO1_CNT); - tcocnt |= TCO_TMR_HLT; + tcocnt |= TCO1_TMR_HLT; tco_write_reg(TCO1_CNT, tcocnt); } @@ -94,8 +94,8 @@ /* Make TCO issue an SMI on INTRD_DET assertion */ tcocnt = tco_read_reg(TCO2_CNT); - tcocnt &= ~TCO_INTRD_SEL_MASK; - tcocnt |= TCO_INTRD_SEL_SMI; + tcocnt &= ~TCO2_INTRD_SEL_MASK; + tcocnt |= TCO2_INTRD_SEL_SMI; tco_write_reg(TCO2_CNT, tcocnt); } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 6c27196..59489a4 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -460,12 +460,12 @@ if (!tco_sts) return; - if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */ + if (tco_sts & TCO1_STS_TIMEOUT) { /* TIMEOUT */ /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); } - if (tco_sts & (TCO_INTRD_DET << 16)) { /* INTRUDER# assertion */ + if (tco_sts & (TCO2_INTRD_DET << 16)) { /* INTRUDER# assertion */ /* * Handle intrusion event * If we ever get here, probably the case has been opened. diff --git a/src/soc/intel/common/pch/include/intelpch/smbus.h b/src/soc/intel/common/pch/include/intelpch/smbus.h index 78b7953..d5501ad 100644 --- a/src/soc/intel/common/pch/include/intelpch/smbus.h +++ b/src/soc/intel/common/pch/include/intelpch/smbus.h @@ -3,19 +3,7 @@ #ifndef _INTELPCH_SMBUS_H_ #define _INTELPCH_SMBUS_H_ -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) +#include <soc/intel/common/tco.h> /* * Default slave address value for PCH. This value is set to match default diff --git a/src/soc/intel/common/tco.h b/src/soc/intel/common/tco.h new file mode 100644 index 0000000..42685cf --- /dev/null +++ b/src/soc/intel/common/tco.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _INTELPCH_TCO_H_ +#define _INTELPCH_TCO_H_ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO_RLD 0x00 +#define TCO_DAT_IN 0x02 +#define TCO_DAT_OUT 0x03 +#define TCO1_STS 0x04 +#define TCO1_STS_TCO_SLVSEL (1 << 13) +#define TCO1_STS_CPUSERR (1 << 12) +#define TCO1_STS_CPUSMI (1 << 10) +#define TCO1_STS_CPUSCI (1 << 9) +#define TCO1_STS_BIOSWR (1 << 8) +#define TCO1_STS_NEWCENTURY (1 << 7) +#define TCO1_STS_TIMEOUT (1 << 3) +#define TCO1_STS_TCO_INT (1 << 2) +#define TCO1_STS_OS_TCO_SMI (1 << 1) +#define TCO1_STS_NMI2SMI (1 << 0) +#define TCO2_STS 0x06 +#define TCO2_STS_SMLINK_SLAVE_SMI (1 << 2) +#define TCO2_STS_SECOND_TO (1 << 1) +#define TCO2_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO1_LOCK (1 << 12) +#define TCO1_TMR_HLT (1 << 11) +#define TCO1_NMI2SMI_EN (1 << 9) +#define TCO1_NMI_NOW (1 << 8) +#define TCO2_CNT 0x0A +#define TCO2_OS_POLICY_MASK (3 << 4) +#define TCO2_OS_POLICY_SHUTDOWN (1 << 4) +#define TCO2_OS_POLICY_DONOT_LOAD (1 << 5) +#define TCO2_SMB_ALERT_DISABLE (1 << 3) +#define TCO2_INTRD_SEL_MASK (3 << 1) +#define TCO2_INTRD_SEL_SMI (1 << 2) +#define TCO2_INTRD_SEL_INT (1 << 1) +#define TCO_MESSAGE1 0x0C +#define TCO_MESSAGE2 0x0D +#define TCO_WDSTATUS 0x0E +#define TCO_LEGACY_ELIM 0x10 +#define TCO_IRQ12_CAUSE (1 << 1) +#define TCO_IRQ1_CAUSE (1 << 0) +#define TCO_TMR 0x12 +#define TCO_TMR_MASK 0x3FF + +#endif diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index 6e4044d..f77e4fa 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -3,6 +3,8 @@ #ifndef _DENVERTON_NS_PMC_H_ #define _DENVERTON_NS_PMC_H_ +#include <soc/intel/common/tco.h> + /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ #define PMC_ACPI_BASE 0x40 /* IO BAR */ #define MASK_PMC_ACPI_BASE 0xfffc @@ -214,29 +216,6 @@ #define SWGPE_EN (1 << 2) #define HOT_PLUG_EN (1 << 1) -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO_RLD 0x00 -#define TCO1_STS 0x04 -#define TCO1_STS_TCO_SLVSEL (1 << 13) -#define TCO1_STS_CPUSERR (1 << 12) -#define TCO1_STS_CPUSMI (1 << 10) -#define TCO1_STS_CPUSCI (1 << 9) -#define TCO1_STS_BIOSWR (1 << 8) -#define TCO1_STS_NEWCENTURY (1 << 7) -#define TCO1_STS_TIMEOUT (1 << 3) -#define TCO1_STS_TCO_INT (1 << 2) -#define TCO1_STS_OS_TCO_SMI (1 << 1) -#define TCO1_STS_NMI2SMI (1 << 0) -#define TCO2_STS 0x06 -#define TCO2_STS_SMLINK_SLAVE_SMI 0x04 -#define TCO2_STS_SECOND_TO 0x02 -#define TCO2_STS_INTRD_DET 0x01 -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0a -#define TCO_TMR 0x12 - /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ #define PRSTS 0x10 #define GPIO_GPE_CFG 0x120 diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 2f3a5cc..8e555ef 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -110,7 +110,7 @@ /* Halt the TCO timer */ uint16_t reg16 = inw(tco_base + TCO1_CNT); - reg16 |= TCO_TMR_HLT; + reg16 |= TCO1_TMR_HLT; outw(reg16, tco_base + TCO1_CNT); /* Clear the Second TCO status bit */ diff --git a/src/soc/intel/xeon_sp/include/soc/smbus.h b/src/soc/intel/xeon_sp/include/soc/smbus.h index 7ef9d0b..5d7dbb1 100644 --- a/src/soc/intel/xeon_sp/include/soc/smbus.h +++ b/src/soc/intel/xeon_sp/include/soc/smbus.h @@ -3,19 +3,7 @@ #ifndef _SOC_SMBUS_H_ #define _SOC_SMBUS_H_ -/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) +#include <soc/intel/common/tco.h> /* SMBus I/O bits. */ #define SMBUS_SLAVE_ADDR 0x24 diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 5bf386f..b586fe5 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -10,13 +10,8 @@ #undef TCO1_CNT #endif -#define PMBASE_TCO_OFFSET 0x60 +#include <soc/intel/common/tco.h> -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) -#define TCO1_CNT 0x08 -#define TCO_TMR_HLT (1 << 11) +#define PMBASE_TCO_OFFSET 0x60 #endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */ diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index 1c43a0c..36b9525 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -27,11 +27,11 @@ /* Disable the watchdog timer. */ value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT); - value |= TCO_TMR_HLT; + value |= TCO1_TMR_HLT; write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value); /* Clear TCO timeout status. */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_STS_TIMEOUT); write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO); printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/80005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Gerrit-Change-Number: 80005 Gerrit-PatchSet: 12 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in em100[main]: em100: return an error if a command fails
by Name of user not set (Code Review) 30 Jan '24

30 Jan '24

c.koehne(a)beckhoff.com has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/80250?usp=email ) Change subject: em100: return an error if a command fails ...................................................................... em100: return an error if a command fails We don't properly return an error in every code path when a command fails. This makes it hard to use this tool in a shell script because you can't be sure that your command was successful. Change-Id: I2554252d007a92e939088389d67f9d4cede837ee Signed-off-by: Corvin Köhne <c.koehne(a)beckhoff.com> --- M em100.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/50/80250/1 diff --git a/em100.c b/em100.c index 666cef9..68407c3 100644 --- a/em100.c +++ b/em100.c @@ -1068,7 +1068,7 @@ if (!set_chip_type(em100, chip)) { printf("Failed configuring chip type.\n"); em100_detach(em100); - return 0; + return 1; } printf("Chip set to %s %s.\n", chip->vendor, chip->name); @@ -1099,7 +1099,7 @@ if (!set_hold_pin_state_from_str(em100, holdpin)) { printf("Failed configuring hold pin state.\n"); em100_detach(em100); - return 0; + return 1; } } -- To view, visit https://review.coreboot.org/c/em100/+/80250?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: main Gerrit-Change-Id: I2554252d007a92e939088389d67f9d4cede837ee Gerrit-Change-Number: 80250 Gerrit-PatchSet: 1 Gerrit-Owner: c.koehne(a)beckhoff.com Gerrit-MessageType: newchange

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