coreboot-gerrit January 2024

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[S] Change in coreboot[main]: soc/amd/*/romstage: factor out FSP-M call
by Felix Held (Code Review) 19 Jan '24

19 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth. Hello Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80002?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Martin Roth, Verified+1 by build bot (Jenkins) Change subject: soc/amd/*/romstage: factor out FSP-M call ...................................................................... soc/amd/*/romstage: factor out FSP-M call Move the call into the FSP code to a file in the common AMD FSP code to isolate the FSP-specific parts of the code and a preparation to make the romstage of all non-CAR AMD SoCs common. Without isolating the call into the FSP-M code, building the common romstage would fail for genoa_poc due to fsp/api.h not being in the include path. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I30cf1bee2ec1a507dc8e61eaf44067663e2505ae --- M src/soc/amd/cezanne/romstage.c A src/soc/amd/common/block/include/amdblocks/fsp.h M src/soc/amd/common/fsp/Makefile.inc A src/soc/amd/common/fsp/fsp_romstage.c M src/soc/amd/glinda/romstage.c M src/soc/amd/mendocino/romstage.c M src/soc/amd/phoenix/romstage.c M src/soc/amd/picasso/romstage.c 8 files changed, 29 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/80002/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30cf1bee2ec1a507dc8e61eaf44067663e2505ae Gerrit-Change-Number: 80002 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/amd/*/romstage: factor out FSP-M call
by Matt DeVillier (Code Review) 18 Jan '24

18 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80002?usp=email ) Change subject: soc/amd/*/romstage: factor out FSP-M call ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/romstage.c: https://review.coreboot.org/c/coreboot/+/80002/comment/c8596677_35b3bd9b : PS2, Line 20: call > Just a nit, but I'm not crazy about the name. I'm channeling my inner Paul here. […] fsp_early_init() ? -- To view, visit https://review.coreboot.org/c/coreboot/+/80002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30cf1bee2ec1a507dc8e61eaf44067663e2505ae Gerrit-Change-Number: 80002 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 18 Jan 2024 22:30:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/*/chip: factor out FSP-S call
by Martin Roth (Code Review) 18 Jan '24

18 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80084?usp=email ) Change subject: soc/amd/*/chip: factor out FSP-S call ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Patchset: PS1: Handle this the same as the fsp_s change. File src/soc/amd/cezanne/chip.c: https://review.coreboot.org/c/coreboot/+/80084/comment/59e1b517_00e634f0 : PS1, Line 40: fsp_s_call same comment as for fsp_m_call. I just don't like the "call" part. It's like naming functions "blahblahblah_func()" It just seems redundant. -- To view, visit https://review.coreboot.org/c/coreboot/+/80084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8236db7ac80275a65020b7e7a9acce8314c831c Gerrit-Change-Number: 80084 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 18 Jan 2024 22:20:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd: factor out non-CAR romstage to common code
by Martin Roth (Code Review) 18 Jan '24

18 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80083?usp=email ) Change subject: soc/amd: factor out non-CAR romstage to common code ...................................................................... Patch Set 2: (2 comments) File src/soc/amd/common/block/acpimmio/Kconfig: https://review.coreboot.org/c/coreboot/+/80083/comment/222ef2d1_f8c77f75 : PS2, Line 21: config SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP Put this in the soc/amd/common/block/cpu Kconfig? File src/soc/amd/common/block/cpu/noncar/romstage.c: https://review.coreboot.org/c/coreboot/+/80083/comment/657bcc12_563683bc : PS2, Line 32: Fixup Nit: This should just be 'fix' or two words, 'fix up'. A 'fixup' is a noun (if you can even count it as a real word - it's not in the dictionary), 'fix' or 'fix up' is the verb. This is similar to 'set up', a verb, vs 'setup', a noun. Fix it up if you want, or not. Up to you. :) -- To view, visit https://review.coreboot.org/c/coreboot/+/80083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9 Gerrit-Change-Number: 80083 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 18 Jan 2024 22:17:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/*/romstage: factor out FSP-M call
by Martin Roth (Code Review) 18 Jan '24

18 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80002?usp=email ) Change subject: soc/amd/*/romstage: factor out FSP-M call ...................................................................... Patch Set 2: Code-Review+2 (2 comments) Patchset: PS2: I'm marking it as +2, because it's really fine, I'm just not crazy about the name. Feel free to ignore my comment if I'm being silly. File src/soc/amd/cezanne/romstage.c: https://review.coreboot.org/c/coreboot/+/80002/comment/a904405b_75b71d82 : PS2, Line 20: call Just a nit, but I'm not crazy about the name. I'm channeling my inner Paul here. Maybe something like one of these: - run_fsp_m() - fsp_m_init() - fsp_m() - early_silicon_init() - this could be preceded by "first_silicon_init()" and we could have mid_ late_ final_ post_enum_ etc_ come later. -- To view, visit https://review.coreboot.org/c/coreboot/+/80002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30cf1bee2ec1a507dc8e61eaf44067663e2505ae Gerrit-Change-Number: 80002 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 18 Jan 2024 22:08:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd/phoenix/Kconfig: factor out FSP-specific options
by Martin Roth (Code Review) 18 Jan '24

18 Jan '24

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[S] Change in coreboot[main]: mainboard/Kconfig: add 24MB ROM size
by Felix Singer (Code Review) 18 Jan '24

18 Jan '24

Attention is currently required from: Maciej Pijanowski, Michał Kopeć, Michał Żygowski. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80072?usp=email ) Change subject: mainboard/Kconfig: add 24MB ROM size ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80072/comment/5dda682f_316d6226 : PS1, Line 9: Lenovo M920 Sounds like there is a new board incoming. Looking forward to it! -- To view, visit https://review.coreboot.org/c/coreboot/+/80072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac6e076ed17d7e944cc829ff0cb27ede50c6f7db Gerrit-Change-Number: 80072 Gerrit-PatchSet: 1 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Thu, 18 Jan 2024 21:54:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mainboard/Kconfig: add 24MB ROM size
by Maciej Pijanowski (Code Review) 18 Jan '24

18 Jan '24

Maciej Pijanowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80072?usp=email ) Change subject: mainboard/Kconfig: add 24MB ROM size ...................................................................... mainboard/Kconfig: add 24MB ROM size 16MB + 8MB flashes are used on some boards, such as Lenovo M920 Change-Id: Iac6e076ed17d7e944cc829ff0cb27ede50c6f7db Signed-off-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> --- M src/mainboard/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/80072/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index aec996a..ec4ae8f 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -44,6 +44,8 @@ bool config BOARD_ROMSIZE_KB_16384 bool +config BOARD_ROMSIZE_KB_24576 + bool config BOARD_ROMSIZE_KB_32768 bool config BOARD_ROMSIZE_KB_65536 @@ -63,6 +65,7 @@ default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 + default COREBOOT_ROMSIZE_KB_24576 if BOARD_ROMSIZE_KB_24576 default COREBOOT_ROMSIZE_KB_32768 if BOARD_ROMSIZE_KB_32768 default COREBOOT_ROMSIZE_KB_65536 if BOARD_ROMSIZE_KB_65536 help @@ -126,6 +129,11 @@ help Choose this option if you have a 16384 KB (16 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_24576 + bool "24576 KB (24 MB)" + help + Choose this option if you have a 24576 KB (24 MB) ROM chip. + config COREBOOT_ROMSIZE_KB_32768 bool "32768 KB (32 MB)" help @@ -152,6 +160,7 @@ default 10240 if COREBOOT_ROMSIZE_KB_10240 default 12288 if COREBOOT_ROMSIZE_KB_12288 default 16384 if COREBOOT_ROMSIZE_KB_16384 + default 24576 if COREBOOT_ROMSIZE_KB_24576 default 32768 if COREBOOT_ROMSIZE_KB_32768 default 65536 if COREBOOT_ROMSIZE_KB_65536 @@ -169,6 +178,7 @@ default 0x00a00000 if COREBOOT_ROMSIZE_KB_10240 default 0x00c00000 if COREBOOT_ROMSIZE_KB_12288 default 0x01000000 if COREBOOT_ROMSIZE_KB_16384 + default 0x01800000 if COREBOOT_ROMSIZE_KB_24576 default 0x02000000 if COREBOOT_ROMSIZE_KB_32768 default 0x04000000 if COREBOOT_ROMSIZE_KB_65536 -- To view, visit https://review.coreboot.org/c/coreboot/+/80072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac6e076ed17d7e944cc829ff0cb27ede50c6f7db Gerrit-Change-Number: 80072 Gerrit-PatchSet: 1 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/amd/*/chip: factor out FSP-S call
by Felix Held (Code Review) 18 Jan '24

18 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80084?usp=email ) Change subject: soc/amd/*/chip: factor out FSP-S call ...................................................................... soc/amd/*/chip: factor out FSP-S call Move the call into the FSP code to a file in the common AMD FSP code to isolate the FSP-specific parts of the code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic8236db7ac80275a65020b7e7a9acce8314c831c --- M src/soc/amd/cezanne/chip.c M src/soc/amd/common/block/include/amdblocks/fsp.h M src/soc/amd/common/fsp/Makefile.inc A src/soc/amd/common/fsp/fsp_ramstage.c M src/soc/amd/glinda/chip.c M src/soc/amd/mendocino/chip.c M src/soc/amd/phoenix/chip.c M src/soc/amd/picasso/chip.c 8 files changed, 21 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/80084/1 diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 9fd687b..ac846de 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/data_fabric.h> +#include <amdblocks/fsp.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/pci_devs.h> @@ -37,7 +37,7 @@ { default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; - fsp_silicon_init(); + fsp_s_call(); data_fabric_set_mmio_np(); diff --git a/src/soc/amd/common/block/include/amdblocks/fsp.h b/src/soc/amd/common/block/include/amdblocks/fsp.h index f666da3..a099e83 100644 --- a/src/soc/amd/common/block/include/amdblocks/fsp.h +++ b/src/soc/amd/common/block/include/amdblocks/fsp.h @@ -4,5 +4,6 @@ #define AMD_BLOCK_FSP_H void fsp_m_call(void); +void fsp_s_call(void); #endif /* AMD_BLOCK_FSP_H */ diff --git a/src/soc/amd/common/fsp/Makefile.inc b/src/soc/amd/common/fsp/Makefile.inc index 2517f0c..fb78f52 100644 --- a/src/soc/amd/common/fsp/Makefile.inc +++ b/src/soc/amd/common/fsp/Makefile.inc @@ -6,6 +6,7 @@ romstage-y += fsp_validate.c ramstage-y += fsp_graphics.c ramstage-y += fsp_memmap.c +ramstage-y += fsp_ramstage.c ramstage-y += fsp_report_resources.c ramstage-y += fsp_reset.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fsp-acpi.c diff --git a/src/soc/amd/common/fsp/fsp_ramstage.c b/src/soc/amd/common/fsp/fsp_ramstage.c new file mode 100644 index 0000000..8882d0b --- /dev/null +++ b/src/soc/amd/common/fsp/fsp_ramstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/fsp.h> +#include <fsp/api.h> + +void fsp_s_call(void) +{ + fsp_silicon_init(); +} diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c index 47794e6..db31b0b 100644 --- a/src/soc/amd/glinda/chip.c +++ b/src/soc/amd/glinda/chip.c @@ -3,10 +3,10 @@ /* TODO: Update for Glinda */ #include <amdblocks/data_fabric.h> +#include <amdblocks/fsp.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/pci_devs.h> @@ -39,7 +39,7 @@ { default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; - fsp_silicon_init(); + fsp_s_call(); data_fabric_set_mmio_np(); diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c index b3cbc74..1dd1481 100644 --- a/src/soc/amd/mendocino/chip.c +++ b/src/soc/amd/mendocino/chip.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/data_fabric.h> +#include <amdblocks/fsp.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/pci_devs.h> @@ -37,7 +37,7 @@ { default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; - fsp_silicon_init(); + fsp_s_call(); data_fabric_set_mmio_np(); diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index 1bbb1b5..405da7b 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -3,10 +3,10 @@ /* TODO: Update for Phoenix */ #include <amdblocks/data_fabric.h> +#include <amdblocks/fsp.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <fsp/api.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/pci_devs.h> @@ -39,7 +39,7 @@ { default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; - fsp_silicon_init(); + fsp_s_call(); data_fabric_set_mmio_np(); diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 067c4a07..4e38af8 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/data_fabric.h> +#include <amdblocks/fsp.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -11,7 +12,6 @@ #include <soc/pci_devs.h> #include <soc/southbridge.h> #include "chip.h" -#include <fsp/api.h> static const char *soc_acpi_name(const struct device *dev) { @@ -38,7 +38,7 @@ { default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; - fsp_silicon_init(); + fsp_s_call(); data_fabric_set_mmio_np(); fch_init(chip_info); -- To view, visit https://review.coreboot.org/c/coreboot/+/80084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8236db7ac80275a65020b7e7a9acce8314c831c Gerrit-Change-Number: 80084 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/amd: factor out non-CAR romstage to common code
by Felix Held (Code Review) 18 Jan '24

18 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80083?usp=email to look at the new patch set (#2). Change subject: soc/amd: factor out non-CAR romstage to common code ...................................................................... soc/amd: factor out non-CAR romstage to common code Since the romstage code is very similar between all AMD non-CAR SoCs, factor out a common romstage implementation. All SoCs that select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE call fill_chipset_state, so this Kconfig option can be used to determine whether to make that call. In the FSP case, fsp_m_call gets called, while in the case of an implementation that doesn't rely on an FSP to do the initialization, cbmem_initialize_empty gets called to set up CBMEM which otherwise would be done inside the FSP driver code. Since only some SoCs call fch_disable_legacy_dma_io again in romstage right after fsp_m_call, introduce the new SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP Kconfig option, so that the SoCs can specify if this call is needed or not. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc D src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/acpimmio/Kconfig M src/soc/amd/common/block/cpu/noncar/Makefile.inc A src/soc/amd/common/block/cpu/noncar/romstage.c M src/soc/amd/genoa_poc/Makefile.inc D src/soc/amd/genoa_poc/romstage.c M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.inc D src/soc/amd/glinda/romstage.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc D src/soc/amd/mendocino/romstage.c M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc D src/soc/amd/phoenix/romstage.c M src/soc/amd/picasso/Makefile.inc D src/soc/amd/picasso/romstage.c 19 files changed, 50 insertions(+), 165 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/80083/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a0695714ba08b13a58b12a490da50cb7f5a1ca9 Gerrit-Change-Number: 80083 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2024