Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79938?usp=email )
Change subject: mb/lenovo/t530: Remove superfluous comments related to PCI devices
......................................................................
mb/lenovo/t530: Remove superfluous comments related to PCI devices
Since all devicetrees from lenovo/t530 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: I5ba08843506bc22136aea42ac37936a4f5cad5ce
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79938
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/mainboard/lenovo/t530/devicetree.cb
M src/mainboard/lenovo/t530/variants/t530/overridetree.cb
M src/mainboard/lenovo/t530/variants/w530/overridetree.cb
3 files changed, 32 insertions(+), 32 deletions(-)
Approvals:
Patrick Rudolph: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index becc357..b8dcfd0 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -18,9 +18,9 @@
device domain 0 on
subsystemid 0x17aa 0x21f6 inherit
- device ref host_bridge on end # Host bridge
- device ref peg10 on end # PCIe bridge for discrete graphics
- device ref igd on end # Internal graphics VGA controller
+ device ref host_bridge on end
+ device ref peg10 on end # discrete graphics
+ device ref igd on end
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
# GPI routing
@@ -53,29 +53,29 @@
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
- device ref xhci on end # USB 3.0 Controller
- device ref mei1 on end # Management Engine Interface 1
- device ref mei2 off end # Management Engine Interface 2
- device ref me_ide_r off end # Management Engine IDE-R
- device ref me_kt off end # Management Engine KT
- device ref gbe on # Intel Gigabit Ethernet
+ device ref xhci on end
+ device ref mei1 on end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe on
subsystemid 0x17aa 0x21f3
end
- device ref ehci2 on end # USB2 EHCI #2
- device ref hda on end # High Definition Audio
- device ref pcie_rp1 on end # PCIe Port #1
- device ref pcie_rp2 on end # PCIe Port #2
- device ref pcie_rp3 on # PCIe Port #3
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp2 on end
+ device ref pcie_rp3 on
smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
end
- device ref pcie_rp4 off end # PCIe Port #4
- device ref pcie_rp5 off end # PCIe Port #5
- device ref pcie_rp6 off end # PCIe Port #6
- device ref pcie_rp7 off end # PCIe Port #7
- device ref pcie_rp8 off end # PCIe Port #8
- device ref ehci1 on end # USB2 EHCI #1
- device ref pci_bridge off end # PCI bridge
- device ref lpc on # PCI-LPC bridge
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 off end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
chip ec/lenovo/pmh7
device pnp ff.1 on end # dummy
register "backlight_enable" = "true"
@@ -137,8 +137,8 @@
register "has_thinker1" = "1"
end
end
- device ref sata1 on end # SATA Controller 1
- device ref smbus on # SMBus
+ device ref sata1 on end
+ device ref smbus on
# eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c
device i2c 54 on end
@@ -151,8 +151,8 @@
device i2c 5f on end
end
end
- device ref sata2 off end # SATA Controller 2
- device ref thermal on end # Thermal
+ device ref sata2 off end
+ device ref thermal on end
end
end
end
diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb
index fda8aef..b574f36 100644
--- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb
+++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb
@@ -2,7 +2,7 @@
register "spd_addresses" = "{0x50, 0, 0x51, 0}"
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
- device ref lpc on # PCI-LPC bridge
+ device ref lpc on
chip ec/lenovo/h8
device pnp ff.2 on end # dummy
register "has_wwan_detection" = "1"
diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb
index 2029dc3..6b86387 100644
--- a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb
+++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb
@@ -1,26 +1,26 @@
chip northbridge/intel/sandybridge
register "spd_addresses" = "{0x50, 0x52, 0x51, 0x53}"
device domain 0 on
- device ref igd on # Internal graphics VGA controller
+ device ref igd on
subsystemid 0x17aa 0x21f5
end
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
- device ref me_kt on end # Management Engine KT
- device ref pcie_rp1 on # PCIe Port #1
+ device ref me_kt on end
+ device ref pcie_rp1 on
chip drivers/ricoh/rce822 # Ricoh cardreader
register "disable_mask" = "0x83"
register "sdwppol" = "1"
device pci 00.0 on end # Ricoh SD card reader
end
end
- device ref lpc on # PCI-LPC bridge
+ device ref lpc on
chip ec/lenovo/h8
device pnp ff.2 on end # dummy
register "config1" = "0x01"
register "config3" = "0xe2"
end
end
- device ref thermal off end # Thermal
+ device ref thermal off end
end
end
end
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Change subject: mb/hp/snb_ivb_desktops: Convert remaining PCI numbers into references
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/lenovo/x230: Remove superfluous comments related to PCI devices
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/lenovo/t430: Remove superfluous comments related to PCI devices
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/lenovo/t530: Remove superfluous comments related to PCI devices
......................................................................
Patch Set 4: Code-Review+2
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Change subject: intel skl mainboards: Move PcieRpEnable option below dt entries
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Then how do people review this patch pretending that all devicetrees have been checked
We don't have to pretend anything. On EHL, I just checked them. Fair enough, on SKL there's more of them so it's not *that* easy.
> They need to go through all .cb files from that platform and compare the option with the devicetree.
Exactly - I have seen this as one-time effort not worth automation. But I don't want to not stand in your way.
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Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78332?usp=email )
Change subject: soc/intel/xeon_sp: Scan and allocate resources on all stacks
......................................................................
Patch Set 13:
(3 comments)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/78332/comment/e6cac989_3660c5fd :
PS13, Line 108: if (ioapic_base == 0)
the SPR HOB returns ineffective IOAPIC range as 0xFFFFFFFF..0x00000000 and here an update is needed accordingly
File src/soc/intel/xeon_sp/chip_common.c:
https://review.coreboot.org/c/coreboot/+/78332/comment/8df364d1_71a80476 :
PS13, Line 112: if (ri->BusBase < ri->BusLimit)
a fixes is needed: ri->BusBase > ri->BusLimit
File src/soc/intel/xeon_sp/util.c:
https://review.coreboot.org/c/coreboot/+/78332/comment/00c4343c_b81eba13 :
PS12, Line 118: if (!is_pcie_iio_stack_res(ri))
> Should we remove ln 118 so that all stack info will be returned? […]
From CPX semantics point of view, stack_needs_resource_alloc equals to is_pcie_iio_stack_res, but from the API semantics point of view, get_iiostack_info are not restricted to return PCIe IIO stack only. Maybe we could move this API as CPX only.
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Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80139?usp=email )
Change subject: util/crossgcc/buildgcc: Compile RISC-V GCC with medany
......................................................................
util/crossgcc/buildgcc: Compile RISC-V GCC with medany
currently the HiFive Unmatched mainboard produces the following error:
util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/rv64imafdc/lp64d/libgcc.a(_clzsi2.o): in function `__clzdi2':
util/crossgcc/build-riscv64-elf-GCC/riscv64-elf/rv64imafdc/lp64d/libgcc/../../../../../gcc-13.2.0/libgcc/libgcc2.c:690:(.text+0x1e): relocation truncated to fit: R_RISCV_HI20 against symbol `__clz_tab' defined in .rodata section in /home/max/coreboot/coreboot-alderlake-p/util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/rv64imafdc/lp64d/libgcc.a(_clz.o)
This is due to the fact that the libgcc.a library is compiled with the
medlow code model but the mainboards are compiled with the medany code
model.
Changing the code model of the GCC libraries to the medany code model
fixes the issue.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: If5f07ce034686dd7fec160ea76838507c0ba7fa0
---
M util/crossgcc/buildgcc
1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/80139/1
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 23a5caf..d200378 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -774,6 +774,11 @@
[ -n "$CXX" ] && $CXX --version | grep clang >/dev/null 2>&1 && \
CLANGCXXFLAGS="-fbracket-depth=1024"
+ # standard code model is medlow but all mainboards are compiled with medany code model
+ if [ "${TARGETARCH}" = "riscv64-elf" ]; then
+ CFLAGS_FOR_TARGET_EXTRA="-mcmodel=medany"
+ fi
+
# GCC does not honor HOSTCFLAGS at all. CFLAGS are used for
# both target and host object files.
# There's a work-around called CFLAGS_FOR_BUILD and CFLAGS_FOR_TARGET
@@ -783,7 +788,7 @@
# using C++.
# shellcheck disable=SC2086
CC="$(hostcc target)" CXX="$(hostcxx target)" \
- CFLAGS_FOR_TARGET="-O2 -Dinhibit_libc" \
+ CFLAGS_FOR_TARGET="${CFLAGS_FOR_TARGET_EXTRA} -O2 -Dinhibit_libc" \
CFLAGS="$HOSTCFLAGS $CLANGFLAGS" \
CFLAGS_FOR_BUILD="$HOSTCFLAGS $CLANGFLAGS" \
CXXFLAGS="$HOSTCFLAGS $CLANGCXXFLAGS" \
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80022?usp=email )
Change subject: mb/siemens/chili: Use chipset dt reference names
......................................................................
mb/siemens/chili: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: Ic3a4c85ec6bfdc858f9b6f79b114cf612ad3a153
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80022
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/mainboard/siemens/chili/variants/base/devicetree.cb
M src/mainboard/siemens/chili/variants/chili/devicetree.cb
2 files changed, 138 insertions(+), 138 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, but someone else must approve
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb
index 8d6c589..4bc9b5f 100644
--- a/src/mainboard/siemens/chili/variants/base/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb
@@ -10,19 +10,19 @@
device cpu_cluster 0 on end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 01.0 off end # PCIe x16
- device pci 01.1 off end # PCIe x8
- device pci 01.2 off end # PCIe x4
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 on end # SA Thermal device
- device pci 05.0 off end # Imaging Processing Unit
- device pci 08.0 off end # Gaussian mixture model, Neural network accelerator
- device pci 12.0 on end # Thermal Subsystem
- device pci 12.5 off end # UFS SCS
- device pci 12.6 off end # GSPI #2
- device pci 13.0 off end # ISH
- device pci 14.0 on # USB xHCI
+ device ref system_agent on end
+ device ref peg0 off end
+ device ref peg1 off end
+ device ref peg2 off end
+ device ref igpu on end
+ device ref dptf on end
+ device ref ipu off end
+ device ref gna off end
+ device ref thermal on end
+ device ref ufs off end
+ device ref gspi2 off end
+ device ref ish off end
+ device ref xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C?
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # single blue
@@ -37,21 +37,21 @@
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage?
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue
end
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.2 on end # Shared SRAM
- device pci 14.3 off end # CNVi Wifi
- device pci 14.5 off end # SDCard
- device pci 15.0 off end # I2C #0
- device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 16.5 off end # Management Engine Interface 4
- device pci 17.0 on # SATA
+ device ref xdci off end
+ device ref shared_sram on end
+ device ref cnvi_wifi off end
+ device ref sdxc off end
+ device ref i2c0 off end
+ device ref i2c1 off end
+ device ref i2c2 off end
+ device ref i2c3 off end
+ device ref heci1 on end
+ device ref heci2 off end
+ device ref csme_ider off end
+ device ref csme_ktr off end
+ device ref heci3 off end
+ device ref heci4 off end
+ device ref sata on
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "1" # HDD / SSD
register "SataPortsEnable[1]" = "1" # ODD
@@ -60,71 +60,71 @@
register "SataPortsDevSlp[0]" = "1" # M.2
register "SataPortsDevSlp[2]" = "1" # HDD / SSD
end
- device pci 19.0 off end # I2C #4
- device pci 19.1 off end # I2C #5
- device pci 19.2 off end # UART #2
- device pci 1a.0 off end # eMMC
- device pci 1c.0 off end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 on # PCI Express Port 5
+ device ref i2c4 off end
+ device ref i2c5 off end
+ device ref uart2 off end
+ device ref emmc off end
+ device ref pcie_rp1 off end
+ device ref pcie_rp2 off end
+ device ref pcie_rp3 off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 on
device pci 00.0 on end # x1 i219
register "PcieRpEnable[4]" = "1"
register "PcieClkSrcUsage[4]" = "0x70"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieRpSlotImplemented[4]" = "0"
end
- device pci 1c.5 on # PCI Express Port 6
+ device ref pcie_rp6 on
device pci 00.0 on end # x1 i210
register "PcieRpEnable[5]" = "1"
register "PcieClkSrcUsage[5]" = "5"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieRpSlotImplemented[5]" = "0"
end
- device pci 1c.6 on # PCI Express Port 7
+ device ref pcie_rp7 on
register "PcieRpEnable[6]" = "1"
register "PcieRpSlotImplemented[6]" = "1"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 off end # PCI Express Port 9
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 off end # PCI Express Port 13
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1b.0 on # PCI Express Port 17
+ device ref pcie_rp8 off end
+ device ref pcie_rp9 off end
+ device ref pcie_rp10 off end
+ device ref pcie_rp11 off end
+ device ref pcie_rp12 off end
+ device ref pcie_rp13 off end
+ device ref pcie_rp14 off end
+ device ref pcie_rp15 off end
+ device ref pcie_rp16 off end
+ device ref pcie_rp17 on
register "PcieRpEnable[16]" = "1"
register "PcieClkSrcUsage[7]" = "16"
register "PcieClkSrcClkReq[7]" = "7"
register "PcieRpSlotImplemented[16]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device pci 1b.1 off end # PCI Express Port 18
- device pci 1b.2 off end # PCI Express Port 19
- device pci 1b.3 off end # PCI Express Port 20
- device pci 1b.4 off end # PCI Express Port 21
- device pci 1b.5 off end # PCI Express Port 22
- device pci 1b.6 off end # PCI Express Port 23
- device pci 1b.7 off end # PCI Express Port 24
- device pci 1e.0 off end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on # LPC Interface
+ device ref pcie_rp18 off end
+ device ref pcie_rp19 off end
+ device ref pcie_rp20 off end
+ device ref pcie_rp21 off end
+ device ref pcie_rp22 off end
+ device ref pcie_rp23 off end
+ device ref pcie_rp24 off end
+ device ref uart0 off end
+ device ref uart1 off end
+ device ref gspi0 off end
+ device ref gspi1 off end
+ device ref lpc_espi on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
- device pci 1f.1 hidden end # P2SB
- device pci 1f.2 hidden end # Power Management Controller
- device pci 1f.3 on end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 on end # GbE
- device pci 1f.7 off end # TraceHub
+ device ref p2sb hidden end
+ device ref pmc hidden end
+ device ref hda on end
+ device ref smbus on end
+ device ref fast_spi on end
+ device ref gbe on end
+ device ref tracehub off end
end
end
diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
index cee1967..b514d74 100644
--- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
@@ -10,19 +10,19 @@
device cpu_cluster 0 on end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 01.0 off end # PCIe x16
- device pci 01.1 off end # PCIe x8
- device pci 01.2 off end # PCIe x4
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 on end # SA Thermal device
- device pci 05.0 off end # Imaging Processing Unit
- device pci 08.0 off end # Gaussian mixture model, Neural network accelerator
- device pci 12.0 on end # Thermal Subsystem
- device pci 12.5 off end # UFS SCS
- device pci 12.6 off end # GSPI #2
- device pci 13.0 off end # ISH
- device pci 14.0 on # USB xHCI
+ device ref system_agent on end
+ device ref peg0 off end
+ device ref peg1 off end
+ device ref peg2 off end
+ device ref igpu on end
+ device ref dptf on end
+ device ref ipu off end
+ device ref gna off end
+ device ref thermal on end
+ device ref ufs off end
+ device ref gspi2 off end
+ device ref ish off end
+ device ref xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Debug
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # ReinerSCT
@@ -30,11 +30,11 @@
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Debug
end
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.2 on end # Shared SRAM
- device pci 14.3 off end # CNVi Wifi
- device pci 14.5 off end # SDCard
- device pci 15.0 on # I2C #0
+ device ref xdci off end
+ device ref shared_sram on end
+ device ref cnvi_wifi off end
+ device ref sdxc off end
+ device ref i2c0 on
chip drivers/secunet/dmi
device i2c 0x57 on end # Serial EEPROM
end
@@ -94,92 +94,92 @@
}"
end
end
- device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 16.5 off end # Management Engine Interface 4
- device pci 17.0 off end # SATA
- device pci 19.0 off end # I2C #4
- device pci 19.1 off end # I2C #5
- device pci 19.2 off end # UART #2
- device pci 1a.0 off end # eMMC
- device pci 1c.0 off # PCI Express Port 1
+ device ref i2c1 off end
+ device ref i2c2 off end
+ device ref i2c3 off end
+ device ref heci1 on end
+ device ref heci2 off end
+ device ref csme_ider off end
+ device ref csme_ktr off end
+ device ref heci3 off end
+ device ref heci4 off end
+ device ref sata off end
+ device ref i2c4 off end
+ device ref i2c5 off end
+ device ref uart2 off end
+ device ref emmc off end
+ device ref pcie_rp1 off
register "PcieRpEnable[0]" = "0" # Debug (x1)
register "PcieClkSrcUsage[2]" = "0"
register "PcieClkSrcClkReq[2]" = "2"
end
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 on # PCI Express Port 5
+ device ref pcie_rp2 off end
+ device ref pcie_rp3 off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 on
register "PcieRpEnable[4]" = "1" # CORE (x1)
register "PcieClkSrcUsage[4]" = "4"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieRpSlotImplemented[4]" = "1"
end
- device pci 1c.5 on # PCI Express Port 6
+ device ref pcie_rp6 on
device pci 00.0 on end # i210 (x1)
register "PcieRpEnable[5]" = "1"
register "PcieClkSrcUsage[5]" = "5"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieRpSlotImplemented[5]" = "0"
end
- device pci 1c.6 on # PCI Express Port 7
- device pci 00.0 on end # VL805 Front Rack/UIB (x1)
+ device ref pcie_rp7 on
+ device pci 00.0 on end # VL805 Front Rack/UIB (x1)
register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[1]" = "6"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieRpSlotImplemented[6]" = "0"
end
- device pci 1c.7 on # PCI Express Port 8
- device pci 00.0 on end # VL805 Back MB (x1)
+ device ref pcie_rp8 on
+ device pci 00.0 on end # VL805 Back MB (x1)
register "PcieRpEnable[7]" = "1"
register "PcieClkSrcUsage[0]" = "7"
register "PcieClkSrcClkReq[0]" = "0"
register "PcieRpSlotImplemented[7]" = "0"
end
- device pci 1d.0 off end # PCI Express Port 9
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 off end # PCI Express Port 13
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1b.0 on # PCI Express Port 17
+ device ref pcie_rp9 off end
+ device ref pcie_rp10 off end
+ device ref pcie_rp11 off end
+ device ref pcie_rp12 off end
+ device ref pcie_rp13 off end
+ device ref pcie_rp14 off end
+ device ref pcie_rp15 off end
+ device ref pcie_rp16 off end
+ device ref pcie_rp17 on
register "PcieRpEnable[16]" = "1" # NVMe (x4)
register "PcieClkSrcUsage[7]" = "16"
register "PcieClkSrcClkReq[7]" = "7"
register "PcieRpSlotImplemented[16]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
end
- device pci 1b.1 off end # PCI Express Port 18
- device pci 1b.2 off end # PCI Express Port 19
- device pci 1b.3 off end # PCI Express Port 20
- device pci 1b.4 off end # PCI Express Port 21
- device pci 1b.5 off end # PCI Express Port 22
- device pci 1b.6 off end # PCI Express Port 23
- device pci 1b.7 off end # PCI Express Port 24
- device pci 1e.0 on end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on # LPC Interface
+ device ref pcie_rp18 off end
+ device ref pcie_rp19 off end
+ device ref pcie_rp20 off end
+ device ref pcie_rp21 off end
+ device ref pcie_rp22 off end
+ device ref pcie_rp23 off end
+ device ref pcie_rp24 off end
+ device ref uart0 on end
+ device ref uart1 off end
+ device ref gspi0 off end
+ device ref gspi1 off end
+ device ref lpc_espi on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
- device pci 1f.1 hidden end # P2SB
- device pci 1f.2 hidden end # Power Management Controller
- device pci 1f.3 on end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
- device pci 1f.7 off end # TraceHub
+ device ref p2sb hidden end
+ device ref pmc hidden end
+ device ref hda on end
+ device ref smbus on end
+ device ref fast_spi on end
+ device ref gbe off end
+ device ref tracehub off end
end
end
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ic3a4c85ec6bfdc858f9b6f79b114cf612ad3a153
Gerrit-Change-Number: 80022
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged