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Change subject: soc/intel/xeon_sp: Support multiple PCI segment groups
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
> After I set CONFIG_ECAM_SEGMENT_COUNT to 1, I see build error for AC: […]
I'll rebase on main. It would be nice to get https://review.coreboot.org/c/coreboot/+/78333 in first to simplify the modifications needed for PCI segment group support.
File src/soc/intel/xeon_sp/spr/soc_acpi.c:
https://review.coreboot.org/c/coreboot/+/79878/comment/29107f97_ba98e837 :
PS2, Line 256: stack_enabled = false;
> shouldn't we continue here?
No, as that would leave the DSDT with missing resources. The OS' AML interpreter will complain that tres doesn't exist.
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Change subject: device/device.h: Drop multiple links
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
Arthur, a major rebase is needed for this patch, will it be handled recently?
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Change subject: soc/intel/xeon_sp: Support multiple PCI segment groups
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/spr/soc_acpi.c:
https://review.coreboot.org/c/coreboot/+/79878/comment/58b73c87_bc324ec1 :
PS2, Line 256: stack_enabled = false;
shouldn't we continue here?
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80047?usp=email )
Change subject: mb/hp/snb_ivb_desktops: Remove superfluous comments about PCI devices
......................................................................
mb/hp/snb_ivb_desktops: Remove superfluous comments about PCI devices
Since all devicetrees from hp/snb_ivb_desktops are using the reference
names for PCI devices now, remove the equivalent comments documenting
their function.
Change-Id: I0974052c6c18f54b588d296c5c5d11e930f0fcd7
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80047
Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/hp/snb_ivb_desktops/devicetree.cb
M src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
2 files changed, 34 insertions(+), 34 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/hp/snb_ivb_desktops/devicetree.cb b/src/mainboard/hp/snb_ivb_desktops/devicetree.cb
index f02ff76..d1aa576 100644
--- a/src/mainboard/hp/snb_ivb_desktops/devicetree.cb
+++ b/src/mainboard/hp/snb_ivb_desktops/devicetree.cb
@@ -11,10 +11,10 @@
device domain 0 on
subsystemid 0x103c 0x1791 inherit
- device ref host_bridge on end # Host bridge Host bridge
- device ref peg10 on end # PCIe Bridge for discrete graphics
- device ref igd on end # Internal graphics VGA controller
- device ref peg60 off end # Extra x4 port on north bridge
+ device ref host_bridge on end
+ device ref peg10 on end
+ device ref igd on end
+ device ref peg60 off end
chip southbridge/intel/bd82x6x # Intel Series 7 PCH
register "docking_supported" = "0"
@@ -29,25 +29,25 @@
register "xhci_switchable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x0000000f"
- device ref xhci on end # xHCI
- device ref mei1 on end # Management Engine Interface 1
- device ref mei2 off end # Management Engine Interface 2
- device ref me_ide_r off end # Management Engine IDE-R
- device ref me_kt on end # Management Engine KT
- device ref gbe on end # Intel Gigabit Ethernet
- device ref ehci2 on end # USB2 EHCI #2
- device ref hda on end # High Definition Audio controller
- device ref pcie_rp1 on end # PCIe Port #1
- device ref pcie_rp2 off end # PCIe Port #2
- device ref pcie_rp3 off end # PCIe Port #3
- device ref pcie_rp4 off end # PCIe Port #4
- device ref pcie_rp5 on end # PCIe Port #5
- device ref pcie_rp6 off end # PCIe Port #6
- device ref pcie_rp7 off end # PCIe Port #7
- device ref pcie_rp8 off end # PCIe Port #8
- device ref ehci1 on end # USB2 EHCI #1
- device ref pci_bridge on end # PCI bridge
- device ref lpc on # LPC bridge PCI-LPC bridge
+ device ref xhci on end
+ device ref mei1 on end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt on end
+ device ref gbe on end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp2 off end
+ device ref pcie_rp3 off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 on end
+ device ref pcie_rp6 off end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge on end
+ device ref lpc on
chip superio/common
device pnp 2e.ff on # passes SIO base addr to SSDT gen
chip superio/nuvoton/npcd378
@@ -152,10 +152,10 @@
device pnp 4e.0 on end # TPM module
end
end
- device ref sata1 on end # SATA Controller 1
- device ref smbus on end # SMBus
- device ref sata2 off end # SATA Controller 2
- device ref thermal off end # Thermal
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
end
end
end
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
index 3634b90..b82ff8a 100644
--- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
@@ -3,16 +3,16 @@
chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x103c 0x1791 inherit
- device ref peg60 on end # Extra x4 port on north bridge
+ device ref peg60 on end
chip southbridge/intel/bd82x6x
register "sata_port_map" = "0x3f"
- device ref pcie_rp2 on end # PCIe Port #2
- device ref pcie_rp3 on end # PCIe Port #3
- device ref pcie_rp4 on end # PCIe Port #4
- device ref pcie_rp6 on end # PCIe Port #6
- device ref pcie_rp7 on end # PCIe Port #7
- device ref pcie_rp8 on end # PCIe Port #8
+ device ref pcie_rp2 on end
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 on end
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 on end
+ device ref pcie_rp8 on end
end
end
end
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Change subject: mb/hp/snb_ivb_desktops: Convert remaining PCI numbers into references
......................................................................
mb/hp/snb_ivb_desktops: Convert remaining PCI numbers into references
Change-Id: I31e348ba5954bc463f43e769ddb4aed413faf193
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
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---
M src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
M src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb
2 files changed, 8 insertions(+), 8 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
index 55bdaac..3634b90 100644
--- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
@@ -3,16 +3,16 @@
chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x103c 0x1791 inherit
- device pci 06.0 on end # Extra x4 port on north bridge
+ device ref peg60 on end # Extra x4 port on north bridge
chip southbridge/intel/bd82x6x
register "sata_port_map" = "0x3f"
- device pci 1c.1 on end # PCIe Port #2
- device pci 1c.2 on end # PCIe Port #3
- device pci 1c.3 on end # PCIe Port #4
- device pci 1c.5 on end # PCIe Port #6
- device pci 1c.6 on end # PCIe Port #7
- device pci 1c.7 on end # PCIe Port #8
+ device ref pcie_rp2 on end # PCIe Port #2
+ device ref pcie_rp3 on end # PCIe Port #3
+ device ref pcie_rp4 on end # PCIe Port #4
+ device ref pcie_rp6 on end # PCIe Port #6
+ device ref pcie_rp7 on end # PCIe Port #7
+ device ref pcie_rp8 on end # PCIe Port #8
end
end
end
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb
index c31bf33..8b827f8 100644
--- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb
@@ -6,7 +6,7 @@
chip southbridge/intel/bd82x6x
register "sata_port_map" = "0xf"
- device pci 1c.4 on end # dummy setting
+ device ref pcie_rp5 on end # dummy setting
end
end
end
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Change subject: soc/intel/xeon_sp: Scan and allocate resources on all stacks
......................................................................
Patch Set 14: Code-Review+1
(1 comment)
Patchset:
PS14:
revised and tested. pass in archercity
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Shuo Liu has uploaded a new patch set (#14) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/78332?usp=email )
Change subject: soc/intel/xeon_sp: Scan and allocate resources on all stacks
......................................................................
soc/intel/xeon_sp: Scan and allocate resources on all stacks
The code can now deal with stacks that have no resources so just hook
them all up.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Change-Id: Id72c6e4499e99df3b7ca821ab2893cbcc869dbcd
---
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/util.c
8 files changed, 28 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/78332/14
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Change subject: mb/lenovo/x230: Remove superfluous comments related to PCI devices
......................................................................
mb/lenovo/x230: Remove superfluous comments related to PCI devices
Since all devicetrees from lenovo/x230 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: Ia06f976ef1439377ff22149044feaa3463d2aeb8
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79964
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/mainboard/lenovo/x230/devicetree.cb
M src/mainboard/lenovo/x230/variants/x230/overridetree.cb
M src/mainboard/lenovo/x230/variants/x230s/overridetree.cb
3 files changed, 32 insertions(+), 32 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 52a2e70..f47e3b7 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -19,9 +19,9 @@
device domain 0 on
subsystemid 0x17aa 0x21fa inherit
- device ref host_bridge on end # host bridge
- device ref peg10 off end # PCIe Bridge for discrete graphics
- device ref igd on end # vga controller
+ device ref host_bridge on end
+ device ref peg10 off end
+ device ref igd on end
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing
@@ -52,33 +52,33 @@
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
- device ref xhci on end # USB 3.0 Controller
- device ref mei1 on end # Management Engine Interface 1
- device ref mei2 off end # Management Engine Interface 2
- device ref me_ide_r off end # Management Engine IDE-R
- device ref me_kt off end # Management Engine KT
+ device ref xhci on end
+ device ref mei1 on end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
device ref gbe on
subsystemid 0x17aa 0x21f3
- end # Intel Gigabit Ethernet
- device ref ehci2 on end # USB2 EHCI #2
- device ref hda on end # High Definition Audio
+ end
+ device ref ehci2 on end
+ device ref hda on end
device ref pcie_rp1 on
chip drivers/ricoh/rce822
register "sdwppol" = "1"
register "disable_mask" = "0x87"
device pci 00.0 on end
end
- end # PCIe Port #1
- device ref pcie_rp2 on end # PCIe Port #2
- device ref pcie_rp3 off end # PCIe Port #3
- device ref pcie_rp4 off end # PCIe Port #4
- device ref pcie_rp5 off end # PCIe Port #5
- device ref pcie_rp6 off end # PCIe Port #6
- device ref pcie_rp7 off end # PCIe Port #7
- device ref pcie_rp8 off end # PCIe Port #8
- device ref ehci1 on end # USB2 EHCI #1
- device ref pci_bridge off end # PCI bridge
- device ref lpc on #LPC bridge
+ end
+ device ref pcie_rp2 on end
+ device ref pcie_rp3 off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 off end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
chip ec/lenovo/pmh7
device pnp ff.1 on end # dummy
register "backlight_enable" = "true"
@@ -130,8 +130,8 @@
register "wwan_gpio_num" = "70"
register "wwan_gpio_lvl" = "0"
end
- end # LPC bridge
- device ref sata1 on end # SATA Controller 1
+ end
+ device ref sata1 on end
device ref smbus on
# eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c
@@ -144,9 +144,9 @@
device i2c 5e on end
device i2c 5f on end
end
- end # SMBus
- device ref sata2 off end # SATA Controller 2
- device ref thermal on end # Thermal
+ end
+ device ref sata2 off end
+ device ref thermal on end
end
end
end
diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb
index 487bdfe..d82faae 100644
--- a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb
+++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb
@@ -5,13 +5,13 @@
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
device ref pcie_rp3 on
smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
- end # PCIe Port #3 (expresscard)
- device ref lpc on # LPC bridge
+ end
+ device ref lpc on
chip ec/lenovo/h8
register "eventa_enable" = "0x01"
device pnp ff.2 on end
end
- end # LPC Controller
+ end
end
end
end
diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb
index e30062a..09e7f92 100644
--- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb
+++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb
@@ -19,7 +19,7 @@
# Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA)
register "sata_port_map" = "0x3"
- device ref lpc on # LPC bridge
+ device ref lpc on
chip ec/lenovo/h8
register "config1" = "0x05"
register "config3" = "0xc4"
@@ -29,7 +29,7 @@
register "has_bdc_detection" = "0"
device pnp ff.2 on end
end
- end # LPC Controller
+ end
end
end
end
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ia06f976ef1439377ff22149044feaa3463d2aeb8
Gerrit-Change-Number: 79964
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79942?usp=email )
Change subject: mb/lenovo/t430: Remove superfluous comments related to PCI devices
......................................................................
mb/lenovo/t430: Remove superfluous comments related to PCI devices
Since all devicetrees from lenovo/t430 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.
Change-Id: I84f432e89c41a02115715f7f1b56123dd0d81171
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79942
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/mainboard/lenovo/t430s/devicetree.cb
M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
M src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb
3 files changed, 33 insertions(+), 33 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb
index 23a41d6..10a388a 100644
--- a/src/mainboard/lenovo/t430s/devicetree.cb
+++ b/src/mainboard/lenovo/t430s/devicetree.cb
@@ -17,9 +17,9 @@
device domain 0 on
subsystemid 0x17aa 0x21fb inherit
- device ref host_bridge on end # host bridge
- device ref peg10 on end # PCIe Bridge for discrete graphics
- device ref igd on end # Integrated Graphics Controller
+ device ref host_bridge on end
+ device ref peg10 on end # Discrete graphics
+ device ref igd on end
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
# GPI routing
@@ -52,28 +52,28 @@
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
- device ref xhci on end # USB 3.0 Controller
- device ref mei1 on end # Management Engine Interface 1
- device ref mei2 off end # Management Engine Interface 2
- device ref me_ide_r off end # Management Engine IDE-R
- device ref me_kt off end # Management Engine KT
+ device ref xhci on end
+ device ref mei1 on end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
device ref gbe on
subsystemid 0x17aa 0x21f3
- end # Intel Gigabit Ethernet
- device ref ehci2 on end # USB Enhanced Host Controller #2
- device ref hda on end # High Definition Audio Controller
- device ref pcie_rp1 off end # PCIe Port #1
- device ref pcie_rp2 on end # PCIe Port #2 Integrated Wireless LAN
+ end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 off end
+ device ref pcie_rp2 on end # Integrated Wireless LAN
device ref pcie_rp3 on
smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
- end # PCIe Port #3 ExpressCard
- device ref pcie_rp4 off end # PCIe Port #4
- device ref pcie_rp5 off end # PCIe Port #5
- device ref pcie_rp6 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe)
- device ref pcie_rp7 off end # PCIe Port #7
- device ref pcie_rp8 off end # PCIe Port #8
- device ref ehci1 on end # USB Enhanced Host Controller #1
- device ref pci_bridge off end # PCI bridge
+ end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 off end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
device ref lpc on
chip ec/lenovo/pmh7
device pnp ff.1 on end # dummy
@@ -117,8 +117,8 @@
register "eventd_enable" = "0xff"
register "evente_enable" = "0x0d"
end
- end # LPC Controller
- device ref sata1 on end # 6 port SATA AHCI Controller
+ end
+ device ref sata1 on end
device ref smbus on
# eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c
@@ -131,9 +131,9 @@
device i2c 5e on end
device i2c 5f on end
end
- end # SMBus Controller
- device ref sata2 off end # SATA Controller 2
- device ref thermal on end # Thermal
+ end
+ device ref sata2 off end
+ device ref thermal on end
end
end
end
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
index 2515150..5677a87 100644
--- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
+++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb
@@ -4,7 +4,7 @@
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
# Enable hotplug on Port 5 for Thunderbolt controller
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }"
- device ref pcie_rp5 on end # PCIe Port #5 Thunderbolt controller
+ device ref pcie_rp5 on end # Thunderbolt controller
device ref lpc on
chip ec/lenovo/h8
device pnp ff.2 on end # dummy
@@ -12,7 +12,7 @@
register "bdc_gpio_num" = "54"
register "bdc_gpio_lvl" = "0"
end
- end # LPC Controller
+ end
end
end
end
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb
index 3e13627..e839358 100644
--- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb
+++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb
@@ -15,7 +15,7 @@
device domain 0 on
subsystemid 0x17aa 0x2208 inherit
- device ref peg10 off end # PCIe Bridge for discrete graphics
+ device ref peg10 off end # discrete graphics
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
# Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) & 4 (dock)
@@ -23,14 +23,14 @@
# T431s has no Express Card slot.
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
- device ref pcie_rp1 on # PCIe Port #1
+ device ref pcie_rp1 on
chip drivers/ricoh/rce822 # Ricoh cardreader
register "disable_mask" = "0x87"
register "sdwppol" = "0"
device pci 00.0 on end # Ricoh SD card reader
end
end
- device ref pcie_rp3 off end # PCIe Port #3
+ device ref pcie_rp3 off end
device ref lpc on
chip ec/lenovo/h8
device pnp ff.2 on end # dummy
@@ -41,8 +41,8 @@
# T431s only has BT on wlan card
register "has_bdc_detection" = "0"
end
- end # LPC Controller
- device ref thermal off end # Thermal
+ end
+ device ref thermal off end
end
end
end
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I84f432e89c41a02115715f7f1b56123dd0d81171
Gerrit-Change-Number: 79942
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Attention is currently required from: Felix Singer.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80047?usp=email )
Change subject: mb/hp/snb_ivb_desktops: Remove superfluous comments about PCI devices
......................................................................
Patch Set 2: Code-Review+2
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I0974052c6c18f54b588d296c5c5d11e930f0fcd7
Gerrit-Change-Number: 80047
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Comment-Date: Fri, 19 Jan 2024 08:50:38 +0000
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