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Change subject: soc/intel/xeon_sp: Add generic function to locate devices
......................................................................
soc/intel/xeon_sp: Add generic function to locate devices
Provide a helper function to locate PCI devices on a given socket
by their PCI vendor and device IDs.
Change-Id: I266360588548ba579f46b228c4d5b3ae6e39a029
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
2 files changed, 30 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/80094/1
diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c
index cf488c4..f775ad7 100644
--- a/src/soc/intel/xeon_sp/chip_common.c
+++ b/src/soc/intel/xeon_sp/chip_common.c
@@ -20,6 +20,32 @@
return &hob->PlatformData.IIO_resource[dn / MAX_LOGIC_IIO_STACK].StackRes[dn % MAX_LOGIC_IIO_STACK];
}
+/**
+ * Find a device of a given vendor and type for the specified socket.
+ * The function iterates over all PCI domains of the specified socket
+ * and matches the PCI vendor and device ID.
+ *
+ * @param socket The socket where to search for the device.
+ * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel).
+ * @param device A PCI device ID.
+ * @return Pointer to the device struct.
+ */
+struct device *dev_find_device_on_socket(uint8_t socket, u16 vendor, u16 device)
+{
+ struct device *domain, *dev = NULL;
+
+ while ((dev = dev_find_device(vendor, device, dev))) {
+ domain = dev_get_pci_domain(dev);
+ if (!domain)
+ continue;
+ if ((domain->path.domain.domain / MAX_LOGIC_IIO_STACK) != socket)
+ continue;
+ return dev;
+ }
+
+ return NULL;
+}
+
void iio_pci_domain_read_resources(struct device *dev)
{
struct resource *res;
@@ -82,14 +108,14 @@
bus->subordinate = sr->BusBase;
bus->max_subordinate = sr->BusLimit;
- printk(BIOS_SPEW, "Scanning IIO stack %d: busses %x-%x\n", dev->path.domain.domain,
+ printk(BIOS_ERR, "Scanning IIO stack %d: personality: %d busses %x-%x\n", dev->path.domain.domain, sr->Personality,
dev->link_list->secondary, dev->link_list->max_subordinate);
pci_host_bridge_scan_bus(dev);
}
/*
* Used by IIO stacks for PCIe bridges. Those contain 1 PCI host bridges,
- * all the bus numbers on the IIO stack can be used for this bridge
+ * all the bus numbers on the IIO stack can be used for this bridge.
*/
static struct device_operations iio_pcie_domain_ops = {
.read_resources = iio_pci_domain_read_resources,
diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h
index dcfb0a0..eb77203 100644
--- a/src/soc/intel/xeon_sp/include/soc/chip_common.h
+++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h
@@ -9,6 +9,8 @@
void iio_pci_domain_scan_bus(struct device *dev);
void attach_stacks(struct device *dev);
+struct device *dev_find_device_on_socket(uint8_t socket, u16 vendor, u16 device);
+
void soc_create_ioat_domains(struct bus *bus, const STACK_RES *sr);
#endif /* _CHIP_COMMON_H_ */
--
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Change subject: soc/intel/xeon_sp: Find VTD devices by PCI DEV ID
......................................................................
soc/intel/xeon_sp: Find VTD devices by PCI DEV ID
Instead of manually crafting S:B:D:F numbers for every
VTD device loop over the entire devicetree by PCI DEV IDs.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa96
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/memmap.c
1 file changed, 10 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/80092/1
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
index e73143f..8fe21e8 100644
--- a/src/soc/intel/xeon_sp/memmap.c
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -4,6 +4,7 @@
#include <cbmem.h>
#include <console/console.h>
#include <device/pci_ops.h>
+#include <device/pci_ids.h>
#include <cpu/x86/smm.h>
#include <soc/soc_util.h>
#include <soc/pci_devs.h>
@@ -53,7 +54,6 @@
#if !defined(__SIMPLE_DEVICE__)
union dpr_register txt_get_chipset_dpr(void)
{
- const IIO_UDS *hob = get_iio_uds();
union dpr_register dpr;
struct device *dev = VTD_DEV(0);
@@ -66,31 +66,15 @@
dpr.raw = pci_read_config32(dev, VTD_LTDPR);
- /* Compare the LTDPR register on all iio stacks */
- for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) {
- if (!soc_cpu_is_enabled(socket))
- continue;
- iio++;
- for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
- const STACK_RES *ri =
- &hob->PlatformData.IIO_resource[socket].StackRes[stack];
- if (!stack_needs_resource_alloc(ri))
- continue;
- uint8_t bus = ri->BusBase;
- dev = VTD_DEV(bus);
-
- if (!dev) {
- printk(BIOS_ERR, "BUS %x: Unable to find VTD PCI dev\n", bus);
- dpr.raw = 0;
- return dpr;
- }
-
- union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
- if (dpr.raw != test_dpr.raw) {
- printk(BIOS_ERR, "LTDPR not the same on all IIO's");
- dpr.raw = 0;
- return dpr;
- }
+ dev = NULL;
+ /* Look for VTD devices on all sockets */
+ while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_STACK_CFG_REG_DEVID, dev))) {
+ /* Compare the LTDPR register on all iio stacks */
+ union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
+ if (dpr.raw != test_dpr.raw) {
+ printk(BIOS_ERR, "LTDPR not the same on all IIO's");
+ dpr.raw = 0;
+ return dpr;
}
}
return dpr;
--
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Change subject: soc/intel/xeon_sp: Attach more stacks
......................................................................
soc/intel/xeon_sp: Attach more stacks
Attach UBOX stacks as well and thus rename the function to
attack_stacks. In order to use PCI drivers for UBOX devices,
locating UBOX devices by vendor and device IDs and replacing device
access by specifying S:B:D:F numbers, add a PCI domain for the UBOX
stacks and let the PCI enumerator index all devices.
Since there are no PCI BARs on the UBOX bus the PCI locator doesn't
have to assign resources on those buses.
Once all PCI devices on the UBOX stack can be located without knowing
their UBOX bus number and PCI segment the Xeon-SP code can fully
enable the multi PCI segment group support.
Test: ibm/sbp1 (4S) is able to find all PCU devices by PCI ID.
Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/skx/chip.c
M src/soc/intel/xeon_sp/spr/chip.c
5 files changed, 50 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/80091/1
diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c
index 0411a03..cf488c4 100644
--- a/src/soc/intel/xeon_sp/chip_common.c
+++ b/src/soc/intel/xeon_sp/chip_common.c
@@ -97,9 +97,27 @@
.scan_bus = iio_pci_domain_scan_bus,
};
-/* Attach IIO stack as domains */
-void attach_iio_stacks(struct device *dev)
+static void ubox_pci_domain_scan_bus(struct device *dev)
{
+ for (struct bus *link = dev->link_list; link; link = link->next)
+ pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff);
+}
+
+/*
+ * Used by UBOX stacks. Those contain 1 PCI host bridges,
+ * all the bus numbers on the stack can be used for this bridge.
+ */
+static struct device_operations ubox_pcie_domain_ops = {
+ .read_resources = noop_read_resources,
+ .set_resources = noop_set_resources,
+ .scan_bus = ubox_pci_domain_scan_bus,
+};
+
+/* Attach stack as domains */
+void attach_stacks(struct device *dev)
+{
+ struct device_path path;
+ struct device *iio_domain;
const IIO_UDS *hob = get_iio_uds();
if (!hob)
return;
@@ -110,22 +128,35 @@
continue;
const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
- if (!stack_needs_resource_alloc(ri))
+ printk(BIOS_ERR, "Attach socket: %d, stack %d: personality: %d busses %x-%x\n", s, x, ri->Personality, ri->BusBase, ri->BusLimit);
+
+ if (ri->Personality >= TYPE_RESERVED)
continue;
- if (!is_pcie_iio_stack_res(ri)) {
- if (CONFIG(HAVE_IOAT_DOMAINS))
- soc_create_ioat_domains(dev->bus, ri);
- continue;
- }
+ if (is_pcie_iio_stack_res(ri) || ri->Personality == TYPE_UBOX) {
+ path.type = DEVICE_PATH_DOMAIN;
+ path.domain.domain = s * MAX_LOGIC_IIO_STACK + x;
+ iio_domain = alloc_dev(dev->bus, &path);
+ if (iio_domain == NULL)
+ die("%s: out of memory.\n", __func__);
- struct device_path path;
- path.type = DEVICE_PATH_DOMAIN;
- path.domain.domain = s * MAX_LOGIC_IIO_STACK + x;
- struct device *iio_domain = alloc_dev(dev->bus, &path);
- if (iio_domain == NULL)
- die("%s: out of memory.\n", __func__);
- iio_domain->ops = &iio_pcie_domain_ops;
+ if (is_pcie_iio_stack_res(ri)) {
+ iio_domain->ops = &iio_pcie_domain_ops;
+ } else {
+ int i;
+ add_more_links(iio_domain, ri->BusLimit - ri->BusBase + 1);
+
+ i = ri->BusBase;
+ for (struct bus *link = iio_domain->link_list; link; link = link->next, i++) {
+ link->secondary = i;
+ link->subordinate = link->secondary;
+ link->max_subordinate = link->secondary;
+ }
+
+ iio_domain->ops = &ubox_pcie_domain_ops;
+ }
+ } else if (stack_needs_resource_alloc(ri) && CONFIG(HAVE_IOAT_DOMAINS))
+ soc_create_ioat_domains(dev->bus, ri);
}
}
}
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 39a7eba..e602ad7 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -61,7 +61,7 @@
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
- attach_iio_stacks(dev);
+ attach_stacks(dev);
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
} else if (dev->path.type == DEVICE_PATH_GPIO) {
diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h
index ac8ba9e..dcfb0a0 100644
--- a/src/soc/intel/xeon_sp/include/soc/chip_common.h
+++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h
@@ -7,7 +7,7 @@
void iio_pci_domain_read_resources(struct device *dev);
void iio_pci_domain_scan_bus(struct device *dev);
-void attach_iio_stacks(struct device *dev);
+void attach_stacks(struct device *dev);
void soc_create_ioat_domains(struct bus *bus, const STACK_RES *sr);
diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
index b468842..0b0f365 100644
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ b/src/soc/intel/xeon_sp/skx/chip.c
@@ -47,7 +47,7 @@
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
- attach_iio_stacks(dev);
+ attach_stacks(dev);
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
} else if (dev->path.type == DEVICE_PATH_GPIO) {
diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c
index 3b3c65e..3c3417e 100644
--- a/src/soc/intel/xeon_sp/spr/chip.c
+++ b/src/soc/intel/xeon_sp/spr/chip.c
@@ -72,7 +72,7 @@
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
- attach_iio_stacks(dev);
+ attach_stacks(dev);
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
} else if (dev->path.type == DEVICE_PATH_GPIO) {
--
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Change subject: device/device_util: Add method to retrieve the domain
......................................................................
device/device_util: Add method to retrieve the domain
Add a function to return the PCI domain device for the specified
device. On multi PCI domain platforms this function allows to
determine which domain and thus which socket the PCI device
belongs to.
Change-Id: I0068b82e139fe7a35e6b1b91b7d386b750c80748
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/device/device_util.c
M src/include/device/device.h
2 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/80090/1
diff --git a/src/device/device_util.c b/src/device/device_util.c
index ac2d33c..c17b4c5 100644
--- a/src/device/device_util.c
+++ b/src/device/device_util.c
@@ -257,6 +257,24 @@
return buffer;
}
+/* Returns the PCI domain for the given PCI device */
+struct device *dev_get_pci_domain(struct device *dev)
+{
+ if (!dev)
+ return NULL;
+
+ /* Walk up the tree up to the PCI domain */
+ while (dev->bus) {
+ dev = dev->bus->dev;
+ if (!dev)
+ break;
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ return dev;
+ }
+
+ return NULL;
+}
+
/**
* Allocate 64 more resources to the free list.
*
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 50307e6..860d110 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -190,6 +190,7 @@
const char *dev_path(const struct device *dev);
u32 dev_path_encode(const struct device *dev);
const char *bus_path(struct bus *bus);
+struct device *dev_get_pci_domain(struct device *dev);
void dev_set_enabled(struct device *dev, int enable);
void disable_children(struct bus *bus);
bool dev_is_active_bridge(struct device *dev);
--
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Change subject: soc/intel/xeon_sp: Fix devicetree walking up
......................................................................
soc/intel/xeon_sp: Fix devicetree walking up
Connect the PCI domain to the bus to allow walking the devicetree
up. This is required to figure out which PCI domain a device
belongs to.
Change-Id: I8cc50cabf7ad540c52498e1ffe7f9246550ed87b
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/spr/ioat.c
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/80089/1
diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c
index c1b331b..0411a03 100644
--- a/src/soc/intel/xeon_sp/chip_common.c
+++ b/src/soc/intel/xeon_sp/chip_common.c
@@ -77,6 +77,7 @@
}
struct bus *bus = dev->link_list;
+ bus->dev = dev;
bus->secondary = sr->BusBase;
bus->subordinate = sr->BusBase;
bus->max_subordinate = sr->BusLimit;
diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c
index f10863a..38bbd93 100644
--- a/src/soc/intel/xeon_sp/spr/ioat.c
+++ b/src/soc/intel/xeon_sp/spr/ioat.c
@@ -45,6 +45,7 @@
die("%s: out of memory.\n", __func__);
struct bus *const bus = domain->link_list;
+ bus->dev = domain;
bus->secondary = bus_base;
bus->subordinate = bus->secondary;
bus->max_subordinate = bus_limit;
--
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Change subject: soc/intel/xeon_sp: Scan and allocate resources on all stacks
......................................................................
Patch Set 14:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78332/comment/7e8861da_9649de61 :
PS14, Line 12: TEST=intel/archercity CRB
> Are there user visible (logs?) changes?
Hi Paul, as a refactor patch, no significant changes.
--
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Change subject: soc/intel/xeon_sp: Support multiple PCI segment groups
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Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/spr/soc_acpi.c:
https://review.coreboot.org/c/coreboot/+/79878/comment/bed6740d_d589b4e7 :
PS2, Line 256: stack_enabled = false;
> Hi Rudolph, […]
Adding a bit more background.
Here we will have https://review.coreboot.org/c/coreboot/+/78333, it will move the whole _CRS creation from ASL template to C codes. Hence for dynamically skipped stacks, it will have the whole _CRS not implemented, which is similar to with a _CRS but with null resources. Both should be okay from Linux point of view.
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Change subject: drivers/uart/sifive.c: Fix divisor calculation
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Patch Set 3: Code-Review+1
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