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Hello Chen, Gang C, Cliff Huang, Felix Held, Jincheng Li, Lance Zhao, Lean Sheng Tan, Nico Huber, Paul Menzel, Shuo Liu, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified-1 by build bot (Jenkins)
Change subject: device/device.h: Drop acpi_inject_dsdt
......................................................................
device/device.h: Drop acpi_inject_dsdt
This is now unused in the tree and filling SSDT should always be used.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Iffefc865901b15fa299931b6ed4c27a9e3a1c330
---
M src/acpi/acpi.c
M src/include/device/device.h
2 files changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/78334/19
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: Add IIO resources via SSDT
......................................................................
soc/intel/xeon_sp: Add IIO resources via SSDT
There is no need to inject this code in DSDT. Just generating a _CRS
Name in SSDT containing a resource template works well and reduces the
need to sync up on names being used to return _CRS names in DSDT.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I691d7497dceb89619652e5523a29ea30a7b0fab8
---
M src/soc/intel/xeon_sp/acpi/iiostack.asl
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/soc/intel/xeon_sp/skx/soc_acpi.c
M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/iiostack.asl
M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/uncore.c
11 files changed, 44 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/78333/20
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Hello Angel Pons, Caveh Jalali, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Felix Held, Forest Mittelberg, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Jason Nien, Jeff Daly, Jincheng Li, Johnny Lin, Jérémy Compostella, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Varshit Pandya, Werner Zeh, build bot (Jenkins),
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Change subject: device/device.h: Rename busses for clarity
......................................................................
device/device.h: Rename busses for clarity
This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
---
M src/acpi/acpi.c
M src/acpi/device.c
M src/arch/x86/mpspec.c
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/device/cardbus_device.c
M src/device/device.c
M src/device/device_const.c
M src/device/device_util.c
M src/device/i2c_bus.c
M src/device/mdio.c
M src/device/oprom/realmode/x86.c
M src/device/oprom/realmode/x86_interrupts.c
M src/device/oprom/yabel/device.c
M src/device/oprom/yabel/interrupt.c
M src/device/pci_device.c
M src/device/pci_rom.c
M src/device/pciexp_device.c
M src/device/pcix_device.c
M src/device/pnp_device.c
M src/device/resource_allocator_v4.c
M src/device/root_device.c
M src/drivers/i2c/ptn3460/ptn3460.c
M src/drivers/intel/dptf/dptf.c
M src/drivers/intel/ish/ish.c
M src/drivers/intel/mipi_camera/camera.c
M src/drivers/intel/soundwire/soundwire.c
M src/drivers/net/phy/m88e1512/m88e1512.c
M src/drivers/net/r8168.c
M src/drivers/nxp/uwb/uwb.c
M src/drivers/pcie/generic/generic.c
M src/drivers/spi/acpi/acpi.c
M src/drivers/usb/hub/acpi.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/smbios.c
M src/drivers/wwan/fm/acpi_fm350gl.c
M src/ec/google/chromeec/ec_acpi.c
M src/include/device/device.h
M src/include/device/pci_ops.h
M src/lib/smbios.c
M src/mainboard/aopen/dxplplusu/acpi_tables.c
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/google/brox/mainboard.c
M src/mainboard/google/brya/mainboard.c
M src/mainboard/google/kahlee/variants/careena/mainboard.c
M src/mainboard/google/kahlee/variants/treeya/audio.c
M src/mainboard/google/octopus/mainboard.c
M src/mainboard/google/rex/mainboard.c
M src/mainboard/google/zork/variants/baseboard/ramstage_common.c
M src/mainboard/ibase/mb899/mptable.c
M src/mainboard/kontron/986lcd-m/mptable.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/mainboard/roda/rk9/ti_pci7xx1.c
M src/mainboard/siemens/fa_ehl/mainboard.c
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/e7505/northbridge.c
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/pineview/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/northbridge.c
M src/soc/amd/cezanne/xhci.c
M src/soc/amd/common/block/acpi/ivrs.c
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/glinda/xhci.c
M src/soc/amd/mendocino/xhci.c
M src/soc/amd/phoenix/xhci.c
M src/soc/amd/picasso/xhci.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/cavium/cn81xx/ecam0.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/common/block/acpi/pep.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
M src/soc/intel/common/block/usb4/pcie.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/meteorlake/fsp_params.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/skx/soc_acpi.c
M src/soc/intel/xeon_sp/spr/ioat.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/uncore.c
M src/soc/intel/xeon_sp/uncore_acpi.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/superio/common/generic.c
M src/superio/common/ssdt.c
M util/sconfig/main.c
102 files changed, 336 insertions(+), 341 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/78330/15
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80092?usp=email )
Change subject: soc/intel/xeon_sp: Find VTD devices by PCI DEV ID
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/xeon_sp/memmap.c:
https://review.coreboot.org/c/coreboot/+/80092/comment/43113f5a_0f7bc3dd :
PS1, Line 71: PCI_VID_INTEL, MMAP_VTD_STACK_CFG_REG_DEVID
> I vaguely remember that they don't all have the same DEVID, but I'm not sure.
The code pulls in the soc specific headers and those might have a different PCI IDs. For some devices, like VTD or SAD, it seems to be the same ID accross multiple generations.
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Change subject: soc/intel/xeon_sp: Attach more stacks
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/xeon_sp/chip_common.c:
https://review.coreboot.org/c/coreboot/+/80091/comment/eb284bfb_8f06976e :
PS1, Line 147: add_more_links(iio_domain, ri->BusLimit - ri->BusBase + 1);
> There are no resources. […]
Can we have two domain devices with the same ID for the same stack?
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Hello Chen, Gang C, Cliff Huang, Felix Held, Jincheng Li, Lance Zhao, Lean Sheng Tan, Nico Huber, Paul Menzel, Shuo Liu, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78334?usp=email
to look at the new patch set (#18).
The following approvals got outdated and were removed:
Code-Review+1 by Nico Huber, Code-Review+1 by Shuo Liu, Code-Review+2 by Felix Held, Code-Review+2 by Lean Sheng Tan, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: device/device.h: Drop acpi_inject_dsdt
......................................................................
device/device.h: Drop acpi_inject_dsdt
This is now unused in the tree and filling SSDT should always be used.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Iffefc865901b15fa299931b6ed4c27a9e3a1c330
---
M src/acpi/acpi.c
M src/include/device/device.h
2 files changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/78334/18
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Iffefc865901b15fa299931b6ed4c27a9e3a1c330
Gerrit-Change-Number: 78334
Gerrit-PatchSet: 18
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
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Gerrit-MessageType: newpatchset
Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu.
Hello Christian Walter, Felix Held, Johnny Lin, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78333?usp=email
to look at the new patch set (#19).
The following approvals got outdated and were removed:
Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Add IIO resources via SSDT
......................................................................
soc/intel/xeon_sp: Add IIO resources via SSDT
There is no need to inject this code in DSDT. Just generating a _CRS
Name in SSDT containing a resource template works well and reduces the
need to sync up on names being used to return _CRS names in DSDT.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I691d7497dceb89619652e5523a29ea30a7b0fab8
---
M src/soc/intel/xeon_sp/acpi/iiostack.asl
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/soc/intel/xeon_sp/skx/soc_acpi.c
M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/iiostack.asl
M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/uncore.c
11 files changed, 44 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/78333/19
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Gerrit-MessageType: newpatchset
Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Nico Huber, Paul Menzel, Shuo Liu, Tim Chu.
Hello Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78332?usp=email
to look at the new patch set (#15).
The following approvals got outdated and were removed:
Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Scan and allocate resources on all stacks
......................................................................
soc/intel/xeon_sp: Scan and allocate resources on all stacks
The code can now deal with stacks that have no resources so just hook
them all up.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Id72c6e4499e99df3b7ca821ab2893cbcc869dbcd
---
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/util.c
8 files changed, 8 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/78332/15
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Attention is currently required from: Angel Pons, Arthur Heymans, Caveh Jalali, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Felix Held, Forest Mittelberg, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Jason Nien, Jeff Daly, Jincheng Li, Johnny Lin, Jérémy Compostella, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Varshit Pandya, Werner Zeh.
Hello Angel Pons, Caveh Jalali, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Felix Held, Forest Mittelberg, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Jason Nien, Jeff Daly, Jincheng Li, Johnny Lin, Jérémy Compostella, Kapil Porwal, Lance Zhao, Martin L Roth, Martin Roth, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Varshit Pandya, Werner Zeh, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78330?usp=email
to look at the new patch set (#14).
The following approvals got outdated and were removed:
Code-Review+1 by Felix Held
Change subject: device/device.h: Rename busses for clarity
......................................................................
device/device.h: Rename busses for clarity
This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
---
M src/acpi/acpi.c
M src/acpi/device.c
M src/arch/x86/mpspec.c
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_2065x/model_2065x_init.c
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/device/cardbus_device.c
M src/device/device.c
M src/device/device_const.c
M src/device/device_util.c
M src/device/i2c_bus.c
M src/device/mdio.c
M src/device/oprom/realmode/x86.c
M src/device/oprom/realmode/x86_interrupts.c
M src/device/oprom/yabel/device.c
M src/device/oprom/yabel/interrupt.c
M src/device/pci_device.c
M src/device/pci_rom.c
M src/device/pciexp_device.c
M src/device/pcix_device.c
M src/device/pnp_device.c
M src/device/resource_allocator_v4.c
M src/device/root_device.c
M src/drivers/i2c/ptn3460/ptn3460.c
M src/drivers/intel/dptf/dptf.c
M src/drivers/intel/ish/ish.c
M src/drivers/intel/mipi_camera/camera.c
M src/drivers/intel/soundwire/soundwire.c
M src/drivers/net/phy/m88e1512/m88e1512.c
M src/drivers/net/r8168.c
M src/drivers/nxp/uwb/uwb.c
M src/drivers/pcie/generic/generic.c
M src/drivers/spi/acpi/acpi.c
M src/drivers/usb/hub/acpi.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/smbios.c
M src/drivers/wwan/fm/acpi_fm350gl.c
M src/ec/google/chromeec/ec_acpi.c
M src/include/device/device.h
M src/include/device/pci_ops.h
M src/lib/smbios.c
M src/mainboard/aopen/dxplplusu/acpi_tables.c
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/google/brox/mainboard.c
M src/mainboard/google/brya/mainboard.c
M src/mainboard/google/kahlee/variants/careena/mainboard.c
M src/mainboard/google/kahlee/variants/treeya/audio.c
M src/mainboard/google/octopus/mainboard.c
M src/mainboard/google/rex/mainboard.c
M src/mainboard/google/zork/variants/baseboard/ramstage_common.c
M src/mainboard/ibase/mb899/mptable.c
M src/mainboard/kontron/986lcd-m/mptable.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/mainboard/roda/rk9/ti_pci7xx1.c
M src/mainboard/siemens/fa_ehl/mainboard.c
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/e7505/northbridge.c
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/pineview/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/northbridge.c
M src/soc/amd/cezanne/xhci.c
M src/soc/amd/common/block/acpi/ivrs.c
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/glinda/xhci.c
M src/soc/amd/mendocino/xhci.c
M src/soc/amd/phoenix/xhci.c
M src/soc/amd/picasso/xhci.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/cavium/cn81xx/ecam0.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/common/block/acpi/pep.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
M src/soc/intel/common/block/usb4/pcie.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/meteorlake/fsp_params.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/skx/soc_acpi.c
M src/soc/intel/xeon_sp/spr/ioat.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/uncore.c
M src/soc/intel/xeon_sp/uncore_acpi.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/superio/common/generic.c
M src/superio/common/ssdt.c
M util/sconfig/main.c
102 files changed, 331 insertions(+), 336 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/78330/14
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Attention is currently required from: Arthur Heymans, Chen, Gang C, Felix Held, Fred Reitberger, Jason Glenesk, Jincheng Li, Jérémy Compostella, Martin L Roth, Matt DeVillier.
Hello Chen, Gang C, Felix Held, Fred Reitberger, Jason Glenesk, Jincheng Li, Jérémy Compostella, Martin L Roth, Matt DeVillier, Shuo Liu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#9).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: device/device.h: Drop multiple links
......................................................................
device/device.h: Drop multiple links
Multiple links are unused throughout the tree and make the code more
confusing as an iteration over all busses is needed to get downstream
devices. This also not done consistently e.g. the allocator does not
care about multiple links on busses. A better way of dealing multiple
links below a device is to feature dummy devices with each their
respective bus.
This drops the sconfig capability to declare the same device multiple
times which was previously used to declare multiple links.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b
---
M src/arch/x86/mpspec.c
M src/device/device.c
M src/device/device_util.c
M src/device/pci_device.c
M src/device/root_device.c
M src/include/device/device.h
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/soc/amd/common/block/acpi/ivrs.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/intel/common/block/lpc/lpc.c
M src/southbridge/amd/pi/hudson/lpc.c
M util/sconfig/main.c
M util/sconfig/sconfig.h
M util/sconfig/sconfig.tab.c_shipped
M util/sconfig/sconfig.y
16 files changed, 188 insertions(+), 373 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/78328/9
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Gerrit-Change-Number: 78328
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