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Change subject: device_util: Drop unused function bus_path
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Patch Set 1: Code-Review+2
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Change subject: arch/riscv: Add OPENSBI_FW_DYNAMIC_BOOT_HART option
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Patch Set 2: Code-Review+1
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Change subject: Makefile: Finish switch to Makefile.mak from .inc
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
We're including 3rdparty submodules directly, so that needs to be addressed before we can merge this.
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Change subject: lib/lzmadecode: Allow for 8 byte reads on 64bit
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/70175/comment/ecf0228c_a894d6f4 :
PS2, Line 16: - google/vilboz: cached boot medium
> Please add a summary of the data, for example: 2 ms difference
This really depends on the data and the hardware used and even caching setup. I don't think a summary is possible.
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Hello Chen, Gang C, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78332?usp=email
to look at the new patch set (#18).
Change subject: soc/intel/xeon_sp: Scan and allocate resources on all stacks
......................................................................
soc/intel/xeon_sp: Scan and allocate resources on all stacks
The code can now deal with stacks that have no resources so just hook
them all up.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Change-Id: Id72c6e4499e99df3b7ca821ab2893cbcc869dbcd
---
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/util.c
8 files changed, 27 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/78332/18
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Change subject: soc/intel/xeon_sp: Attach more stacks
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/xeon_sp/chip_common.c:
https://review.coreboot.org/c/coreboot/+/80091/comment/9ec3ef9e_ac26387b :
PS1, Line 147: add_more_links(iio_domain, ri->BusLimit - ri->BusBase + 1);
> Can we have two domain devices with the same ID for the same stack?
Maybe it sometimes works, but I thinks it's best to use unique ID. It's a 32bit number so you can use a few bits to encode which stack is used for instance, iaot.c does something like that. As a sidenote that code also needs to be updated to be segment aware to avoid overlaps on the domain id.
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Change subject: soc/intel/xeon_sp: Find VTD devices by PCI DEV ID
......................................................................
Patch Set 1: -Code-Review
(1 comment)
File src/soc/intel/xeon_sp/memmap.c:
https://review.coreboot.org/c/coreboot/+/80092/comment/33804b7b_7f10ae20 :
PS1, Line 71: PCI_VID_INTEL, MMAP_VTD_STACK_CFG_REG_DEVID
> The code pulls in the soc specific headers and those might have a different PCI IDs. For some devices, like VTD or SAD, it seems to be the same ID accross multiple generations.
I mean on the same soc, e.g. cpx:
#define MMAP_VTD_CFG_REG_DEVID 0x2024
#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034
but both need to be set.
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I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
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Change subject: soc/intel/xeon_sp: Scan and allocate resources on all stacks
......................................................................
soc/intel/xeon_sp: Scan and allocate resources on all stacks
The code can now deal with stacks that have no resources so just hook
them all up.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Change-Id: Id72c6e4499e99df3b7ca821ab2893cbcc869dbcd
---
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/util.c
8 files changed, 28 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/78332/17
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