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Change subject: device/device.h: Drop multiple links
......................................................................
Patch Set 10:
(12 comments)
File src/device/device.c:
https://review.coreboot.org/c/coreboot/+/78328/comment/83eab2b7_0c0ecf60 :
PS10, Line 362: if (link && link->reset_needed) {
Or `continue;` if not.
https://review.coreboot.org/c/coreboot/+/78328/comment/233c4af7_ac24d9a6 :
PS10, Line 489: if (dev_root.link_list)
Other functions seem to imply this.
https://review.coreboot.org/c/coreboot/+/78328/comment/1ecb7a8b_23243d0e :
PS10, Line 558: if (dev_root.link_list)
Other functions seem to imply this.
File src/device/device_util.c:
https://review.coreboot.org/c/coreboot/+/78328/comment/9e6efb87_066154ea :
PS10, Line 550: search_bus_resources(curdev->link_list, type_mask, type,
Missing NULL-check.
File src/device/root_device.c:
https://review.coreboot.org/c/coreboot/+/78328/comment/2848c726_a5bc9011 :
PS10, Line 41:
Missing NULL-check.
https://review.coreboot.org/c/coreboot/+/78328/comment/154450d7_e0cb27e2 :
PS10, Line 78: Then, link_list buses
Was this on purpose? Looks a bit like something went wrong undoing the renaming?
File src/include/device/device.h:
https://review.coreboot.org/c/coreboot/+/78328/comment/7162398c_1e0a1e53 :
PS10, Line 239: }
Probably shouldn't be inline anymore.
File util/sconfig/main.c:
https://review.coreboot.org/c/coreboot/+/78328/comment/ac2dd216_cbc258c2 :
PS10, Line 797: const struct bus *bus = parent->bus;
NULL check?
https://review.coreboot.org/c/coreboot/+/78328/comment/3b90a65b_6b789616 :
PS10, Line 1178: if (bus->children)
Or `assert(ptr->bus && ptr->bus->children);`. It seems to be checked before
the call.
https://review.coreboot.org/c/coreboot/+/78328/comment/0b072d27_f053a36d :
PS10, Line 1330: bus && bus->children
Or dev_has_children(). We should either use it everywhere or could also drop it.
https://review.coreboot.org/c/coreboot/+/78328/comment/574353ed_56b3cce1 :
PS10, Line 1789: buses
*bus
File util/sconfig/sconfig.h:
https://review.coreboot.org/c/coreboot/+/78328/comment/b6cb876f_bd6ea45c :
PS10, Line 157: struct bus *last_bus;
Drop
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Change subject: ec: Rename Makefiles from .inc to .mak
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Patch Set 2: Code-Review+1
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Change subject: device/device.h: Drop multiple links
......................................................................
Patch Set 10: Code-Review-2
(1 comment)
Patchset:
PS10:
Something is broken during scanning but IDK what. Debugging
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Change subject: mb/google/brox: enable WIFI_SAR
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/brox: enable WIFI_SAR
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brox/variants/brox/variant.c:
https://review.coreboot.org/c/coreboot/+/80085/comment/43428b9a_b7d0e351 :
PS2, Line 5: #include <baseboard/variants.h>
> While you're here, could you alphabetize <baseboard/variants.h> and put it above <chip. […]
Done.
The sad thing is that I meant to/tried to do it but obviously did a poor job. :P
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Change subject: mb/google/brox: enable WIFI_SAR
......................................................................
mb/google/brox: enable WIFI_SAR
Add get_wifi_sar_cbfs_filename(). This function uses the FW_CONFIG
for WIFI to choose the right wifi_sar hex file. Below is the file
mapping:
wifi_sar_0.hex = wifi6
wifi_sar_1.hex = wifi7
BUG=b:319302319
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
Change-Id: I212c80412141e7770a512bd8ccf4111963bab395
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/Kconfig
M src/mainboard/google/brox/variants/brox/variant.c
2 files changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/80085/3
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Change subject: Makefile.inc: Compress DSDT file
......................................................................
Makefile.inc: Compress DSDT file
Now that x86 has a CBFS cache we can use that cache as a dsdt
decompression location. To be on the safe side, increase the cache size
to 128K which would largely fit all dsdt in coreboot.
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M Makefile.inc
M src/arch/x86/Kconfig
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Change subject: acpi: Load DSDT directly into target location
......................................................................
Abandoned
now x86 has scratchpad
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Change subject: soc/intel/xeon_sp/skx/soc_util: Find devices by PCI ID
......................................................................
soc/intel/xeon_sp/skx/soc_util: Find devices by PCI ID
Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code
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Change-Id: Ie5ef78523c740f23807b3acf232f1c0e29feb4c6
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---
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/soc_util.c
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/80100/2
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Change subject: soc/intel/xeon_sp/spr: Locate PCU by PCI device ID
......................................................................
soc/intel/xeon_sp/spr: Locate PCU by PCI device ID
Instead of manually crafting S:B:D:F numbers for each PCI device
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This adds PCI multi-segment support without any further code
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Intel Document-ID: 735086
Intel Document-ID: 612246
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---
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/spr/chip.c
M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
4 files changed, 60 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/80093/3
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