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Change subject: soc/intel/meteorlake: Fix system hang by enabling SMI handling
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Change subject: soc/intel/cmn/block/pmc: Fix prev_sleep_state string name mapping
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Change subject: libpayload/arch/arm64/mmu: Specify ttb_buffer section name explicitly
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Change subject: commonlib/bsd/compiler.h: Define __section(section) macro
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Change subject: 3rdparty/arm-trusted-firmware: Update submodule to upstream master
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Change subject: mb/purism/librem_skl: Fix pcie_rp5 in device tree (WLAN)
......................................................................
mb/purism/librem_skl: Fix pcie_rp5 in device tree (WLAN)
WLAN has always been pcie_rp5, there is nothing on pcie_rp1. RP5 gets
promoted to function 0 (RP1's function) since no earlier functions are
enabled.
This simplifies later refactoring that will handle the FSP root port
enable flags (which were correctly set already) using the device tree
enables.
Test: Boot librem_13v2 and verify WLAN is enabled.
Change-Id: I7a724a01b5f171a16de83ff6122630e2d66557c1
Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80065
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
---
M src/mainboard/purism/librem_skl/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Felix Singer: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 1928d15..08a88d6 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -157,7 +157,7 @@
device ref south_xdci on end
device ref thermal on end
device ref sata on end
- device ref pcie_rp1 on end
+ device ref pcie_rp5 on end
device ref pcie_rp9 on end
device ref lpc_espi on
chip drivers/pc80/tpm
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79984?usp=email )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/amd/phoenix/Makefile: conditionally add fsp_[m,s]_params.c
......................................................................
soc/amd/phoenix/Makefile: conditionally add fsp_[m,s]_params.c
fsp_m_params.c and fsp_s_params.c only contain FSP-specific code, so
only add those to the build if the SOC_AMD_PHOENIX_FSP Kconfig option is
selected. Other files have FSP-specific parts too, but those will be
reworked in future patches.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ife38ca6a548d7c3c2e765d9c9f30e0a4057bb373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79984
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/phoenix/Makefile.inc
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Martin Roth: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc
index 03a38ad..0301cdc 100644
--- a/src/soc/amd/phoenix/Makefile.inc
+++ b/src/soc/amd/phoenix/Makefile.inc
@@ -21,7 +21,7 @@
verstage-y += espi_util.c
-romstage-y += fsp_m_params.c
+romstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_m_params.c
romstage-y += romstage.c
romstage-y += soc_util.c
@@ -30,7 +30,7 @@
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += fch.c
-ramstage-y += fsp_s_params.c
+ramstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_s_params.c
ramstage-y += graphics.c
ramstage-y += mca.c
ramstage-y += root_complex.c
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