Attention is currently required from: Nico Huber.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80022?usp=email )
Change subject: mb/siemens/chili: Use chipset dt reference names
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/siemens/chili/variants/base/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80022/comment/aafe5ba2_8dbd1de4 :
PS2, Line 13:
> Nit, it looks like the second tab isn't needed in any line.
Will shrink that down with CB:80043.
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ic3a4c85ec6bfdc858f9b6f79b114cf612ad3a153
Gerrit-Change-Number: 80022
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-Comment-Date: Fri, 19 Jan 2024 08:02:18 +0000
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Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: comment
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80056?usp=email )
Change subject: mb/purism/librem_cnl: Use chipset dt reference names
......................................................................
mb/purism/librem_cnl: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: I87cec9026bcb621ceb7eae51f65ae35bc31d584a
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80056
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm>
---
M src/mainboard/purism/librem_cnl/devicetree.cb
M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
M src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
3 files changed, 65 insertions(+), 65 deletions(-)
Approvals:
Jonathon Hall: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb
index ff21977..3d26b09 100644
--- a/src/mainboard/purism/librem_cnl/devicetree.cb
+++ b/src/mainboard/purism/librem_cnl/devicetree.cb
@@ -44,58 +44,58 @@
device cpu_cluster 0 on end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 on # SA Thermal device
+ device ref system_agent on end
+ device ref igpu on end
+ device ref dptf on
register "Device4Enable" = "1"
end
- device pci 12.0 on end # Thermal Subsystem
- device pci 13.0 off end # Integrated Sensor Hub
- device pci 14.0 on end # USB xHC
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 15.0 off end # I2C #0
- device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 16.5 off end # Management Engine Interface 4
- device pci 17.0 on end # SATA
- device pci 19.0 off end # I2C #4
- device pci 19.1 off end # I2C #5
- device pci 19.2 off end # UART #2
- device pci 1a.0 off end # eMMC
- device pci 1c.0 off end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 off end # PCI Express Port 5
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 off end # PCI Express Port 9
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 off end # PCI Express Port 13
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1e.0 off end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on end # LPC Bridge
- device pci 1f.1 off end # P2SB
- device pci 1f.2 hidden end # Power Management Controller
- device pci 1f.3 on # Intel HDA
+ device ref thermal on end
+ device ref ish off end
+ device ref xhci on end
+ device ref xdci off end
+ device ref i2c0 off end
+ device ref i2c1 off end
+ device ref i2c2 off end
+ device ref i2c3 off end
+ device ref heci1 off end
+ device ref heci2 off end
+ device ref csme_ider off end
+ device ref csme_ktr off end
+ device ref heci3 off end
+ device ref heci4 off end
+ device ref sata on end
+ device ref i2c4 off end
+ device ref i2c5 off end
+ device ref uart2 off end
+ device ref emmc off end
+ device ref pcie_rp1 off end
+ device ref pcie_rp2 off end
+ device ref pcie_rp3 off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 off end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref pcie_rp9 off end
+ device ref pcie_rp10 off end
+ device ref pcie_rp11 off end
+ device ref pcie_rp12 off end
+ device ref pcie_rp13 off end
+ device ref pcie_rp14 off end
+ device ref pcie_rp15 off end
+ device ref pcie_rp16 off end
+ device ref uart0 off end
+ device ref uart1 off end
+ device ref gspi0 off end
+ device ref gspi1 off end
+ device ref lpc_espi on end
+ device ref p2sb off end
+ device ref pmc hidden end
+ device ref hda on
register "PchHdaAudioLinkHda" = "1"
end
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
+ device ref smbus on end
+ device ref fast_spi on end
+ device ref gbe off end
end
end
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
index ef35ac0..b3fd862 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
@@ -24,7 +24,7 @@
# Actual device tree
device domain 0 on
- device pci 02.0 on # Integrated Graphics Device
+ device ref igpu on
register "gfx" = "GMA_DEFAULT_PANEL(0)"
register "panel_cfg" = "{
.up_delay_ms = 200,
@@ -35,7 +35,7 @@
.backlight_off_delay_ms = 1,
}"
end
- device pci 14.0 on # USB xHCI
+ device ref xhci on
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
@@ -131,8 +131,8 @@
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-C left
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader
end
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 15.0 on # I2C #0
+ device ref xdci off end
+ device ref i2c0 on
chip drivers/i2c/hid
register "generic.hid" = ""HTIX5288""
register "generic.name" = ""TPD0""
@@ -142,7 +142,7 @@
device i2c 2c on end
end
end
- device pci 17.0 on # SATA
+ device ref sata on
register "satapwroptimize" = "1"
register "SataSalpSupport" = "1"
# Port 2 (M.2 / inner)
@@ -152,7 +152,7 @@
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1"
end
- device pci 1c.6 on # PCI Express Port 7 -- x1 M.2/E 2230 (WLAN)
+ device ref pcie_rp7 on # x1 M.2/E 2230 (WLAN)
register "PcieRpEnable[6]" = "1"
register "PcieRpSlotImplemented[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
@@ -161,13 +161,13 @@
register "PcieClkSrcClkReq[2]" = "2"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end
- device pci 1c.7 on # PCI Express Port 8
+ device ref pcie_rp8 on
device pci 00.0 on end # x1 (LAN)
register "PcieRpEnable[7]" = "1"
register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3"
end
- device pci 1d.0 on # PCI Express Port 9 -- x4 M.2/M 2280 (NVMe)
+ device ref pcie_rp9 on # x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[8]" = "1"
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
@@ -175,7 +175,7 @@
register "PcieClkSrcClkReq[0]" = "0"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe)
+ device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
@@ -183,7 +183,7 @@
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device pci 1f.0 on # LPC Bridge
+ device ref lpc_espi on
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x88: Decode 0x68 - 0x6F (EC PM channel)
register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
index cab254a..f9baef2 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
@@ -20,7 +20,7 @@
# Actual device tree
device domain 0 on
- device pci 14.0 on # USB xHCI
+ device ref xhci on
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
@@ -123,12 +123,12 @@
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
end
- device pci 17.0 on # SATA
+ device ref sata on
register "SataPortsEnable[0]" = "1" # 2.5"
register "SataPortsEnable[2]" = "1" # m.2
register "satapwroptimize" = "1"
end
- device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN)
+ device ref pcie_rp8 on # x1 M.2/E 2230 (WLAN)
register "PcieRpSlotImplemented[7]" = "1"
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
@@ -136,13 +136,13 @@
register "PcieClkSrcUsage[2]" = "0x80"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end
- device pci 1d.1 on # PCI Express Port 10
+ device ref pcie_rp10 on
device pci 00.0 on end # x1 (LAN)
register "PcieRpEnable[9]" = "1"
register "PcieClkSrcUsage[3]" = "9"
register "PcieClkSrcClkReq[3]" = "3"
end
- device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe)
+ device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
@@ -150,7 +150,7 @@
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device pci 1f.0 on # LPC Bridge
+ device ref lpc_espi on
chip superio/ite/it8528e
device pnp 2e.1 on # UART1
io 0x60 = 0x3F8
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I87cec9026bcb621ceb7eae51f65ae35bc31d584a
Gerrit-Change-Number: 80056
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80055?usp=email )
Change subject: mb/purism/librem_l1um_v2: Use chipset dt reference names
......................................................................
mb/purism/librem_l1um_v2: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: Id592241a1dc33559115800da10a57a5fc10867f9
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80055
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm>
---
M src/mainboard/purism/librem_l1um_v2/devicetree.cb
1 file changed, 38 insertions(+), 38 deletions(-)
Approvals:
build bot (Jenkins): Verified
Jonathon Hall: Looks good to me, approved
diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb
index 0144f22..e86b7a0 100644
--- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb
+++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb
@@ -40,20 +40,20 @@
device cpu_cluster 0 on end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 01.0 on # PCIE6 - x16 or x8
+ device ref system_agent on end
+ device ref peg0 on # x16 or x8
register "PcieClkSrcUsage[3]" = "0x40"
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "PCIE6" "SlotDataBusWidth16X"
end
- device pci 01.1 on # PCIE4 - x8
+ device ref peg1 on # x8
register "PcieClkSrcUsage[4]" = "0x41"
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthOther" "PCIE4" "SlotDataBusWidth8X"
end
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 off end # SA Thermal Device
- device pci 08.0 on end # Gaussian Mixture
- device pci 12.0 on end # Thermal Subsystem
- device pci 14.0 on # USB xHCI
+ device ref igpu on end
+ device ref dptf off end
+ device ref gna on end
+ device ref thermal on end
+ device ref xhci on
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 front left
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 front right
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB_1_2 header port A
@@ -176,20 +176,20 @@
end
end
end
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.2 on end # RAM controller
- device pci 14.3 off end
- device pci 14.5 off end # SDCard
- device pci 15.0 off end # I2C #0
- device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE Redirection
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 17.0 on
+ device ref xdci off end
+ device ref shared_sram on end
+ device ref cnvi_wifi off end
+ device ref sdxc off end
+ device ref i2c0 off end
+ device ref i2c1 off end
+ device ref i2c2 off end
+ device ref i2c3 off end
+ device ref heci1 off end
+ device ref heci2 off end
+ device ref csme_ider off end
+ device ref csme_ktr off end
+ device ref heci3 off end
+ device ref sata on
register "satapwroptimize" = "1"
register "SataPortsEnable[0]" = "1"
@@ -209,22 +209,22 @@
register "SataPortsHotPlug[5]" = "1"
register "SataPortsHotPlug[6]" = "1"
register "SataPortsHotPlug[7]" = "1"
- end # SATA
- device pci 1b.4 on # PCI Express Port 21 - PCIE5
+ end
+ device ref pcie_rp21 on
register "PcieRpSlotImplemented[20]" = "1"
register "PcieRpEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[10]" = "20"
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X"
end
- device pci 1c.0 on # PCI Express Port 1 - M2_1
+ device ref pcie_rp1 on
register "PcieRpSlotImplemented[0]" = "1"
register "PcieRpEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieClkSrcUsage[1]" = "0x80"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X"
end
- device pci 1d.0 on # PCI Express Port 9 - GbE #1
+ device ref pcie_rp9 on # GbE #1
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[14]" = "8"
@@ -237,12 +237,12 @@
smbios_dev_info 1
end
end
- device pci 1d.1 on # PCI Express Port 10 - BMC video
+ device ref pcie_rp10 on # BMC video
register "PcieRpEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "1"
register "PcieClkSrcUsage[8]" = "9"
end
- device pci 1d.2 on # PCI Express Port 11 - GbE #2
+ device ref pcie_rp11 on # GbE #2
register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
register "PcieClkSrcUsage[11]" = "10"
@@ -250,11 +250,11 @@
smbios_dev_info 2
end
end
- device pci 1e.0 off end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on # LPC Interface
+ device ref uart0 off end
+ device ref uart1 off end
+ device ref gspi0 off end
+ device ref gspi1 off end
+ device ref lpc_espi on
# This board has a lot of SuperIO LDNs with I/O BARs, the LPC generic
# I/O ranges must be configured manually.
register "gen1_dec" = "0x000c0ca1" # IPMI: ca0-caf
@@ -385,10 +385,10 @@
device pnp 0c31.0 on end
end
end
- device pci 1f.1 off end # P2SB
- device pci 1f.2 hidden end # PMC
- device pci 1f.3 off end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # SPI
+ device ref p2sb off end
+ device ref pmc hidden end
+ device ref hda off end
+ device ref smbus on end
+ device ref fast_spi on end
end
end
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Id592241a1dc33559115800da10a57a5fc10867f9
Gerrit-Change-Number: 80055
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80054?usp=email )
Change subject: mb/protectli/vault_cml: Use chipset dt reference names
......................................................................
mb/protectli/vault_cml: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: I76ec42fccfa42bbe3943e048968a76eec3584ee8
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80054
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/mainboard/protectli/vault_cml/devicetree.cb
1 file changed, 53 insertions(+), 53 deletions(-)
Approvals:
build bot (Jenkins): Verified
Michał Żygowski: Looks good to me, approved
diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb
index dd04aa9..740c3af 100644
--- a/src/mainboard/protectli/vault_cml/devicetree.cb
+++ b/src/mainboard/protectli/vault_cml/devicetree.cb
@@ -141,57 +141,57 @@
device cpu_cluster 0 on end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 on end # SA Thermal device
- device pci 08.0 off end # Gaussian Mixture Model
- device pci 12.0 on end # Thermal Subsystem
- device pci 12.5 off end # UFS SCS
- device pci 12.6 off end # GSPI #2
- device pci 14.0 on end # USB xHCI
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.5 off end # SDCard
- device pci 15.0 off end # I2C #0
- device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 16.5 off end # Management Engine Interface 4
- device pci 17.0 on end # SATA
- device pci 19.0 off end # I2C #4
- device pci 19.1 off end # I2C #5
- device pci 19.2 off end # UART #2
- device pci 1a.0 on end # eMMC
- device pci 1c.0 off end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 on end # PCI Express Port 5 LAN1
- device pci 1c.5 on end # PCI Express Port 6 LAN2
- device pci 1c.6 on end # PCI Express Port 7 LAN3
- device pci 1c.7 on end # PCI Express Port 8 LAN4
- device pci 1d.0 on end # PCI Express Port 9 LAN5
- device pci 1d.1 on end # PCI Express Port 10 LAN6
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 on end # PCI Express Port 12 M.2 WiFi
+ device ref system_agent on end
+ device ref igpu on end
+ device ref dptf on end
+ device ref gna off end
+ device ref thermal on end
+ device ref ufs off end
+ device ref gspi2 off end
+ device ref xhci on end
+ device ref xdci off end
+ device ref sdxc off end
+ device ref i2c0 off end
+ device ref i2c1 off end
+ device ref i2c2 off end
+ device ref i2c3 off end
+ device ref heci1 on end
+ device ref heci2 off end
+ device ref csme_ider off end
+ device ref csme_ktr off end
+ device ref heci3 off end
+ device ref heci4 off end
+ device ref sata on end
+ device ref i2c4 off end
+ device ref i2c5 off end
+ device ref uart2 off end
+ device ref emmc on end
+ device ref pcie_rp1 off end
+ device ref pcie_rp2 off end
+ device ref pcie_rp3 off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 on end # LAN1
+ device ref pcie_rp6 on end # LAN2
+ device ref pcie_rp7 on end # LAN3
+ device ref pcie_rp8 on end # LAN4
+ device ref pcie_rp9 on end # LAN5
+ device ref pcie_rp10 on end # LAN6
+ device ref pcie_rp11 off end
+ device ref pcie_rp12 on end
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
"M.2/E 2230 (M2_WIFI2)" "SlotDataBusWidth1X"
- device pci 1d.4 on # PCI Express Port 13 NVMe
+ device ref pcie_rp13 on # NVMe
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
"M.2/M 2280 (J1)" "SlotDataBusWidth4X"
end
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1e.0 off end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on
+ device ref pcie_rp14 off end
+ device ref pcie_rp15 off end
+ device ref pcie_rp16 off end
+ device ref uart0 off end
+ device ref uart1 off end
+ device ref gspi0 off end
+ device ref gspi1 off end
+ device ref lpc_espi on
chip superio/ite/it8784e
register "TMPIN1.mode" = "THERMAL_RESISTOR"
register "TMPIN2.mode" = "THERMAL_MODE_DISABLED"
@@ -231,12 +231,12 @@
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
- end # LPC Interface
- device pci 1f.1 hidden end # P2SB
- device pci 1f.2 hidden end # Power Management Controller
- device pci 1f.3 on end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
+ end
+ device ref p2sb hidden end
+ device ref pmc hidden end
+ device ref hda on end
+ device ref smbus on end
+ device ref fast_spi on end
+ device ref gbe off end
end
end
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Gerrit-Change-Id: I76ec42fccfa42bbe3943e048968a76eec3584ee8
Gerrit-Change-Number: 80054
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Maximilian Brune has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/80138?usp=email )
Change subject: 3rdparty/opensbi: Update OpenSBI submodule to v1.4
......................................................................
Abandoned
There is already CB:75787
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Gerrit-Change-Id: Ie719c6de0af44da78f23a60bc089821fb9a19129
Gerrit-Change-Number: 80138
Gerrit-PatchSet: 1
Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-MessageType: abandon
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80053?usp=email )
Change subject: mb/dell/snb_ivb_workst: Remove superfluous comments about PCI devices
......................................................................
mb/dell/snb_ivb_workst: Remove superfluous comments about PCI devices
Since all devicetrees from dell/snb_ivb_workstation are using the
reference names for PCI devices now, remove the equivalent comments
documenting their function.
Change-Id: Iac70aa25dd324e1ed5fa0bb995eb995ec3545715
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80053
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb
M src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
M src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
3 files changed, 37 insertions(+), 37 deletions(-)
Approvals:
build bot (Jenkins): Verified
Michał Żygowski: Looks good to me, approved
diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb
index bf04692..28c8d05 100644
--- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb
+++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb
@@ -7,12 +7,12 @@
end
device domain 0 on
- device ref host_bridge on end # Host bridge Host bridge
- device ref peg10 on # PEG1 (blue slot1)
+ device ref host_bridge on end
+ device ref peg10 on # blue slot1
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT1" "SlotDataBusWidth16X"
end
- device ref igd on end # Internal graphics VGA controller
- device ref peg60 off end # PEG2
+ device ref igd on end
+ device ref peg60 off end
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "gpe0_en" = "0x00002a46"
@@ -30,25 +30,25 @@
register "superspeed_capable_ports" = "0x0000000f"
register "xhci_overcurrent_mapping" = "0x08040201"
register "xhci_switchable_ports" = "0x0000000f"
- device ref xhci on end # USB 3.0 Controller
- device ref mei1 off end # Management Engine Interface 1
- device ref mei2 off end # Management Engine Interface 2
- device ref me_ide_r off end # Management Engine IDE-R
- device ref me_kt off end # Management Engine KT
- device ref gbe on end # Intel Gigabit Ethernet
- device ref ehci2 on end # USB2 EHCI #2
- device ref hda on end # High Definition Audio controller
- device ref pcie_rp1 off end # PCIe Port #1
- device ref pcie_rp2 off end # PCIe Port #2
- device ref pcie_rp3 off end # PCIe Port #3
- device ref pcie_rp4 off end # PCIe Port #4
- device ref pcie_rp5 off end # PCIe Port #5
- device ref pcie_rp6 off end # PCIe Port #6
- device ref pcie_rp7 off end # PCIe Port #7
- device ref pcie_rp8 off end # PCIe Port #8
- device ref ehci1 on end # USB2 EHCI #1
- device ref pci_bridge off end # PCI bridge
- device ref lpc on # LPC bridge
+ device ref xhci on end
+ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe on end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 off end
+ device ref pcie_rp2 off end
+ device ref pcie_rp3 off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 off end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
@@ -78,10 +78,10 @@
device pnp 2e.11 off end # PP
end
end
- device ref sata1 on end # SATA Controller 1
- device ref smbus on end # SMBus
- device ref sata2 off end # SATA Controller 2
- device ref thermal on end # Thermal
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal on end
end
end
end
diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
index c17593a..a59d57c 100644
--- a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
+++ b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
@@ -3,12 +3,12 @@
subsystemid 0x1028 0x052c inherit
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "sata_port_map" = "0x7"
- device ref pcie_rp5 on # PCIe Port #5
+ device ref pcie_rp5 on
smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X"
end
- device ref pcie_rp6 on end # PCIe Port #6
- device ref pcie_rp7 on end # PCIe Port #7
- device ref pcie_rp8 on end # PCIe Port #8
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 on end
+ device ref pcie_rp8 on end
end
end
end
diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
index fbc21d8..bbc1bf9 100644
--- a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
+++ b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
@@ -4,16 +4,16 @@
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "sata_port_map" = "0xf"
- device ref pcie_rp3 on # PCIe Port #3
+ device ref pcie_rp3 on
smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X"
end
- device ref pcie_rp5 on # PCIe Port #5
+ device ref pcie_rp5 on
smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X"
end
- device ref pcie_rp6 on end # PCIe Port #6
- device ref pcie_rp7 on end # PCIe Port #7
- device ref pcie_rp8 on end # PCIe Port #8
- device ref pci_bridge on # PCI bridge
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 on end
+ device ref pcie_rp8 on end
+ device ref pci_bridge on
smbios_slot_desc "SlotTypePci" "SlotLengthLong" "SLOT3" "SlotDataBusWidth32Bit"
end
end
--
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Gerrit-Branch: main
Gerrit-Change-Id: Iac70aa25dd324e1ed5fa0bb995eb995ec3545715
Gerrit-Change-Number: 80053
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80052?usp=email )
Change subject: mb/dell/snb_ivb_workst: Convert remaining PCI numbers into references
......................................................................
mb/dell/snb_ivb_workst: Convert remaining PCI numbers into references
Change-Id: I9c6d931d5d5650eb5818116050f9f599a815c315
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80052
Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
M src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
2 files changed, 10 insertions(+), 10 deletions(-)
Approvals:
build bot (Jenkins): Verified
Michał Żygowski: Looks good to me, approved
diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
index bfe453f..c17593a 100644
--- a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
+++ b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
@@ -3,12 +3,12 @@
subsystemid 0x1028 0x052c inherit
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "sata_port_map" = "0x7"
- device pci 1c.4 on # PCIe Port #5
+ device ref pcie_rp5 on # PCIe Port #5
smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X"
end
- device pci 1c.5 on end # PCIe Port #6
- device pci 1c.6 on end # PCIe Port #7
- device pci 1c.7 on end # PCIe Port #8
+ device ref pcie_rp6 on end # PCIe Port #6
+ device ref pcie_rp7 on end # PCIe Port #7
+ device ref pcie_rp8 on end # PCIe Port #8
end
end
end
diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
index 81133ee..fbc21d8 100644
--- a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
+++ b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
@@ -4,16 +4,16 @@
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "sata_port_map" = "0xf"
- device pci 1c.2 on # PCIe Port #3
+ device ref pcie_rp3 on # PCIe Port #3
smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X"
end
- device pci 1c.4 on # PCIe Port #5
+ device ref pcie_rp5 on # PCIe Port #5
smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X"
end
- device pci 1c.5 on end # PCIe Port #6
- device pci 1c.6 on end # PCIe Port #7
- device pci 1c.7 on end # PCIe Port #8
- device pci 1e.0 on # PCI bridge
+ device ref pcie_rp6 on end # PCIe Port #6
+ device ref pcie_rp7 on end # PCIe Port #7
+ device ref pcie_rp8 on end # PCIe Port #8
+ device ref pci_bridge on # PCI bridge
smbios_slot_desc "SlotTypePci" "SlotLengthLong" "SLOT3" "SlotDataBusWidth32Bit"
end
end
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Gerrit-Change-Id: I9c6d931d5d5650eb5818116050f9f599a815c315
Gerrit-Change-Number: 80052
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80051?usp=email )
Change subject: mb/starlabs/starbook/cml: Use chipset dt reference names
......................................................................
mb/starlabs/starbook/cml: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: Ia004de6606a1685822d5567123887c60d89e3119
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80051
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
1 file changed, 49 insertions(+), 49 deletions(-)
Approvals:
Sean Rhodes: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
index 9a71015..5757439 100644
--- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
+++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
@@ -53,15 +53,15 @@
device cpu_cluster 0 on end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 on # SA Thermal Device
+ device ref system_agent on end
+ device ref igpu on end
+ device ref dptf on
register "Device4Enable" = "1"
end
- device pci 12.0 off end # Thermal Subsystem
- device pci 12.5 off end # UFS SCS
- device pci 12.6 off end # GSPI #2
- device pci 14.0 on # USB xHCI
+ device ref thermal off end
+ device ref ufs off end
+ device ref gspi2 off end
+ device ref xhci on
# Motherboard USB Type C
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
@@ -83,16 +83,16 @@
# Internal Bluetooth
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"
end
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.2 on end # SRAM
- device pci 14.3 on # CNVi
+ device ref xdci off end
+ device ref shared_sram on end
+ device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
- device pci 14.5 off end # SDCard
- device pci 15.0 on # I2C0
+ device ref sdxc off end
+ device ref i2c0 on
chip drivers/i2c/hid
register "generic.hid" = ""STAR0001""
register "generic.desc" = ""Touchpad""
@@ -102,34 +102,34 @@
device i2c 2c on end
end
end
- device pci 15.1 off end # I2C1
- device pci 15.2 off end # I2C2
- device pci 15.3 off end # I2C3
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 16.5 off end # Management Engine Interface 4
- device pci 17.0 on # SATA
+ device ref i2c1 off end
+ device ref i2c2 off end
+ device ref i2c3 off end
+ device ref heci1 on end
+ device ref heci2 off end
+ device ref csme_ider off end
+ device ref csme_ktr off end
+ device ref heci3 off end
+ device ref heci4 off end
+ device ref sata on
register "SataSalpSupport" = "1"
# Port 1
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
end
- device pci 19.0 on end # I2C4
- device pci 19.1 off end # I2C5
- device pci 19.2 on end # UART #2
- device pci 1a.0 off end # eMMC
- device pci 1c.0 off end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 off end # PCI Express Port 5
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on # PCI Express Port 9 (SSD x4)
+ device ref i2c4 on end
+ device ref i2c5 off end
+ device ref uart2 on end
+ device ref emmc off end
+ device ref pcie_rp1 off end
+ device ref pcie_rp2 off end
+ device ref pcie_rp3 off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 off end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref pcie_rp9 on # SSD x4
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
@@ -137,14 +137,14 @@
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1e.0 off end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on # LPC Interface
+ device ref pcie_rp10 off end
+ device ref pcie_rp11 off end
+ device ref pcie_rp12 off end
+ device ref uart0 off end
+ device ref uart1 off end
+ device ref gspi0 off end
+ device ref gspi1 off end
+ device ref lpc_espi on
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"
register "gen3_dec" = "0x00fc0201"
@@ -174,14 +174,14 @@
device pnp 4e.19 off end # Power Management Channel 5
end
end
- device pci 1f.1 on end # P2SB
- device pci 1f.2 hidden end # Power Management Controller
- device pci 1f.3 on # Intel HDA
+ device ref p2sb on end
+ device ref pmc hidden end
+ device ref hda on
register "PchHdaAudioLinkHda" = "1"
end
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
+ device ref smbus on end
+ device ref fast_spi on end
+ device ref gbe off end
end
chip drivers/crb
device mmio 0xfed40000 on end
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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80014?usp=email )
Change subject: libpayload/arch/arm64/mmu: Specify ttb_buffer section name explicitly
......................................................................
Patch Set 3:
(1 comment)
File payloads/libpayload/arch/arm64/mmu.c:
https://review.coreboot.org/c/coreboot/+/80014/comment/c2f45134_73407b6a :
PS1, Line 51: __section
> `checkpatch` tricked me to write `__section`, but that doesn't seem to be defined in coreboot.
Uploaded CB:80137.
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