coreboot-gerrit August 2023

coreboot-gerrit@coreboot.org

1 participants
6717 discussions

[XL] Change in coreboot[master]: payloads/cbui: Add new payload CBUI
by Martin L Roth (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Iman Bingi, Patrick Rudolph. Hello Iman Bingi, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/76913?usp=email to review the following change. Change subject: payloads/cbui: Add new payload CBUI ...................................................................... payloads/cbui: Add new payload CBUI Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Ported coreinfo and nvramcui * Allows to modify NVRAM and RTC * Works as ELF payload * Works as Seabios secondary payload * Basic support for multiple languages * Hacky support for BIOS calls (depends on NASM) * Runs in qemu and on real hardware * Use linker script to allocate low memory Shortcomings: * Doesn't work in VGA text mode * Untested on UEFI * int32 relocates itself to low memory Licenses: * GPLv2 (CBUI + libpayload) * BSD (libpayload) * MIT (nuklear) TODO: * Test on as much platforms as possible * Link int32 into low memory This is Patrick Rudolph's original patch, updated by Ben Adu-Boahen to: * Add Read/Write module * This module allows read/write to any hardware component that is readable/writeable Notes: * This is work in progress * Original review: CB:23586 Change-Id: I533d247cd92341c3f91cc6927b875d6d2c460bd7 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbui/.gitignore A payloads/cbui/Kconfig A payloads/cbui/Makefile A payloads/cbui/NuklearUI/NuklearCheckbox.c A payloads/cbui/NuklearUI/NuklearCheckbox.h A payloads/cbui/NuklearUI/NuklearCombo.c A payloads/cbui/NuklearUI/NuklearCombo.h A payloads/cbui/NuklearUI/NuklearCommon.h A payloads/cbui/NuklearUI/NuklearDataGrid.c A payloads/cbui/NuklearUI/NuklearDataGrid.h A payloads/cbui/NuklearUI/NuklearDatePicker.c A payloads/cbui/NuklearUI/NuklearDatePicker.h A payloads/cbui/NuklearUI/NuklearFieldFile.c A payloads/cbui/NuklearUI/NuklearFieldFile.h A payloads/cbui/NuklearUI/NuklearFieldHex.c A payloads/cbui/NuklearUI/NuklearFieldHex.h A payloads/cbui/NuklearUI/NuklearFileChooser.c A payloads/cbui/NuklearUI/NuklearFileChooser.h A payloads/cbui/NuklearUI/NuklearGroup.c A payloads/cbui/NuklearUI/NuklearGroup.h A payloads/cbui/NuklearUI/NuklearHex.c A payloads/cbui/NuklearUI/NuklearHex.h A payloads/cbui/NuklearUI/NuklearInput.c A payloads/cbui/NuklearUI/NuklearInput.h A payloads/cbui/NuklearUI/NuklearIntegerRange.c A payloads/cbui/NuklearUI/NuklearIntegerRange.h A payloads/cbui/NuklearUI/NuklearLabel.c A payloads/cbui/NuklearUI/NuklearLabel.h A payloads/cbui/NuklearUI/NuklearObject.c A payloads/cbui/NuklearUI/NuklearObject.h A payloads/cbui/NuklearUI/NuklearRW.c A payloads/cbui/NuklearUI/NuklearRW.h A payloads/cbui/NuklearUI/NuklearRoot.c A payloads/cbui/NuklearUI/NuklearRwAcpi.c A payloads/cbui/NuklearUI/NuklearRwAcpi.h A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.c A payloads/cbui/NuklearUI/NuklearRwAtaAtapi.h A payloads/cbui/NuklearUI/NuklearRwDimmSpd.c A payloads/cbui/NuklearUI/NuklearRwDimmSpd.h A payloads/cbui/NuklearUI/NuklearRwEc.c A payloads/cbui/NuklearUI/NuklearRwEc.h A payloads/cbui/NuklearUI/NuklearRwIo.c A payloads/cbui/NuklearUI/NuklearRwIo.h A payloads/cbui/NuklearUI/NuklearRwIoIndexData.c A payloads/cbui/NuklearUI/NuklearRwIoIndexData.h A payloads/cbui/NuklearUI/NuklearRwMemory.c A payloads/cbui/NuklearUI/NuklearRwMemory.h A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.c A payloads/cbui/NuklearUI/NuklearRwMemoryIndexData.h A payloads/cbui/NuklearUI/NuklearRwNvram.c A payloads/cbui/NuklearUI/NuklearRwNvram.h A payloads/cbui/NuklearUI/NuklearRwPci.c A payloads/cbui/NuklearUI/NuklearRwPci.h A payloads/cbui/NuklearUI/NuklearRwPciIndexData.c A payloads/cbui/NuklearUI/NuklearRwPciIndexData.h A payloads/cbui/NuklearUI/NuklearRwSmbios.c A payloads/cbui/NuklearUI/NuklearRwSmbios.h A payloads/cbui/NuklearUI/NuklearRwSuperIo.c A payloads/cbui/NuklearUI/NuklearRwSuperIo.h A payloads/cbui/NuklearUI/NuklearStyle.c A payloads/cbui/NuklearUI/NuklearStyle.h A payloads/cbui/NuklearUI/NuklearTabView.c A payloads/cbui/NuklearUI/NuklearTextView.c A payloads/cbui/NuklearUI/NuklearTextView.h A payloads/cbui/NuklearUI/NuklearTextfield.c A payloads/cbui/NuklearUI/NuklearTextfield.h A payloads/cbui/NuklearUI/NuklearTimePicker.c A payloads/cbui/NuklearUI/NuklearTimePicker.h A payloads/cbui/NuklearUI/NuklearUI.h A payloads/cbui/NuklearUI/NuklearVector.c A payloads/cbui/NuklearUI/NuklearVector.h A payloads/cbui/arch/x86/cpuid.c A payloads/cbui/arch/x86/cpuid.h A payloads/cbui/arch/x86/int32.h A payloads/cbui/arch/x86/int32.ld A payloads/cbui/arch/x86/int32.nasm A payloads/cbui/arch/x86/memcpy.c A payloads/cbui/arch/x86/memcpy.h A payloads/cbui/arch/x86/vga.c A payloads/cbui/arch/x86/vga.h A payloads/cbui/cbui.c A payloads/cbui/cbui.h A payloads/cbui/fsys/usbstorage.c A payloads/cbui/fsys/usbstorage.h A payloads/cbui/gfx/coreboot.c A payloads/cbui/gfx/coreboot.h A payloads/cbui/gfx/gfx.c A payloads/cbui/gfx/gfx.h A payloads/cbui/gfx/splash.c A payloads/cbui/gfx/splash.h A payloads/cbui/gfx/vbe.c A payloads/cbui/gfx/vbe.h A payloads/cbui/lang/de.c A payloads/cbui/lang/en.c A payloads/cbui/lang/lang.c A payloads/cbui/lang/lang.h A payloads/cbui/logo/cbui.png A payloads/cbui/lp.config A payloads/cbui/modules/bootlog_module.c A payloads/cbui/modules/cbfs_module.c A payloads/cbui/modules/cmos_module.c A payloads/cbui/modules/coreboot_module.c A payloads/cbui/modules/cpuinfo_module.c A payloads/cbui/modules/license_module.c A payloads/cbui/modules/modules.c A payloads/cbui/modules/modules.h A payloads/cbui/modules/nvram_module.c A payloads/cbui/modules/pci_module.c A payloads/cbui/modules/reboot_module.c A payloads/cbui/modules/rtc_module.c A payloads/cbui/modules/rw_module.c A payloads/cbui/modules/timestamps_module.c A payloads/cbui/modules/usb_module.c A payloads/cbui/smbios/smbios.c A payloads/cbui/smbios/smbios.h A payloads/cbui/smbios/smbios_oem.c A payloads/cbui/smbios/smbios_oem.h A payloads/cbui/smbios/smbios_output.c A payloads/cbui/smbios/smbios_output.h A payloads/cbui/util/buffers.c A payloads/cbui/util/buffers.h A payloads/libpayload/configs/defconfig-cbui 124 files changed, 25,499 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/76913/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76913?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I533d247cd92341c3f91cc6927b875d6d2c460bd7 Gerrit-Change-Number: 76913 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Iman Bingi <imanbingy(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[master]: src/lib/: Enable CBMEM entry store into PRERAM buffer
by Dinesh Gehlot (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Julius Werner, Kapil Porwal, Subrata Banik. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76394?usp=email ) Change subject: src/lib/: Enable CBMEM entry store into PRERAM buffer ...................................................................... Patch Set 7: Code-Review-1 (1 comment) Patchset: PS7: This patch is not required now as the design has been changed. -- To view, visit https://review.coreboot.org/c/coreboot/+/76394?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f45ba71723a23233261953aadda0fe4723c61ea Gerrit-Change-Number: 76394 Gerrit-PatchSet: 7 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 02 Aug 2023 15:13:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: soc/intel/meteorlake/Kconfig: Enable PRERAM VSD buffer for rex
by Dinesh Gehlot (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Dinesh Gehlot, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli. Hello Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76609?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/meteorlake/Kconfig: Enable PRERAM VSD buffer for rex ...................................................................... soc/intel/meteorlake/Kconfig: Enable PRERAM VSD buffer for rex This patch allows the Rex board to store Vendor Specific Data (VSD) during PRERAM. BUG=b:285405031 TEST=Build and boot verified on rex. Change-Id: I1cc3972fa51fea1e7605ac3c33423317044125c5 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/76609/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/76609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cc3972fa51fea1e7605ac3c33423317044125c5 Gerrit-Change-Number: 76609 Gerrit-PatchSet: 4 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: soc/intel/common/block/cse/: Store CSE RW FW version during cse_fw_sync
by Dinesh Gehlot (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Arthur Heymans, Dinesh Gehlot, Julius Werner, Kapil Porwal, Subrata Banik. Hello Kapil Porwal, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76395?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/cse/: Store CSE RW FW version during cse_fw_sync ...................................................................... soc/intel/common/block/cse/: Store CSE RW FW version during cse_fw_sync The current way to store CSE versions requires obtaining the version from CSE, which takes 7 to 19 milliseconds. This patch stores the CSE version while the CSE firmware sync, so it does not need to be retrieved again. BUG=b:285405031 TEST=Build and boot verified on rex. Change-Id: If95ce7e1584aae6be3c431f07f8d8e5001e7854a Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/drivers/intel/ish/ish.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_lite.c 5 files changed, 25 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/76395/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/76395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If95ce7e1584aae6be3c431f07f8d8e5001e7854a Gerrit-Change-Number: 76395 Gerrit-PatchSet: 8 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: src/{include,cpu,lib}: Implement framework for PRERAM VSD store
by Dinesh Gehlot (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Dinesh Gehlot, Julius Werner, Kapil Porwal. Hello Julius Werner, Kapil Porwal, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76393?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: src/{include,cpu,lib}: Implement framework for PRERAM VSD store ...................................................................... src/{include,cpu,lib}: Implement framework for PRERAM VSD store This patch implements a framework that stores Vendor Specific Data (VSD) until CBMEM is intialized. It also copies the VSD back to its original CBMEM once it is initialized. BUG=b:285405031 TEST=Build and boot verified on rex. Change-Id: I0baebb902807d5403800ac18757512bd2a59d2b9 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/cpu/intel/car/romstage.c A src/include/cbmem_vsd.h M src/lib/Makefile.inc A src/lib/cbmem_vsd.c 5 files changed, 80 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/76393/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/76393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0baebb902807d5403800ac18757512bd2a59d2b9 Gerrit-Change-Number: 76393 Gerrit-PatchSet: 11 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: arch/x86: Implement config to Vendor Specific Data during PRERAM
by Dinesh Gehlot (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Dinesh Gehlot, Julius Werner, Kapil Porwal. Hello Julius Werner, Kapil Porwal, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76371?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/x86: Implement config to Vendor Specific Data during PRERAM ...................................................................... arch/x86: Implement config to Vendor Specific Data during PRERAM The patch defines config option PRERAM_CBMEM_VSD, stores Vendor Specific Data (VSD) until CBMEM is initialized. BUG=b:285405031 TEST=Build and boot verified on rex. Change-Id: Ia40f6a33cf2fd0198042c4e6733eea7debb78e8d Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/include/memlayout.h M src/include/symbols.h 4 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/76371/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/76371?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia40f6a33cf2fd0198042c4e6733eea7debb78e8d Gerrit-Change-Number: 76371 Gerrit-PatchSet: 9 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[master]: mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AB-MGCL
by Felix Held (Code Review) 02 Aug '23

02 Aug '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76866?usp=email ) Change subject: mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AB-MGCL ...................................................................... mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AB-MGCL Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for Samsung K4U6E3S4AB-MGCL. BUG=b:293240969 TEST=emerge-dedede coreboot Change-Id: I92a1f2110e74b5d25572e0e86e04b5b32112c1f5 Signed-off-by: tongjian <tongjian(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76866 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/storo/memory/Makefile.inc M src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 3 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc b/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc index 2f5ba21..95e640a 100644 --- a/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/storo/memory/Makefile.inc @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/storo/memory src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/storo/memory src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt index e627949..1d288e1 100644 --- a/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/storo/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/storo/memory src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/storo/memory src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) @@ -9,3 +9,4 @@ MT53E1G32D2NP-046 WT:A 1 (0001) H9HCNNNCPMMLXR-NEE 2 (0010) K4U6E3S4AA-MGCR 0 (0000) +K4U6E3S4AB-MGCL 0 (0000) diff --git a/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt index 901ff7b..9223fcc 100644 --- a/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/storo/memory/mem_parts_used.txt @@ -14,3 +14,4 @@ MT53E1G32D2NP-046 WT:A H9HCNNNCPMMLXR-NEE K4U6E3S4AA-MGCR +K4U6E3S4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/76866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92a1f2110e74b5d25572e0e86e04b5b32112c1f5 Gerrit-Change-Number: 76866 Gerrit-PatchSet: 2 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: soc/intel/mtl: Change default for debug consent from 3 to 6
by Paul Menzel (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Kane Chen, Sridhar Siricilla, Tarun Tuli. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76880?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/mtl: Change default for debug consent from 3 to 6 ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76880/comment/ca60e83a_be7e6696 : PS3, Line 9: USB DBC is very helpful for SoC debug. : TraceHub needs to be enabled in coreboot ifdebug consent == 2 or 4. : Debug consent == 6 enables USB DBC without TraceHub enabled. : This patch changes debug consent to 6 in default to provide basic SoC : debug capability. Please do not wrap a line, just because a sentence ends, or add a blank line between paragraphs. https://review.coreboot.org/c/coreboot/+/76880/comment/ba6e287c_db326896 : PS3, Line 14: Please also mention, you update the config description/help text. -- To view, visit https://review.coreboot.org/c/coreboot/+/76880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2 Gerrit-Change-Number: 76880 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 02 Aug 2023 14:44:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/dedede/var/boxy: Add power limits for N4500/N5100
by Paul Menzel (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Stanley Wu, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76876?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/dedede/var/boxy: Add power limits for N4500/N5100 ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76876/comment/7c356618_cdb9a324 : PS1, Line 12: TEST=emerge-dedede coreboot and read correct value on boxy > BIOS log will show the values during post. Maybe paste those into the “test section” of the git commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/76876?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715 Gerrit-Change-Number: 76876 Gerrit-PatchSet: 2 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Aug 2023 14:42:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/rex/var/screebo: Compatible with RTS5227S and GL9750
by Paul Menzel (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Jakub Czapiga, Kun Liu, Tarun Tuli. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76912?usp=email ) Change subject: mb/google/rex/var/screebo: Compatible with RTS5227S and GL9750 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76912/comment/765439b9_07c002dc : PS1, Line 7: Compatible with RTS5227S and GL9750 Please make it a statement by adding a verb (in imperative mood). See `git log --oneline` for examples. -- To view, visit https://review.coreboot.org/c/coreboot/+/76912?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98aa0d3e52c355f6c1528c912a6fa0f32652dda8 Gerrit-Change-Number: 76912 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Aug 2023 14:41:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2023