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Change subject: util/abuild: Add per-build statistics tarfile
......................................................................
Patch Set 2:
(3 comments)
File util/abuild/abuild:
https://review.coreboot.org/c/coreboot/+/75803/comment/4270129d_5fff3f0e :
PS2, Line 440: echo "$BUILD_NAME" >> "$PASSED_BOARDS"
Not in the scope, but compile_target runs concurrently with upto 32 concurrent cpus. Is there some implicit locking happening, or is it possible that some lines are lost here?
https://review.coreboot.org/c/coreboot/+/75803/comment/4798c054_98e08091 :
PS2, Line 449: echo "$BUILD_NAME" >> "$FAILED_BOARDS"
Same here.
https://review.coreboot.org/c/coreboot/+/75803/comment/f0fbe87e_9f566842 :
PS2, Line 457: sha256sum "${build_dir}/coreboot.rom" >> "${checksum_file}_platform"
Same here.
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Change subject: payloads/edk2: Enable MMIO serial output for AMD Zen platforms
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Nice work. If this is fixed in EDK2, please link to the commit.
it's fixed in my uefipayload_202306 branch (which is now the coreboot default) and I'm working on getting it upstreamed. It's also 3 atomic commits
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Change subject: mb/google/rex/var/screebo: Compatible with RTS5227S and GL9750
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/rex/variants/screebo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/76912/comment/230d6482_1c85d816 :
PS1, Line 23: SD_GL9750
do you also want to select `DRIVERS_GENESYSLOGIC_GL9750` for Screebo?
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Change subject: util/abuild: Add per-build statistics tarfile
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> I want to fix these in stdout before merge: […]
Done
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Change subject: soc/intel/mtl: Change default for debug consent from 3 to 6
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/intel/mtl: Change default for debug consent from 3 to 6
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76880/comment/4f7d7ba3_c1b3bcbe :
PS2, Line 7: Set SOC_INTEL_METEORLAKE_DEBUG_CONSENT to 6
> Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/76880/comment/7b1961d6_30febdfb :
PS2, Line 9: SOC_INTEL_METEORLAKE_DEBUG_CONSENT=6 is more common use case
: for soc debug with usb dbc.
> Please extend, and so why it is more common.
Done
File src/soc/intel/meteorlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/76880/comment/013f0019_fa38aed3 :
PS2, Line 357: 0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready,
: 6:Enable Trace Power-Off, 7:Manual
> So 3, used before wasn’t even a valid value?
3 is not used in MTL.
pls refer to PlatformDebugOption src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
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Change subject: mb/google/rex/var/screebo: Compatible with RTS5227S and GL9750
......................................................................
Patch Set 1: Code-Review+1
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Hello Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/76880?usp=email
to look at the new patch set (#3).
Change subject: soc/intel/mtl: Change default for debug consent from 3 to 6
......................................................................
soc/intel/mtl: Change default for debug consent from 3 to 6
USB DBC is very helpful for SoC debug.
TraceHub needs to be enabled in coreboot ifdebug consent == 2 or 4.
Debug consent == 6 enables USB DBC without TraceHub enabled.
This patch changes debug consent to 6 in default to provide basic SoC
debug capability.
TEST=Boot to OS on screebo and DBC connection is OK.
Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2
Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 4 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/76880/3
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Change subject: mb/google/rex/var/screebo: Compatible with RTS5227S and GL9750
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/rex/var/screebo: Compatible with RTS5227S and GL9750
......................................................................
mb/google/rex/var/screebo: Compatible with RTS5227S and GL9750
Compatible with RTS5227S and GL9750
BUG=b:284273384
TEST=emerge-rex coreboot
Change-Id: I98aa0d3e52c355f6c1528c912a6fa0f32652dda8
Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/rex/variants/screebo/overridetree.cb
1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/76912/1
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index a7b7d54..9320011 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -18,6 +18,11 @@
option TOUCHSCREEN_ILITEK 1
option TOUCHSCREEN_ELAN 2
end
+ field DB_SD 11 12
+ option SD_ABSENT 0
+ option SD_GL9750 1
+ option SD_RTS5227S 2
+ end
end
chip soc/intel/meteorlake
@@ -251,7 +256,10 @@
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)"
register "srcclk_pin" = "7"
- device generic 0 on end
+ device generic 0 on
+ probe DB_SD SD_GL9750
+ probe DB_SD SD_RTS5227S
+ end
end
end
device ref tbt_pcie_rp0 on end
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