coreboot-gerrit August 2023

coreboot-gerrit@coreboot.org

1 participants
6717 discussions

[S] Change in coreboot[master]: mb/google/nissa/var/pirrha: Generate SPD ID for supported memory part
by SH Kim (Code Review) 02 Aug '23

02 Aug '23

SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76881?usp=email ) Change subject: mb/google/nissa/var/pirrha: Generate SPD ID for supported memory part ...................................................................... mb/google/nissa/var/pirrha: Generate SPD ID for supported memory part Add pirrha supported memory parts in mem_parts_used.txt, generate SPD IDs for them. 1. K3KL8L80CM-MGCT (Samsung) 2. K3KL6L60GM-MGCT (Samsung) BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/brya/variants/pirrha/memory/Makefile.inc M src/mainboard/google/brya/variants/pirrha/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt 3 files changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/76881/1 diff --git a/src/mainboard/google/brya/variants/pirrha/memory/Makefile.inc b/src/mainboard/google/brya/variants/pirrha/memory/Makefile.inc index eace2e4..248011d 100644 --- a/src/mainboard/google/brya/variants/pirrha/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/pirrha/memory/Makefile.inc @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pirrha/memory src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 1(0b0001) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/brya/variants/pirrha/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pirrha/memory/dram_id.generated.txt index fa24790..2e5b4ad 100644 --- a/src/mainboard/google/brya/variants/pirrha/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/pirrha/memory/dram_id.generated.txt @@ -1 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pirrha/memory src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K3KL8L80CM-MGCT 0 (0000) +K3KL6L60GM-MGCT 1 (0001) diff --git a/src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt index 9621137..9de4d15 100644 --- a/src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt @@ -9,3 +9,5 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +K3KL8L80CM-MGCT +K3KL6L60GM-MGCT -- To view, visit https://review.coreboot.org/c/coreboot/+/76881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664 Gerrit-Change-Number: 76881 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO
by Michał Kopeć (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Michał Żygowski, Paul Menzel, Subrata Banik, Tarun Tuli. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76418?usp=email ) Change subject: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO ...................................................................... Patch Set 7: Code-Review+2 (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/76418/comment/80ea325a_45ffef35 : PS6, Line 273: (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) && CONFIG(FSP_USE_REPO)) > > please, no spaces at the start of a line […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76418?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Gerrit-Change-Number: 76418 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 02 Aug 2023 10:19:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/nissa/var/joxer: support DPTF oem_variables
by Sumeet R Pawnikar (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Derek Huang, Eric Lai, Felix Held, Mark Hsieh, Scott Chao, Shou-Chieh Hsu, Tarun Tuli. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76773?usp=email ) Change subject: mb/google/nissa/var/joxer: support DPTF oem_variables ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e52ac624f7d7628cce3035a2bac67fc527bc167 Gerrit-Change-Number: 76773 Gerrit-PatchSet: 6 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 02 Aug 2023 10:17:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Disable PCIe clock gating
by Patrick Rudolph (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Angel Pons, Subrata Banik, Tarun Tuli. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76687?usp=email ) Change subject: soc/intel/alderlake: Disable PCIe clock gating ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76687/comment/1934f8ad_05aa88df : PS1, Line 8: > > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` […] Done File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/76687/comment/4dee682e_4aafa2b3 : PS1, Line 925: PCIe PCH > nit: PCH PCIe Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76687?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I673bbdbadc9afbed6a7bd5ce9f35dc70716d875b Gerrit-Change-Number: 76687 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 02 Aug 2023 10:13:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Disable PCIe clock gating
by Patrick Rudolph (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Angel Pons, Subrata Banik, Tarun Tuli. Hello Angel Pons, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76687?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: soc/intel/alderlake: Disable PCIe clock gating ...................................................................... soc/intel/alderlake: Disable PCIe clock gating Intel requires that all enabled PCIe PCH ports have a CLK_REQ signal connected. The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 link-state is also entered on PCI-PM D3, even with ASPM L1 disabled. When no CLK_REQ signal is used, for example when it's using a free running clock the silicon will never wake from L1 link state. This will trigger a MCE. Starting with FSP MR4 the UPD 'PchPcieClockGating' allows to work around this issue by disabling ClockGating. Disabling ClockGating should be avoided as the silicon draws more power when it is idle. TEST: Verified on two boards, one with missing CLK_REQ on a PCH root port, that the code does the right decision to disable UPD PchPcieClockGating when necessary. Change-Id: I673bbdbadc9afbed6a7bd5ce9f35dc70716d875b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/76687/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76687?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I673bbdbadc9afbed6a7bd5ce9f35dc70716d875b Gerrit-Change-Number: 76687 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotion
by Sumeet R Pawnikar (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Sukumar Ghorai, Tarun Tuli. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76826?usp=email ) Change subject: soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotion ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76826?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc60bd297271fcb3000c0298af71208e3be60fc Gerrit-Change-Number: 76826 Gerrit-PatchSet: 6 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Wed, 02 Aug 2023 10:05:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: soc/intel/mtl: Set SOC_INTEL_METEORLAKE_DEBUG_CONSENT to 6
by Sridhar Siricilla (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Jakub Czapiga, Kane Chen, Kapil Porwal, Subrata Banik, Tarun Tuli. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76880?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/mtl: Set SOC_INTEL_METEORLAKE_DEBUG_CONSENT to 6 ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/76880/comment/3089bb83_44280057 : PS1, Line 347: 3 6 -- To view, visit https://review.coreboot.org/c/coreboot/+/76880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2 Gerrit-Change-Number: 76880 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 02 Aug 2023 09:56:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/dedede/var/boxy: Update power limits
by Sumeet R Pawnikar (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Derek Huang, Stanley Wu, Subrata Banik. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76877?usp=email ) Change subject: mb/google/dedede/var/boxy: Update power limits ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76877?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4257dab358f066ebd13b6f251e8a5258a72fbd39 Gerrit-Change-Number: 76877 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Aug 2023 09:55:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/dedede/var/boxy: Add power limits for N4500/N5100
by Sumeet R Pawnikar (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Derek Huang, Paul Menzel, Stanley Wu, Subrata Banik. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76876?usp=email ) Change subject: mb/google/dedede/var/boxy: Add power limits for N4500/N5100 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76876?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715 Gerrit-Change-Number: 76876 Gerrit-PatchSet: 2 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 02 Aug 2023 09:47:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
by Sridhar Siricilla (Code Review) 02 Aug '23

02 Aug '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Pratikkumar V Prajapati, Ravishankar Sarawadi, Tarun Tuli. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75626?usp=email ) Change subject: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d Gerrit-Change-Number: 75626 Gerrit-PatchSet: 15 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 02 Aug 2023 09:46:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2023