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Change subject: arch/arm64: Hook up ACPI table generation
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File src/acpi/Kconfig:
https://review.coreboot.org/c/coreboot/+/76071/comment/5cd29575_5f4e46a6 :
PS6, Line 78: config MAX_ACPI_TABLE_SIZE_KB
This is sort of missing 'depends on HAVE_ACPI_TABLES' but we probably should group most of the file under a single 'if HAVE_ACPI_TABLES' anyway.
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Change subject: acpi: Add functions to declare ARM GIC V3 hardware
......................................................................
Patch Set 5:
(2 comments)
File src/arch/arm64/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/76132/comment/54ed1509_ed66329c :
PS5, Line 122: ramstage-$(CONFIG_ACPI_COMMON_MADT_GICC_V3) += ../../acpi/acpi_gic.c
> Why put that here and not in acpi/Makefile.inc?
Similar to how arch/x86 includes apic/hpet/dmar acpi code.
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/76132/comment/271beb87_fd951b07 :
PS5, Line 1571: uintptr_t get_gicr_base(void);
> These are platform callbacks, right? They should probably be a bit better namespaced, e.g. […]
Done
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Change subject: acpi: Add function to add ARM PL011 to ACPI DBG2
......................................................................
acpi: Add function to add ARM PL011 to ACPI DBG2
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I3c3f7f579ec0ec4fdb72e1f6b785026daab17bac
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
2 files changed, 54 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/76297/4
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Verified+1 by build bot (Jenkins)
Change subject: acpi: Add functions to declare ARM GIC V3 hardware
......................................................................
acpi: Add functions to declare ARM GIC V3 hardware
For GICD and GICR a SOC needs to implement 2 callbacks to get the base
of those interrupt controllers.
For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3
devices in a similar fashion to how x86 lapics are added. It's up to the
SOC to add those devices to the tree.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f
---
M src/acpi/Kconfig
M src/acpi/acpi.c
A src/acpi/acpi_gic.c
M src/arch/arm64/Makefile.inc
M src/include/acpi/acpi.h
M src/include/device/path.h
6 files changed, 108 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/76132/6
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Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76880?usp=email )
Change subject: soc/intel/mtl: Set SOC_INTEL_METEORLAKE_DEBUG_CONSENT to 6
......................................................................
soc/intel/mtl: Set SOC_INTEL_METEORLAKE_DEBUG_CONSENT to 6
SOC_INTEL_METEORLAKE_DEBUG_CONSENT=6 is more common use case
for soc debug with usb dbc.
TEST=boot to os on screebo and dbc connection is OK.
Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2
Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 3 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/76880/1
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 2eb1405..b34daec 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -346,7 +346,7 @@
int "Debug Consent for MTL"
# USB DBC is more common for developers so make this default to 3 if
# SOC_INTEL_DEBUG_CONSENT=y
- default 3 if SOC_INTEL_DEBUG_CONSENT
+ default 6 if SOC_INTEL_DEBUG_CONSENT
default 0
help
This is to control debug interface on SOC.
@@ -354,9 +354,8 @@
PlatformDebugConsent in FspmUpd.h has the details.
Desired platform debug type are
- 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
- 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
- 6:Enable (2-wire DCI OOB), 7:Manual
+ 0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready,
+ 6:Enable Trace Power-Off, 7:Manual
config DATA_BUS_WIDTH
int
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Change subject: arch/arm64: Hook up ACPI table generation
......................................................................
arch/arm64: Hook up ACPI table generation
Linux is able to detect and use ACPI tables on an out of tree target
using hacked version of u-boot to pass ACPI through UEFI.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I4f60c546ec262ffb4d447fe6476844cf5a1b756d
---
M src/acpi/Kconfig
M src/arch/arm64/tables.c
M src/arch/x86/Kconfig
3 files changed, 23 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/76071/6
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Change subject: arch/arm64: Hook up ACPI table generation
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76071/comment/80474058_8ed9dad3 :
PS4, Line 9: Linux
> What version did you test with?
No idea. I did not test this. @Max?
https://review.coreboot.org/c/coreboot/+/76071/comment/24fb2342_722759c2 :
PS4, Line 9: Linux is able to detect and use ACPI tables on an out of tree target
> > `Possible repeated word: 'via'` […]
Done
https://review.coreboot.org/c/coreboot/+/76071/comment/6b279a09_e3e9b3c6 :
PS4, Line 10: using hacked version of u-boot to pass the via via UEFI.
> Ah, you mean instead of one of the words *via*.
Done
File src/arch/arm64/tables.c:
https://review.coreboot.org/c/coreboot/+/76071/comment/97f5c122_bde447ee :
PS4, Line 18: printk(BIOS_ERR, "Increase ACPI size\n");
> I see that this is the same as what x86 already does, but this is a truly terrible API. We're running straight over other CBMEM spaces and this isn't even an assert(), just a BIOS_ERR print. Can we (in a separate patch effort) fix write_acpi_tables() to actually take an upper bound and respect it?
The whole acpi generation code is very unsafe... I added an assert here but making ACPI generation more safe is a larger effort.
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