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Change subject: acpi/acpi.c: Move setting FADT SCI INT to arch specific code
......................................................................
Patch Set 3: Code-Review+2
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Change subject: acpi/acpi.c: Move MADT lapic addr to APIC code
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76070/comment/1767814c_8bbdee95 :
PS4, Line 7: acpi/acpi.c: Move MADT lapic addr to APIC code
acpi/acpi.c: Add and use acpi_arch_fill_madt()
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Change subject: arch/arm64: Hook up ACPI table generation
......................................................................
arch/arm64: Hook up ACPI table generation
Linux is able to detect and use ACPI tables on an out of tree target
using hacked version of u-boot to pass the via via UEFI.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I4f60c546ec262ffb4d447fe6476844cf5a1b756d
---
M src/arch/arm64/Kconfig
M src/arch/arm64/tables.c
2 files changed, 20 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/76071/5
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Change subject: acpi.c: Fill in >4G FADT entries correctly
......................................................................
acpi.c: Fill in >4G FADT entries correctly
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I84ab0068e8409a5e525ddc781347087680d80640
---
M src/acpi/acpi.c
1 file changed, 10 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/76179/6
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Change subject: acpi.c: Fill in >4G FADT entries correctly
......................................................................
Patch Set 5:
(2 comments)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/76179/comment/cf3b6d02_290af735 :
PS5, Line 1092: fadt->x_firmware_ctl_h = (uint32_t)((uint64_t)(uintptr_t)facs >> 32);
> Wouldn't write shift work here without warnings with just:
> (uintptr_t)facs >> 32
That results in shift-count-overflow warning/error on 32bit targets. All the casts are to make the compiler happy in both 32 and 64bit cases.
https://review.coreboot.org/c/coreboot/+/76179/comment/a5cd44ff_88738af3 :
PS5, Line 1096: fadt->dsdt = (unsigned long)dsdt;
> (uintptr_t) for consistency here?
Done
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Change subject: acpi.c: Find FACS using 64bit address fields
......................................................................
Patch Set 2:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/76293/comment/ad0d1637_79074969 :
PS2, Line 1633: | (uint64_t)fadt->x_firmware_ctl_h << 32);
> For some reason, src/southbridge/amd/pi/hudson/fadt.c has this:
>
> fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */
> fadt->x_firmware_ctl_h = 0;
>
> The only hardware using this now, pcengines/apu[2..6] do not support S3 but I think this change would break S3 resume if FACS was ever located above 4G.
I guess that can safely be removed.
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Change subject: soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotion
......................................................................
soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotion
FSP has a parameter to enable/disable c1-state autodemotion feature.
Boards/Baseboard can choose to use this feature as per requirement.
This patch hooks up this parameter to devicetree.
BUG=b:286328295
TEST=Check code compiles & boot google/rex, and correct value has been
passed to FSP.
Change-Id: I2cc60bd297271fcb3000c0298af71208e3be60fc
Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
---
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/fsp_params.c
2 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/76826/6
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Change subject: arch/x86: Adjust stack pointer to point to dummy argument
......................................................................
Patch Set 1: Code-Review-2
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76878/comment/f7196e60_d97dc949 :
PS1, Line 9: The patch pushes dummy argument so that stack pointer points to this
: dummy element instead of coreboot table address as depthcharge picks the
: second element from top of the stack as coreboot table address.
The coreboot Documentation specifies that payloads need to be entered in 32bit mode and while not documented the argument containing the coreboot tables just follows the ABI which here means pushing a 32bit variable on the stack. I think you should fix this in depthcharge rather than break all other payloads that consume the calling argument to pass the coreboot tables.
Patchset:
PS1:
This looks like a depthcharge problem and not a coreboot problem.
File src/arch/x86/c_exit.S:
https://review.coreboot.org/c/coreboot/+/76878/comment/6aa843ed_5f514c7d :
PS1, Line 32: subl $12, %esp
Stack is not aligned to 16 any longer when calling a function.
https://review.coreboot.org/c/coreboot/+/76878/comment/ae7c9802_a04d364a :
PS1, Line 34: pushl $0 /* Dummy argument */
The 32bit ABI has argument 0 pushed last to the stack. This will break all payloads that expect it.
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