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[M] Change in coreboot[master]: soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros
by Matt DeVillier (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Raul Rangel. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76886?usp=email ) Change subject: soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63a284b26081c170a217b082b100c482f6158e7e Gerrit-Change-Number: 76886 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Aug 2023 13:48:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros
by Felix Held (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76886?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros ...................................................................... soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros To have both the PCI function number and the register offset into the config space of that function of the data fabric device in the data fabric register definitions, introduce and use the DF_REG_ID, DF_REG_FN and DF_REG_REG macros. The DF_REG_ID macro is used for register definitions where both the function number and the register offset are specified, and the DF_REG_FN and DF_REG_REG macros are used to extract the function number and the register offset from the register defines. This will allow having one define for accessing an indexed group of registers that are on different functions of the data fabric device. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I63a284b26081c170a217b082b100c482f6158e7e --- M src/soc/amd/cezanne/include/soc/data_fabric.h M src/soc/amd/common/block/data_fabric/data_fabric_helper.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h A src/soc/amd/common/block/include/amdblocks/data_fabric_defs.h M src/soc/amd/glinda/include/soc/data_fabric.h M src/soc/amd/mendocino/include/soc/data_fabric.h M src/soc/amd/phoenix/include/soc/data_fabric.h M src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/include/soc/data_fabric.h 10 files changed, 97 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/76886/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63a284b26081c170a217b082b100c482f6158e7e Gerrit-Change-Number: 76886 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common/tcss: Configure USB-C ports with attached devices
by Matt DeVillier (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Eric Lai, Jakub Czapiga, John Su, John Zhao, Kapil Porwal, Sean Rhodes, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72909?usp=email ) Change subject: soc/intel/common/tcss: Configure USB-C ports with attached devices ...................................................................... Patch Set 5: (2 comments) File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/72909/comment/19a43cea_59b9fc67 : PS4, Line 357: if ((ret < 0) || !mux_info.usb) > could you please change it as below […] Done https://review.coreboot.org/c/coreboot/+/72909/comment/95bfe50b_df4487bf : PS4, Line 361: ret = send_pmc_connect_request(i, &mux_info, port_info); > Correct. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/72909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812 Gerrit-Change-Number: 72909 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: CoolStar <coolstarorganization(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 12:56:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Merge TME new key gen and exclusion range configs
by Felix Held (Code Review) 03 Aug '23

03 Aug '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76879?usp=email ) Change subject: soc/intel/common: Merge TME new key gen and exclusion range configs ...................................................................... soc/intel/common: Merge TME new key gen and exclusion range configs Merge TME_KEY_REGENERATION_ON_WARM_BOOT and TME_EXCLUDE_CBMEM_ENCRYPTION config options under new config option named TME_KEY_REGENERATION_ON_WARM_BOOT. Program Intel TME to generate a new key for each warm boot. TME always generates a new key on each cold boot. With this option enabled TME generates a new key even in warm boot. Without this option TME reuses the key for warm boot. If a new key is generated on warm boot, DRAM contents from previous warm boot will not get decrypted. This creates issue in accessing CBMEM region from previous warm boot. To mitigate the issue coreboot also programs exclusion range. Intel TME does not encrypt physical memory range set in exclusion range. Current coreboot implementation programs TME to exclude CBMEM region. When this config option is enabled, coreboot instructs Intel FSP to program TME to generate a new key on every warm boot and also exclude CBMEM region from being encrypted by TME. BUG=b:276120526 TEST=Able to build rex. Change-Id: I19d9504229adb1abff2ef394c4ca113c335099c2 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76879 Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 10 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Sridhar Siricilla: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index fb1e251..316ec40 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -142,7 +142,7 @@ it would get enabled. If CPU supports MKTME, this same config option enables MKTME. -config TME_GENERATE_NEW_KEY_ON_WARM_BOOT +config TME_KEY_REGENERATION_ON_WARM_BOOT bool "Generate new TME key on each warm boot" depends on INTEL_TME default n @@ -152,24 +152,15 @@ generates a new key even in warm boot. Without this option TME reuses the key for warm boot. -config TME_EXCLUDE_CBMEM_ENCRYPTION - bool "Exclude CBMEM from TME encryption" - depends on INTEL_TME - default n - help - This option allows to exclude the CBMEM region from being encrypted by - Intel TME. When TME is enabled it encrypts whole DRAM. TME provides - option to carve out a region of physical memory to get excluded from - encryption. With this config enabled, CBMEM region does not get - encrypted by TME. If TME is not programmed to generate a new key in - warm boot, exclusion range does not need be programmed due to the - fact that TME uses same key in warm boot if - TME_GENERATE_NEW_KEY_ON_WARM_BOOT is not set. But if TME is programmed - to generate a new key in warm boot, contents of the CBMEM get - encrypted with a new key in each warm boot case hence, that leads to - loss of CBMEM data from previous warm boot. So enabling this config - allows CBMEM region to get excluded from being encrypted and can be - accessible irrespective of the type of the platform reset. + If a new key is generated on warm boot, DRAM contents from previous + warm boot will not get decrypted. This creates issue in accessing + CBMEM region from previous warm boot. To mitigate the issue coreboot + also programs exclusion range. Intel TME does not encrypt physical + memory range set in exclusion range. Current coreboot implementation + programs TME to exclude CBMEM region. When this config option is + enabled, coreboot instructs Intel FSP to program TME to generate + a new key on every warm boot and also exclude CBMEM region from being + encrypted by TME. config CPU_XTAL_HZ int -- To view, visit https://review.coreboot.org/c/coreboot/+/76879?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d9504229adb1abff2ef394c4ca113c335099c2 Gerrit-Change-Number: 76879 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google: Add more comment on GFX devices for the future reference
by Felix Held (Code Review) 03 Aug '23

03 Aug '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76776?usp=email ) Change subject: mb/google: Add more comment on GFX devices for the future reference ...................................................................... mb/google: Add more comment on GFX devices for the future reference Add more details to instruct future boards/models implementers regarding how GFX devices should be added. If HDMI and DP connectors are enumerated by the kernel in /sys/class/drm/ then corresponding GFX device should be added to ACPI. It is possible that some connectors do not have dedicated ports, but still enumerated. The order of GFX devices is DDIA -> DDIB -> TCPX. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224 Signed-off-by: Won Chung <wonchung(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76776 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/skolas/overridetree.cb M src/mainboard/google/brya/variants/skolas4es/overridetree.cb M src/mainboard/google/rex/variants/rex0/overridetree.cb 6 files changed, 17 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 31d78a4a..50fadbc 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -122,6 +122,7 @@ # DDIA for eDP register "device[0].name" = ""LCD"" # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 register "device[2].name" = ""DD02"" @@ -135,7 +136,7 @@ register "device[4].name" = ""DD04"" register "device[4].use_pld" = "true" register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" - # TCP3 (DP-4) unused + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 register "device[5].name" = ""DD05"" device generic 0 on end end diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 26b15e2..e825996 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -117,13 +117,13 @@ register "device[2].name" = ""DD02"" register "device[2].use_pld" = "true" register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - # TCP1 (DP-2) unused + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 register "device[3].name" = ""DD03"" # TCP2 (DP-3) for port C2 register "device[4].name" = ""DD04"" register "device[4].use_pld" = "true" register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - # TCP3 (DP-4) unused + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 register "device[5].name" = ""DD05"" device generic 0 on probe EPS PRIVACY_SCREEN @@ -139,13 +139,13 @@ register "device[2].name" = ""DD02"" register "device[2].use_pld" = "true" register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - # TCP1 (DP-2) unused + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 register "device[3].name" = ""DD03"" # TCP2 (DP-3) for port C2 register "device[4].name" = ""DD04"" register "device[4].use_pld" = "true" register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - # TCP3 (DP-4) unused + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 register "device[5].name" = ""DD05"" device generic 0 on probe EPS PRIVACY_SCREEN_ABSENT diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 6509061..a2cac5a 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -98,13 +98,13 @@ register "device[2].name" = ""DD02"" register "device[2].use_pld" = "true" register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - # TCP1 (DP-2) unused + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 register "device[3].name" = ""DD03"" # TCP2 (DP-3) for port C2 register "device[4].name" = ""DD04"" register "device[4].use_pld" = "true" register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - # TCP3 (DP-4) unused + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 register "device[5].name" = ""DD05"" device generic 0 on probe EPS PRIVACY_SCREEN @@ -120,13 +120,13 @@ register "device[2].name" = ""DD02"" register "device[2].use_pld" = "true" register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - # TCP1 (DP-2) unused + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 register "device[3].name" = ""DD03"" # TCP2 (DP-3) for port C2 register "device[4].name" = ""DD04"" register "device[4].use_pld" = "true" register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - # TCP3 (DP-4) unused + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 register "device[5].name" = ""DD05"" device generic 0 on probe EPS PRIVACY_SCREEN_ABSENT diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb index 1740432..8cc5157 100644 --- a/src/mainboard/google/brya/variants/skolas/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb @@ -122,6 +122,7 @@ # DDIA for eDP register "device[0].name" = ""LCD"" # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 register "device[2].name" = ""DD02"" @@ -135,7 +136,7 @@ register "device[4].name" = ""DD04"" register "device[4].use_pld" = "true" register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" - # TCP3 (DP-4) unused + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 register "device[5].name" = ""DD05"" device generic 0 on end end diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb index 0c0aa82..407e0a1 100644 --- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb @@ -118,6 +118,7 @@ # DDIA for eDP register "device[0].name" = ""LCD"" # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 register "device[2].name" = ""DD02"" @@ -131,7 +132,7 @@ register "device[4].name" = ""DD04"" register "device[4].use_pld" = "true" register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" - # TCP3 (DP-4) unused + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 register "device[5].name" = ""DD05"" device generic 0 on end end diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 793a46d..0cbea7b 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -154,18 +154,19 @@ # DDIA for eDP register "device[0].name" = ""LCD"" # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB register "device[1].name" = ""DD01"" # TCP0 (DP-1) for port C0 register "device[2].name" = ""DD02"" register "device[2].use_pld" = "true" register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - # TCP1 (DP-2) unused + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 register "device[3].name" = ""DD03"" # TCP2 (DP-3) for port C1 register "device[4].name" = ""DD04"" register "device[4].use_pld" = "true" register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - # TCP3 (DP-4) unused + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 register "device[5].name" = ""DD05"" device generic 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/76776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224 Gerrit-Change-Number: 76776 Gerrit-PatchSet: 6 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/nissa/var/craaskov: Add overridetree
by Felix Held (Code Review) 03 Aug '23

03 Aug '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76662?usp=email ) Change subject: mb/google/nissa/var/craaskov: Add overridetree ...................................................................... mb/google/nissa/var/craaskov: Add overridetree Add override devicetree based on schematics(ver. 20230714). BUG=b:290248526 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id002282d91dc94b00f5d133203b62ca39d6cae6d Signed-off-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76662 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/craaskov/overridetree.cb 1 file changed, 226 insertions(+), 1 deletion(-) Approvals: Sumeet R Pawnikar: Looks good to me, approved Derek Huang: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb index 4f2c04a..cd020a5 100644 --- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb +++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb @@ -1,6 +1,231 @@ chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" - device domain 0 on + # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. + # Bit 2 - C1 has a redriver which does SBU muxing. + # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. + register "tcss_aux_ori" = "1" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | TOF/ALS | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 2 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + device domain 0 on + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "150" + register "generic.stop_off_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end #I2C1 + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""10EC5650"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5650"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-mode"" + register "property_list[0].integer" = "2" + device i2c 1a on end + end + end #I2C3 + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "detect" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref pcie_rp7 off end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/76662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id002282d91dc94b00f5d133203b62ca39d6cae6d Gerrit-Change-Number: 76662 Gerrit-PatchSet: 11 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer
by Subrata Banik (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Andrey Petrov, Kapil Porwal, Nick Vaccaro, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76921?usp=email ) Change subject: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76921/comment/584658e2_7ba5a161 : PS3, Line 15: bootloader > Wrong term? Acknowledged https://review.coreboot.org/c/coreboot/+/76921/comment/e9b19b26_bec97646 : PS3, Line 18: It also adds a : new config (BMP_LOGO_TO_GOP_BLT) to ensure backward compatibility with : older generation FSP. > Can’t this (the FSP version) be detected at runtime? I don't believe such a decision can be made dynamic because not all platform might like to enable pre-boot splash screen feature hence, its good to leave that flexibility in hand of the platform owner to choose if pre-boot splash screen is something that they wish to opt. From SOC side, this is a feature which platform owner can enable/disable hence, the choice has to be the there. File src/drivers/intel/fsp2_0/fsp_gop_blt.c: PS3: > How special is `efi_bmp_image_header`? Otherwise most of these functions (check, if the image is valid) could be common code in coreboot. not very big like 54 bytes in size plus we need efi_bmp_color_map and efi_graphics_output_blt_pixel. hence, better we leverage those from EDk2 headers -- To view, visit https://review.coreboot.org/c/coreboot/+/76921?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I992b45d65374f09498ff0cab497f7091e1e7a350 Gerrit-Change-Number: 76921 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 12:51:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer
by Subrata Banik (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Andrey Petrov, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Andrey Petrov, Kapil Porwal, Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76921?usp=email to look at the new patch set (#4). Change subject: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer ...................................................................... drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer This patch adds an API to convert BMP images into GOP BLT buffers for Intel FSP-S. This is required to display the OEM splash screen at pre-boot phase. Previously, Intel FSP-S had provision to consume the *.BMP file as is. However, starting with the Alder Lake platform, Intel FSP has dropped this conversion logic and expects the boot firmware to pass the BLT buffer directly. This patch implements the conversion logic in coreboot. It also adds a new config (BMP_LOGO_TO_GOP_BLT) to ensure backward compatibility with older generation FSP. BUG=b:284799726 TEST=Able to build and boot google/rex Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I992b45d65374f09498ff0cab497f7091e1e7a350 --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc A src/drivers/intel/fsp2_0/fsp_gop_blt.c A src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h 4 files changed, 295 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/76921/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/76921?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I992b45d65374f09498ff0cab497f7091e1e7a350 Gerrit-Change-Number: 76921 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: crossgcc: Upgrade GCC from 11.3.0 to 13.2.0
by Nico Huber (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Elyes Haouas, Felix Singer, Martin L Roth, Patrick Georgi. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70771?usp=email ) Change subject: crossgcc: Upgrade GCC from 11.3.0 to 13.2.0 ...................................................................... Patch Set 19: (1 comment) File util/crossgcc/buildgcc: https://review.coreboot.org/c/coreboot/+/70771/comment/a8ef9460_9401860c : PS17, Line 1155: have_gnat > I have no idea why (yet) but a gnat built with this patch and a host GCC 12.2 […] Looking at Jenkins' output, I guess CB:76489 is currently the only working solution. So we have to squash it to get a green light. -- To view, visit https://review.coreboot.org/c/coreboot/+/70771?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f2ed4de4811abaa13528906de71eee29a8f2910 Gerrit-Change-Number: 70771 Gerrit-PatchSet: 19 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 03 Aug 2023 12:50:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer
by Paul Menzel (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Andrey Petrov, Kapil Porwal, Nick Vaccaro, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76921?usp=email ) Change subject: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76921/comment/4eccaeea_95df80af : PS3, Line 15: bootloader Wrong term? https://review.coreboot.org/c/coreboot/+/76921/comment/3fa7f95a_187c01f6 : PS3, Line 18: It also adds a : new config (BMP_LOGO_TO_GOP_BLT) to ensure backward compatibility with : older generation FSP. Can’t this (the FSP version) be detected at runtime? File src/drivers/intel/fsp2_0/fsp_gop_blt.c: PS3: How special is `efi_bmp_image_header`? Otherwise most of these functions (check, if the image is valid) could be common code in coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/76921?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I992b45d65374f09498ff0cab497f7091e1e7a350 Gerrit-Change-Number: 76921 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 12:45:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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