coreboot-gerrit August 2023

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[S] Change in coreboot[master]: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO
by Michał Żygowski (Code Review) 03 Aug '23

03 Aug '23

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76418?usp=email ) Change subject: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO ...................................................................... soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO Only the headers on Intel FSP repository have the CnviWifiCore present. Options guarded for RPL like: DisableDynamicTccoldHandshake or EnableFastVmode and IccLimit is also supported by all public FSPs (except ADL-N for the handshake). Options like LowerBasicMemTestSize and DisableSagvReorder have to be guarded when FSP_USE_REPO is not selected, as publci FSPs do not have these options. Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE as dependency on the guarded UPDs to make them available for FSPs that support them as well. Also prioritize the headers from FSP repo over vendorcode headers if FSP_USE_REPO is selected. Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76418 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/vr_config.h M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/vr_config.c 5 files changed, 11 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Michał Kopeć: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 782ce22..3e8f767 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -397,13 +397,13 @@ config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N - default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE + default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if SOC_INTEL_ALDERLAKE_PCH_N && !FSP_USE_REPO + default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if SOC_INTEL_RAPTORLAKE && !FSP_USE_REPO default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S && FSP_TYPE_IOT default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P default "3rdparty/fsp/AlderLakeFspBinPkg/Client/AlderLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S - default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" + default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" if !FSP_USE_REPO config FSP_FD_PATH string diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 13abd6f..2260259 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -818,12 +818,10 @@ const struct soc_intel_alderlake_config *config) { /* CNVi */ -#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) -#if !CONFIG(SOC_INTEL_RAPTORLAKE) - /* This option is only available in public FSP headers of ADL-P and ADL-S */ +#if CONFIG(FSP_USE_REPO) + /* This option is only available in public FSP headers on FSP repo */ s_cfg->CnviWifiCore = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); #endif -#endif s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); s_cfg->CnviBtCore = config->cnvi_bt_core; s_cfg->CnviBtAudioOffload = config->cnvi_bt_audio_offload; @@ -1032,8 +1030,7 @@ s_cfg->C1e = 0; else s_cfg->C1e = 1; - -#if CONFIG(SOC_INTEL_RAPTORLAKE) +#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) s_cfg->EnableHwpScalabilityTracking = config->enable_hwp_scalability_tracking; #endif } diff --git a/src/soc/intel/alderlake/include/soc/vr_config.h b/src/soc/intel/alderlake/include/soc/vr_config.h index 41c2f6b..f43daf2 100644 --- a/src/soc/intel/alderlake/include/soc/vr_config.h +++ b/src/soc/intel/alderlake/include/soc/vr_config.h @@ -8,7 +8,7 @@ #include <fsp/api.h> struct vr_config { -#if CONFIG(SOC_INTEL_RAPTORLAKE) +#if CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(FSP_USE_REPO) /* * When enabled, this feature makes the SoC throttle when the power * consumption exceeds the I_TRIP threshold. diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 9bab919..59cd8ff 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -158,7 +158,7 @@ m_cfg->DdrFreqLimit = config->max_dram_speed_mts; m_cfg->DdrSpeedControl = 1; } -#if CONFIG(SOC_INTEL_RAPTORLAKE) +#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; m_cfg->DisableSagvReorder = config->disable_sagv_reorder; #endif @@ -272,7 +272,8 @@ m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0); m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1); -#if CONFIG(SOC_INTEL_RAPTORLAKE) +#if (CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)) || \ + (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) && CONFIG(FSP_USE_REPO)) m_cfg->DisableDynamicTccoldHandshake = config->disable_dynamic_tccold_handshake; #endif diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index cec2dd3..3467bdd 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -353,7 +353,7 @@ static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg, int domain, const struct vr_config *chip_cfg) { -#if CONFIG(SOC_INTEL_RAPTORLAKE) +#if CONFIG(SOC_INTEL_RAPTORLAKE) || CONFIG(FSP_USE_REPO) s_cfg->EnableFastVmode[domain] = chip_cfg->enable_fast_vmode; if (s_cfg->EnableFastVmode[domain]) s_cfg->IccLimit[domain] = chip_cfg->fast_vmode_i_trip; -- To view, visit https://review.coreboot.org/c/coreboot/+/76418?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Gerrit-Change-Number: 76418 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/intel/common: Return CB_ERR when cse_data_clear_request() fails
by Sridhar Siricilla (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Krishna P Bhat D, Paul Menzel, Rizwan Qureshi. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76918?usp=email ) Change subject: soc/intel/common: Return CB_ERR when cse_data_clear_request() fails ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76918?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a Gerrit-Change-Number: 76918 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 09:33:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Support ARM arch timer
by Yidi Lin (Code Review) 03 Aug '23

03 Aug '23

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76919?usp=email ) Change subject: soc/mediatek/mt8188: Support ARM arch timer ...................................................................... soc/mediatek/mt8188: Support ARM arch timer Use ARM architectual timer by initializing frequency to 13 MHz. Since system timer is the source of the architectual timer, we also call `timer_prepare` in `init_timer`. BUG=b:229800119 TEST=run `suite:faft_bios` to verify the firmware stability. check timestamps by cbmem. Change-Id: I8b1348044e4c92984510604b7f61611e13284d86 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/mt8188/Kconfig M src/soc/mediatek/mt8188/Makefile.inc A src/soc/mediatek/mt8188/timer.c 3 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/76919/1 diff --git a/src/soc/mediatek/mt8188/Kconfig b/src/soc/mediatek/mt8188/Kconfig index 6d3c659..0568cd6 100644 --- a/src/soc/mediatek/mt8188/Kconfig +++ b/src/soc/mediatek/mt8188/Kconfig @@ -13,6 +13,7 @@ select MEDIATEK_DRAM_BLOB_FAST_INIT select USE_CBMEM_DRAM_INFO select DPM_FOUR_CHANNEL + select ARM64_USE_ARCH_TIMER if SOC_MEDIATEK_MT8188 diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 67c2d7a..1426b83 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -6,7 +6,7 @@ all-y += ../common/i2c.c i2c.c all-y += ../common/pll.c pll.c all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c -all-y += ../common/timer.c ../common/timer_prepare.c +all-y += timer.c ../common/timer_prepare.c all-y += ../common/uart.c bootblock-y += bootblock.c diff --git a/src/soc/mediatek/mt8188/timer.c b/src/soc/mediatek/mt8188/timer.c new file mode 100644 index 0000000..00aaa40 --- /dev/null +++ b/src/soc/mediatek/mt8188/timer.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> +#include <delay.h> +#include <soc/timer_common.h> + +void init_timer(void) +{ + timer_prepare(); + + raw_write_cntfrq_el0(13 * MHz); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/76919?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b1348044e4c92984510604b7f61611e13284d86 Gerrit-Change-Number: 76919 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common/tcss: Configure USB-C ports with attached devices
by Subrata Banik (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Eric Lai, John Su, John Zhao, Kapil Porwal, Matt DeVillier. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72909?usp=email ) Change subject: soc/intel/common/tcss: Configure USB-C ports with attached devices ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/72909/comment/ccbddc62_653aa533 : PS4, Line 361: ret = send_pmc_connect_request(i, &mux_info, port_info); I'm afraid that we might end up sending the PMC connect cmd twice if DP=1 and USB=1 for the same port mux. -- To view, visit https://review.coreboot.org/c/coreboot/+/72909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812 Gerrit-Change-Number: 72909 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: CoolStar <coolstarorganization(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 08:46:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: drivers/intel/gma/Kconfig: Add VBT compression configuration entry
by Arthur Heymans (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Anil Kumar K, Jérémy Compostella, Subrata Banik. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76816?usp=email ) Change subject: drivers/intel/gma/Kconfig: Add VBT compression configuration entry ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76816/comment/71cc246d_c00f9d27 : PS7, Line 14: For instance, it can be set to `none' to allow the VBT binary to be : used in pre-memory stages such as romstage. Why is that necessary? Compression does work pre-memory. Is that VBT binary so large it does not fit in CAR? File src/drivers/intel/gma/Kconfig: https://review.coreboot.org/c/coreboot/+/76816/comment/ef76696f_05a45593 : PS7, Line 69: No input validation on the string? coreboot only has 2 supported compression mechanisms. Can a bool be used instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/76816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1df6a96c2ec122f0ef8ee6a1e96ffbd621b14941 Gerrit-Change-Number: 76816 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 08:39:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cbfstool: Add relocation support for EFI binaries
by Arthur Heymans (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Anil Kumar K, Cliff Huang, Jérémy Compostella, Subrata Banik. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76762?usp=email ) Change subject: cbfstool: Add relocation support for EFI binaries ...................................................................... Patch Set 7: Code-Review-2 (1 comment) Patchset: PS7: Please start a discussion on the mailing list about this. This adds the possibility for a new types of blobs. FSP was specifically designed so that non-EFI targets, which coreboot is, can consume reference code. Coreboot actively tries not to be like EFI, so some thorough discussion on the mailing list is warranted. -- To view, visit https://review.coreboot.org/c/coreboot/+/76762?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e98ffd1d864cf9ac675421471d888334d8ab28b Gerrit-Change-Number: 76762 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 08:34:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: drivers/uart/pl011: Fix regwidth
by Arthur Heymans (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Elyes Haouas, Julius Werner, Kyösti Mälkki, Paul Menzel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76883?usp=email ) Change subject: drivers/uart/pl011: Fix regwidth ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76883/comment/435b0815_9b1ff24e : PS1, Line 7: drivers/uart/pl011: Fix regwidth > … from 1 to 4 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955319d31bba5c0cd4d50f2b34111d51fea653ed Gerrit-Change-Number: 76883 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 03 Aug 2023 08:17:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: drivers/uart/pl011: Fix regwidth
by Arthur Heymans (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Elyes Haouas, Julius Werner, Kyösti Mälkki. Hello Eric Lai, Julius Werner, Kyösti Mälkki, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76883?usp=email to look at the new patch set (#2). Change subject: drivers/uart/pl011: Fix regwidth ...................................................................... drivers/uart/pl011: Fix regwidth Width of registers are always dwords on pl011, not bytes. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I955319d31bba5c0cd4d50f2b34111d51fea653ed --- M src/drivers/uart/pl011.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/76883/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955319d31bba5c0cd4d50f2b34111d51fea653ed Gerrit-Change-Number: 76883 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common/tcss: Configure USB-C ports with attached devices
by Sean Rhodes (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Eric Lai, John Su, John Zhao, Kapil Porwal, Matt DeVillier, Subrata Banik. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72909?usp=email ) Change subject: soc/intel/common/tcss: Configure USB-C ports with attached devices ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/72909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812 Gerrit-Change-Number: 72909 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: CoolStar <coolstarorganization(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 08:11:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: ec/starlabs/merlin: Update the merlin variant
by Sean Rhodes (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Martin L Roth. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74443?usp=email ) Change subject: ec/starlabs/merlin: Update the merlin variant ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > There's no need to maintain the old code for existing platforms? No, that old code wasn't ever used on production hardware. -- To view, visit https://review.coreboot.org/c/coreboot/+/74443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8384fc9322058297e8219ac8e483ac37a70bd33 Gerrit-Change-Number: 74443 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 08:09:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit August 2023