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Change subject: soc/intel/apollolake: Communicate with the PMC over Trusted Sideband
......................................................................
Abandoned
Replaced by CB:76717
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Change subject: Revert "soc/intel/apollolake: handle p2sb quirks"
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Set Ready For Review
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Change subject: soc/intel/common: Return CB_ERR when cse_data_clear_request() fails
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76918/comment/38f35d4e_846d66f8 :
PS1, Line 7: Modify incorrect return value
> Please be more specific. For example: […]
Done
https://review.coreboot.org/c/coreboot/+/76918/comment/19894c23_168556f7 :
PS1, Line 10: cse_data_clear_request fails. It was modified to CB_SUCCESS in this
> > `Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'comm […]
Done
https://review.coreboot.org/c/coreboot/+/76918/comment/88fd09fb_2ed95708 :
PS1, Line 12:
> Please add a TEST= line.
Acknowledged
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Hello Rizwan Qureshi, Sridhar Siricilla, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/intel/common: Return CB_ERR when cse_data_clear_request() fails
......................................................................
soc/intel/common: Return CB_ERR when cse_data_clear_request() fails
cse_prep_for_rw_update() should return CB_ERR when
cse_data_clear_request fails. It was modified to CB_SUCCESS in this
commit ad6d3128f87c ("soc/intel/common: Use enum cb_err values")
BRANCH=None
BUG=None
TEST=Verify the system goes to recovery during downgrade when
cse_data_clear_request() fails.
Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com>
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/76918/3
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Change subject: drivers/uart/pl011: Fix regwidth
......................................................................
Patch Set 1:
(1 comment)
File src/drivers/uart/pl011.c:
https://review.coreboot.org/c/coreboot/+/76883/comment/520c4343_a55c9b57 :
PS1, Line 38: enum cb_err
> out of scope
> it returns something else than CB_SUCCESS ?
What else should it return?
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Change subject: mb/google/rex: enable d3hot for storage devices
......................................................................
Patch Set 3:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76835/comment/2dd19361_24619d65 :
PS3, Line 9: is needed to set
needs to be set
https://review.coreboot.org/c/coreboot/+/76835/comment/1d6fa971_c7e9d8a1 :
PS3, Line 13: bypass
bypasses
https://review.coreboot.org/c/coreboot/+/76835/comment/580b8f7c_064cb094 :
PS3, Line 13: This feature also bypass the low LTR requirenet from SSD that blocking S0i2.2 LTR soc requirement.
Please reflow for 72 characters per line.
https://review.coreboot.org/c/coreboot/+/76835/comment/7ff09c49_0542946d :
PS3, Line 13: requirenet
requirement
https://review.coreboot.org/c/coreboot/+/76835/comment/8fb30c68_b8e88ac5 :
PS3, Line 15: Name (_DSD, Package () {
:         ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"),
:            Package () {
:                 Package (2) {"StorageD3Enable", 1},
: // 1 - Enable; 0 - Disable
:             }
:         }
: )
Please use either tabs or spaces for indentation.
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Change subject: drivers/uart/pl011: Fix regwidth
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76883/comment/8680059d_3110f3bf :
PS1, Line 7: drivers/uart/pl011: Fix regwidth
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