coreboot-gerrit August 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: src/*/post_code.h: Change post code prefix to POSTCODE
by Martin L Roth (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Yuchen He. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76044?usp=email ) Change subject: src/*/post_code.h: Change post code prefix to POSTCODE ...................................................................... Patch Set 8: Code-Review+2 (1 comment) File src/include/cpu/intel/post_codes.h: https://review.coreboot.org/c/coreboot/+/76044/comment/0a4fdf42_e6143e9f : PS8, Line 10: Nit: alignment issues here as well. You can fix this in a follow-on commit if you'd like. -- To view, visit https://review.coreboot.org/c/coreboot/+/76044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Gerrit-Change-Number: 76044 Gerrit-PatchSet: 8 Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Aug 2023 15:26:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/abuild: Add per-build statistics tarfile
by Martin L Roth (Code Review) 03 Aug '23

03 Aug '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75803?usp=email ) Change subject: util/abuild: Add per-build statistics tarfile ...................................................................... util/abuild: Add per-build statistics tarfile Change-Id: Icb9a5bdf94013fe493dc8ec634cf3094bcff2838 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75803 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/abuild/abuild 1 file changed, 19 insertions(+), 1 deletion(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve diff --git a/util/abuild/abuild b/util/abuild/abuild index fb2fbaf..233a661 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -420,9 +420,15 @@ cd "${build_dir}" || return $? + timestamps="abuild.timestamps" + printf "Build started %s\n" "${ts_basetime_str}" > "${timestamps}" + printf "BASETIME_SECONDS %d\n" $ts_exec_shell >> "${timestamps}" + printf "TS_0 %d\n" $ts_0 >> "${timestamps}" + printf "TS_1 %d\n" $ts_1 >> "${timestamps}" + printf "TS_2 %d\n" $ts_2 >> "${timestamps}" + duration=$(ts_delta_seconds $ts_0 $ts_2) duration_str=$(ts_delta_string $ts_0 $ts_2) - junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='$BUILD_NAME' time='$duration' >" if [ $MAKE_FAILED -eq 0 ]; then @@ -452,6 +458,13 @@ sort "${build_dir}/config.h" | grep CONFIG_ > "${build_dir}/config.h.sorted" sha256sum "${build_dir}/config.h.sorted" >> "${checksum_file}_config" fi + + stats_files="${build_dir}/${timestamps}" + if [ -f ${build_dir}/ccache.stats ]; then + stats_files="${stats_files} ${build_dir}/ccache.stats" + fi + flock -F -w 0.1 $TARGET/.statslock tar -rf ${stats_archive} ${stats_files} 2> /dev/null + if [ "$clean_work" = "true" ]; then rm -rf "${build_dir}" fi @@ -914,6 +927,8 @@ FAILED_BOARDS="$(realpath ${TARGET}/failed_boards)" PASSED_BOARDS="$(realpath ${TARGET}/passing_boards)" +stats_archive="$TARGET/statistics.tar" + # Generate a single xcompile for all boards export xcompile="${TARGET}/xcompile" @@ -921,6 +936,9 @@ rm -f "${xcompile}" $MAKE -C"${ROOT}" obj="$TARGET/temp" objutil="$TARGET/sharedutils" UPDATED_SUBMODULES=1 "${xcompile}" || exit 1 rm -f "$FAILED_BOARDS" "$PASSED_BOARDS" + + # Initialize empty statistics archive + tar -cf "${stats_archive}" "${xcompile}" 2> /dev/null fi USE_XARGS=0 -- To view, visit https://review.coreboot.org/c/coreboot/+/75803?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9a5bdf94013fe493dc8ec634cf3094bcff2838 Gerrit-Change-Number: 75803 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
by 9elements QA (Code Review) 03 Aug '23

03 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75626?usp=email ) Change subject: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen ...................................................................... Patch Set 17: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 8 / 14 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176278 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176276 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/176275 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/176274 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/176273 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176272 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/176271 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/176270 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/176268 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/176266 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176265 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/176264 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/176263 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/176262 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/75626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d Gerrit-Change-Number: 75626 Gerrit-PatchSet: 17 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 15:21:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/tcss: Configure USB-C ports with attached devices
by Subrata Banik (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Angel Pons, Eric Lai, Jakub Czapiga, John Su, John Zhao, Kapil Porwal, Matt DeVillier, Sean Rhodes. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72909?usp=email ) Change subject: soc/intel/common/tcss: Configure USB-C ports with attached devices ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/72909/comment/65d0349f_4822f078 : PS5, Line 459: if (CONFIG(EC_GOOGLE_CHROMEEC)) > This condition seems wrong. Is it because ChromeEC uses FCM (Firmware Connection Manager) whereas others use SCM (Software Connection Manager)? FCM and SCM is related to IOE FW configuration I don't believe ChromeEC has any role with it -- To view, visit https://review.coreboot.org/c/coreboot/+/72909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812 Gerrit-Change-Number: 72909 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: CoolStar <coolstarorganization(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 15:17:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/pirrha: Generate SPD ID for supported memory part
by Felix Held (Code Review) 03 Aug '23

03 Aug '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76881?usp=email ) Change subject: mb/google/nissa/var/pirrha: Generate SPD ID for supported memory part ...................................................................... mb/google/nissa/var/pirrha: Generate SPD ID for supported memory part Add pirrha supported memory parts in mem_parts_used.txt, generate SPD IDs for them. 1. K3KL8L80CM-MGCT (Samsung) 2. K3KL6L60GM-MGCT (Samsung) BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76881 Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/pirrha/memory/Makefile.inc M src/mainboard/google/brya/variants/pirrha/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt 3 files changed, 14 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pirrha/memory/Makefile.inc b/src/mainboard/google/brya/variants/pirrha/memory/Makefile.inc index eace2e4..248011d 100644 --- a/src/mainboard/google/brya/variants/pirrha/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/pirrha/memory/Makefile.inc @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pirrha/memory src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 1(0b0001) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/brya/variants/pirrha/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pirrha/memory/dram_id.generated.txt index fa24790..2e5b4ad 100644 --- a/src/mainboard/google/brya/variants/pirrha/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/pirrha/memory/dram_id.generated.txt @@ -1 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pirrha/memory src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K3KL8L80CM-MGCT 0 (0000) +K3KL6L60GM-MGCT 1 (0001) diff --git a/src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt index 9621137..9de4d15 100644 --- a/src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/pirrha/memory/mem_parts_used.txt @@ -9,3 +9,5 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +K3KL8L80CM-MGCT +K3KL6L60GM-MGCT -- To view, visit https://review.coreboot.org/c/coreboot/+/76881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664 Gerrit-Change-Number: 76881 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common/tcss: Configure USB-C ports with attached devices
by Angel Pons (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Eric Lai, Jakub Czapiga, John Su, John Zhao, Kapil Porwal, Matt DeVillier, Sean Rhodes, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72909?usp=email ) Change subject: soc/intel/common/tcss: Configure USB-C ports with attached devices ...................................................................... Patch Set 5: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/72909/comment/a342f131_ce15655e : PS5, Line 9: TCC What does TCC mean? File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/72909/comment/30f986bb_687c5e48 : PS5, Line 363: zd `%zu` ? https://review.coreboot.org/c/coreboot/+/72909/comment/40610afb_092c243f : PS5, Line 364: continue; Not sure, but linter may complain that this `continue;` is currently useless. https://review.coreboot.org/c/coreboot/+/72909/comment/aa1269b0_b1c0ed2a : PS5, Line 459: if (CONFIG(EC_GOOGLE_CHROMEEC)) This condition seems wrong. Is it because ChromeEC uses FCM (Firmware Connection Manager) whereas others use SCM (Software Connection Manager)? -- To view, visit https://review.coreboot.org/c/coreboot/+/72909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812 Gerrit-Change-Number: 72909 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: CoolStar <coolstarorganization(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 15:09:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer
by Subrata Banik (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Andrey Petrov, Kapil Porwal, Nick Vaccaro, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76921?usp=email ) Change subject: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76921/comment/f222f644_87a03625 : PS3, Line 18: It also adds a : new config (BMP_LOGO_TO_GOP_BLT) to ensure backward compatibility with : older generation FSP. > I meant, if `BMP_LOGO` is selected, then build in the BMP to GOP BLT conversion always. UPDs are different between just passing BMP image to FSP vs GOP BLT to FSP. Are you saying pass the GOP BLT by default (if BMP_LOGO is enabled) ? File src/drivers/intel/fsp2_0/fsp_gop_blt.c: PS3: > Maybe the same structs could be used for coreboot in general, and then only the structs are converted, and the newly added function would be common code. coreboot’s splash screen feature also supports BMP, so having a checker for that could be used there too. why would coreboot like to convert BMP into GOP BLT format (for EFI header efi_graphics_output_blt_pixel). As mentioned earlier GOP BLT format is more for UEFI BMP driver code. I don't see any value at this stage to adopt this solution for common code beyond just FSP driver. if coreboot would like to render the BMP image to the framebuffer, we shouldn't be relying on the efi_graphics_output_blt_pixel structure. -- To view, visit https://review.coreboot.org/c/coreboot/+/76921?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I992b45d65374f09498ff0cab497f7091e1e7a350 Gerrit-Change-Number: 76921 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 14:59:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Merge TME new key gen and exclusion range configs
by 9elements QA (Code Review) 03 Aug '23

03 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76879?usp=email ) Change subject: soc/intel/common: Merge TME new key gen and exclusion range configs ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 9 / 15 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176261 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176259 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/176258 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/176257 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/176256 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176255 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/176254 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/176253 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/176252 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/176251 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/176249 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176248 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/176247 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/176246 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/176245 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76879?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d9504229adb1abff2ef394c4ca113c335099c2 Gerrit-Change-Number: 76879 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 14:54:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: security/tpm/: turn tis_{init,open} into tis_probe
by Michał Żygowski (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Sergii Dmytruk. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68991?usp=email ) Change subject: security/tpm/: turn tis_{init,open} into tis_probe ...................................................................... Patch Set 6: (1 comment) File src/security/tpm/tss/tcg-2.0/tss.c: https://review.coreboot.org/c/coreboot/+/68991/comment/8c86d807_aa1797a6 : PS6, Line 32: die("TSS 2.0 wasn't initialized\n"); > It boots fine after reverting this change. Thanks Sergii for the due diligence. […] Can't we just return NULL? If TPM command could nto be processed that is not such a big deal to halt the platform. Instead the caller should handle eventual error path -- To view, visit https://review.coreboot.org/c/coreboot/+/68991?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ce35ada24e3959ea1a518c29d431b4ae123809 Gerrit-Change-Number: 68991 Gerrit-PatchSet: 6 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 14:37:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/craaskov: Add overridetree
by 9elements QA (Code Review) 03 Aug '23

03 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76662?usp=email ) Change subject: mb/google/nissa/var/craaskov: Add overridetree ...................................................................... Patch Set 11: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 9 / 15 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176244 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176242 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/176241 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/176240 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/176239 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176238 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/176237 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/176236 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/176235 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/176234 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/176232 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176231 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/176230 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/176229 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/176228 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id002282d91dc94b00f5d133203b62ca39d6cae6d Gerrit-Change-Number: 76662 Gerrit-PatchSet: 11 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 14:32:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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