coreboot-gerrit August 2023

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[XS] Change in coreboot[master]: include/efi: Include BMP and BLT header macro definitions
by Paz Zcharya (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Paz Zcharya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76920?usp=email ) Change subject: include/efi: Include BMP and BLT header macro definitions ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e282d135007d288aadb5996a662524f76428874 Gerrit-Change-Number: 76920 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 14:26:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer
by Paul Menzel (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Andrey Petrov, Kapil Porwal, Nick Vaccaro, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76921?usp=email ) Change subject: drivers/intel/fsp2_0: Add API to convert BMP images to GOP BLT buffer ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76921/comment/41c46feb_c9327bd0 : PS3, Line 18: It also adds a : new config (BMP_LOGO_TO_GOP_BLT) to ensure backward compatibility with : older generation FSP. > > Can’t this (the FSP version) be detected at runtime? […] I meant, if `BMP_LOGO` is selected, then build in the BMP to GOP BLT conversion always. File src/drivers/intel/fsp2_0/fsp_gop_blt.c: PS3: > > How special is `efi_bmp_image_header`? Otherwise most of these functions (check, if the image is v […] Maybe the same structs could be used for coreboot in general, and then only the structs are converted, and the newly added function would be common code. coreboot’s splash screen feature also supports BMP, so having a checker for that could be used there too. -- To view, visit https://review.coreboot.org/c/coreboot/+/76921?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I992b45d65374f09498ff0cab497f7091e1e7a350 Gerrit-Change-Number: 76921 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 14:19:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
by Sridhar Siricilla (Code Review) 03 Aug '23

03 Aug '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75626?usp=email ) ( 15 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen ...................................................................... soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen Set UPD params GenerateNewTmeKey, TmeExcludeBase, and TmeExcludeSize when TME_KEY_REGENERATION_ON_WARM_BOOT config is enabled. These UPDs are programmed only when INTEL_TME is enabled. Bug=b:276120526 TEST=Able to build REX platform. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d Reviewed-on: https://review.coreboot.org/c/coreboot/+/75626 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/romstage/fsp_params.c 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, but someone else must approve build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 40b7c47..fd634ec 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -8,6 +8,7 @@ #include <drivers/wifi/generic/wifi.h> #include <fsp/fsp_debug_event.h> #include <fsp/util.h> +#include <intelbasecode/ramtop.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcie_rp.h> #include <option.h> @@ -173,12 +174,30 @@ m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); } +static void fill_tme_params(FSP_M_CONFIG *m_cfg) +{ + m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); + if (!m_cfg->TmeEnable) + return; + m_cfg->GenerateNewTmeKey = CONFIG(TME_KEY_REGENERATION_ON_WARM_BOOT); + if (m_cfg->GenerateNewTmeKey) { + uint32_t ram_top = get_ramtop_addr(); + if (!ram_top) { + printk(BIOS_WARNING, "Invalid exclusion range start address. " + "Full memory encryption is enabled.\n"); + return; + } + m_cfg->TmeExcludeBase = (ram_top - 16*MiB); + m_cfg->TmeExcludeSize = 16*MiB; + } +} + static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; - m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); + fill_tme_params(m_cfg); } static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/75626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d Gerrit-Change-Number: 75626 Gerrit-PatchSet: 17 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: drivers/uart/pl011: Fix regwidth
by Paul Menzel (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Arthur Heymans, Elyes Haouas, Julius Werner, Kyösti Mälkki. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76883?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: drivers/uart/pl011: Fix regwidth ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76883/comment/2bde4317_9a79da00 : PS1, Line 7: drivers/uart/pl011: Fix regwidth > Done If you meant to update the summary, there is no change in patchset 2. -- To view, visit https://review.coreboot.org/c/coreboot/+/76883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955319d31bba5c0cd4d50f2b34111d51fea653ed Gerrit-Change-Number: 76883 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 03 Aug 2023 14:13:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google: Add more comment on GFX devices for the future reference
by 9elements QA (Code Review) 03 Aug '23

03 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76776?usp=email ) Change subject: mb/google: Add more comment on GFX devices for the future reference ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 8 / 14 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176227 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176225 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/176224 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/176223 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/176222 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176221 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/176220 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/176219 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/176217 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/176215 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176214 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/176213 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/176212 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/176211 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224 Gerrit-Change-Number: 76776 Gerrit-PatchSet: 6 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 14:10:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros
by Felix Held (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76886?usp=email ) Change subject: soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/include/amdblocks/data_fabric_defs.h: https://review.coreboot.org/c/coreboot/+/76886/comment/40adde5f_9eb0f727 : PS1, Line 6: 11 bits had an off by one in my calculation, but at least the macros were correct -- To view, visit https://review.coreboot.org/c/coreboot/+/76886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63a284b26081c170a217b082b100c482f6158e7e Gerrit-Change-Number: 76886 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 14:05:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/*/include/data_fabric: reorder register definitions
by Felix Held (Code Review) 03 Aug '23

03 Aug '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76923?usp=email ) Change subject: soc/amd/*/include/data_fabric: reorder register definitions ...................................................................... soc/amd/*/include/data_fabric: reorder register definitions Order the data fabric register definitions by function number and register offset. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia3066ad0f564520cb322a3e41a413eb3bf51260d --- M src/soc/amd/cezanne/include/soc/data_fabric.h M src/soc/amd/glinda/include/soc/data_fabric.h M src/soc/amd/mendocino/include/soc/data_fabric.h M src/soc/amd/phoenix/include/soc/data_fabric.h M src/soc/amd/picasso/include/soc/data_fabric.h 5 files changed, 73 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/76923/1 diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h index b51a3de..a8d06e9 100644 --- a/src/soc/amd/cezanne/include/soc/data_fabric.h +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -6,19 +6,15 @@ #include <amdblocks/data_fabric_defs.h> #include <types.h> +#define IOMS0_FABRIC_ID 10 + #define DF_MMIO_BASE0 DF_REG_ID(0, 0x200) #define DF_MMIO_LIMIT0 DF_REG_ID(0, 0x204) #define DF_MMIO_SHIFT 16 #define DF_MMIO_CTRL0 DF_REG_ID(0, 0x208) -#define DF_MMIO_REG_SET_SIZE 4 -#define DF_MMIO_REG_SET_COUNT 8 - -#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C) -#define DF_FICAD_LO DF_REG_ID(4, 0x98) -#define DF_FICAD_HI DF_REG_ID(4, 0x9C) - -#define IOMS0_FABRIC_ID 10 +#define DF_MMIO_REG_SET_SIZE 4 +#define DF_MMIO_REG_SET_COUNT 8 union df_mmio_control { struct { @@ -33,6 +29,10 @@ uint32_t raw; }; +#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C) +#define DF_FICAD_LO DF_REG_ID(4, 0x98) +#define DF_FICAD_HI DF_REG_ID(4, 0x9C) + union df_ficaa { struct { uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h index c03c70e..dac7e04 100644 --- a/src/soc/amd/glinda/include/soc/data_fabric.h +++ b/src/soc/amd/glinda/include/soc/data_fabric.h @@ -6,19 +6,15 @@ #include <amdblocks/data_fabric_defs.h> #include <types.h> +#define IOMS0_FABRIC_ID 15 + #define DF_MMIO_BASE0 DF_REG_ID(0, 0xD80) #define DF_MMIO_LIMIT0 DF_REG_ID(0, 0xD84) #define DF_MMIO_SHIFT 16 #define DF_MMIO_CTRL0 DF_REG_ID(0, 0xD88) -#define DF_MMIO_REG_SET_SIZE 4 -#define DF_MMIO_REG_SET_COUNT 8 - -#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C) -#define DF_FICAD_LO DF_REG_ID(4, 0xB8) -#define DF_FICAD_HI DF_REG_ID(4, 0xBC) - -#define IOMS0_FABRIC_ID 15 +#define DF_MMIO_REG_SET_SIZE 4 +#define DF_MMIO_REG_SET_COUNT 8 union df_mmio_control { struct { @@ -33,6 +29,10 @@ uint32_t raw; }; +#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C) +#define DF_FICAD_LO DF_REG_ID(4, 0xB8) +#define DF_FICAD_HI DF_REG_ID(4, 0xBC) + union df_ficaa { struct { uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h index 548a3b51..9824544 100644 --- a/src/soc/amd/mendocino/include/soc/data_fabric.h +++ b/src/soc/amd/mendocino/include/soc/data_fabric.h @@ -6,24 +6,20 @@ #include <amdblocks/data_fabric_defs.h> #include <types.h> +#define IOMS0_FABRIC_ID 9 + #define DF_MMIO_BASE0 DF_REG_ID(0, 0x200) #define DF_MMIO_LIMIT0 DF_REG_ID(0, 0x204) #define DF_MMIO_SHIFT 16 #define DF_MMIO_CTRL0 DF_REG_ID(0, 0x208) #if CONFIG(SOC_AMD_REMBRANDT) -#define DF_MMIO_REG_SET_SIZE 3 +#define DF_MMIO_REG_SET_SIZE 3 #else -#define DF_MMIO_REG_SET_SIZE 4 +#define DF_MMIO_REG_SET_SIZE 4 #endif -#define DF_MMIO_REG_SET_COUNT 8 - -#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C) -#define DF_FICAD_LO DF_REG_ID(4, 0x98) -#define DF_FICAD_HI DF_REG_ID(4, 0x9C) - -#define IOMS0_FABRIC_ID 9 +#define DF_MMIO_REG_SET_COUNT 8 union df_mmio_control { struct { @@ -38,6 +34,10 @@ uint32_t raw; }; +#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C) +#define DF_FICAD_LO DF_REG_ID(4, 0x98) +#define DF_FICAD_HI DF_REG_ID(4, 0x9C) + union df_ficaa { struct { uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ diff --git a/src/soc/amd/phoenix/include/soc/data_fabric.h b/src/soc/amd/phoenix/include/soc/data_fabric.h index ca144e1..53316f3 100644 --- a/src/soc/amd/phoenix/include/soc/data_fabric.h +++ b/src/soc/amd/phoenix/include/soc/data_fabric.h @@ -6,19 +6,15 @@ #include <amdblocks/data_fabric_defs.h> #include <types.h> +#define IOMS0_FABRIC_ID 0x13 + #define DF_MMIO_BASE0 DF_REG_ID(0, 0xD80) #define DF_MMIO_LIMIT0 DF_REG_ID(0, 0xD84) #define DF_MMIO_SHIFT 16 #define DF_MMIO_CTRL0 DF_REG_ID(0, 0xD88) -#define DF_MMIO_REG_SET_SIZE 4 -#define DF_MMIO_REG_SET_COUNT 8 - -#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C) -#define DF_FICAD_LO DF_REG_ID(4, 0xB8) -#define DF_FICAD_HI DF_REG_ID(4, 0xBC) - -#define IOMS0_FABRIC_ID 0x13 +#define DF_MMIO_REG_SET_SIZE 4 +#define DF_MMIO_REG_SET_COUNT 8 union df_mmio_control { struct { @@ -33,6 +29,10 @@ uint32_t raw; }; +#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C) +#define DF_FICAD_LO DF_REG_ID(4, 0xB8) +#define DF_FICAD_HI DF_REG_ID(4, 0xBC) + union df_ficaa { struct { uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 5926e49d..880afe1 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -6,46 +6,7 @@ #include <amdblocks/data_fabric_defs.h> #include <types.h> -#define DF_MMIO_BASE0 DF_REG_ID(0, 0x200) -#define DF_MMIO_LIMIT0 DF_REG_ID(0, 0x204) -#define DF_MMIO_SHIFT 16 -#define DF_MMIO_CTRL0 DF_REG_ID(0, 0x208) - -#define DF_MMIO_REG_SET_SIZE 4 -#define DF_MMIO_REG_SET_COUNT 8 - -#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C) -#define DF_FICAD_LO DF_REG_ID(4, 0x98) -#define DF_FICAD_HI DF_REG_ID(4, 0x9C) - -#define IOMS0_FABRIC_ID 9 - -union df_mmio_control { - struct { - uint32_t re : 1; /* [ 0.. 0] */ - uint32_t we : 1; /* [ 1.. 1] */ - uint32_t : 2; /* [ 3.. 2] */ - uint32_t fabric_id : 8; /* [11.. 4] */ - uint32_t np : 1; /* [12..12] */ - uint32_t : 19; /* [31..13] */ - }; - uint32_t raw; -}; - -union df_ficaa { - struct { - uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ - uint32_t : 1; /* [ 1.. 1] */ - uint32_t reg_num : 9; /* [10.. 2] */ - uint32_t func_num : 3; /* [13..11] */ - uint32_t b64_en : 1; /* [14..14] */ - uint32_t : 1; /* [15..15] */ - uint32_t inst_id : 8; /* [23..16] */ - uint32_t : 8; /* [31..24] */ - }; - uint32_t raw; -}; - +#define IOMS0_FABRIC_ID 9 #define D18F0_VGAEN DF_REG_ID(0, 0x80) #define VGA_ADDR_ENABLE BIT(0) @@ -55,7 +16,7 @@ #define DRAM_HOLE_CTL_BASE_SHFT 24 #define DRAM_HOLE_CTL_BASE (0xff << DRAM_HOLE_CTL_BASE_SHFT) -#define DF_DRAM_BASE0 DF_REG_ID(0, 0x110) +#define DF_DRAM_BASE0 DF_REG_ID(0, 0x110) #define DRAM_BASE_REG_VALID BIT(0) #define DRAM_BASE_HOLE_EN BIT(1) #define DRAM_BASE_INTLV_CH_SHFT 4 @@ -82,4 +43,42 @@ #define DF_DRAM_LIMIT(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \ + DF_DRAM_LIMIT0) +#define DF_MMIO_BASE0 DF_REG_ID(0, 0x200) +#define DF_MMIO_LIMIT0 DF_REG_ID(0, 0x204) +#define DF_MMIO_SHIFT 16 +#define DF_MMIO_CTRL0 DF_REG_ID(0, 0x208) + +#define DF_MMIO_REG_SET_SIZE 4 +#define DF_MMIO_REG_SET_COUNT 8 + +union df_mmio_control { + struct { + uint32_t re : 1; /* [ 0.. 0] */ + uint32_t we : 1; /* [ 1.. 1] */ + uint32_t : 2; /* [ 3.. 2] */ + uint32_t fabric_id : 8; /* [11.. 4] */ + uint32_t np : 1; /* [12..12] */ + uint32_t : 19; /* [31..13] */ + }; + uint32_t raw; +}; + +#define DF_FICAA_BIOS DF_REG_ID(4, 0x5C) +#define DF_FICAD_LO DF_REG_ID(4, 0x98) +#define DF_FICAD_HI DF_REG_ID(4, 0x9C) + +union df_ficaa { + struct { + uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */ + uint32_t : 1; /* [ 1.. 1] */ + uint32_t reg_num : 9; /* [10.. 2] */ + uint32_t func_num : 3; /* [13..11] */ + uint32_t b64_en : 1; /* [14..14] */ + uint32_t : 1; /* [15..15] */ + uint32_t inst_id : 8; /* [23..16] */ + uint32_t : 8; /* [31..24] */ + }; + uint32_t raw; +}; + #endif /* AMD_PICASSO_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/76923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3066ad0f564520cb322a3e41a413eb3bf51260d Gerrit-Change-Number: 76923 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_*
by Matt DeVillier (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76889?usp=email ) Change subject: soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_* ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a26402b8078d288a7e32c1668591d001fa3ede9 Gerrit-Change-Number: 76889 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Aug 2023 13:52:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/*/include/data_fabric: rename D18F0_MMIO_* to DF_MMIO_*
by Matt DeVillier (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Raul Rangel. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76888?usp=email ) Change subject: soc/amd/*/include/data_fabric: rename D18F0_MMIO_* to DF_MMIO_* ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0355838ac1d513ba562fd6fb4672342dd383498 Gerrit-Change-Number: 76888 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Aug 2023 13:52:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/common/data_fabric_helper: use DF broadcast read/write functions
by Matt DeVillier (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Raul Rangel. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76887?usp=email ) Change subject: soc/amd/common/data_fabric_helper: use DF broadcast read/write functions ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76887?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I174c1e6ee4856d97c5ec6d07bb8c217d6df9425f Gerrit-Change-Number: 76887 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Aug 2023 13:52:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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