coreboot-gerrit August 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: util/abuild: Add per-build statistics tarfile
by 9elements QA (Code Review) 03 Aug '23

03 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75803?usp=email ) Change subject: util/abuild: Add per-build statistics tarfile ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 9 / 15 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176313 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176311 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/176310 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/176309 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/176308 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176307 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/176306 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/176305 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/176304 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/176303 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/176301 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176300 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/176299 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/176298 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/176297 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/75803?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb9a5bdf94013fe493dc8ec634cf3094bcff2838 Gerrit-Change-Number: 75803 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 16:54:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: src/*/post_code.h: Change post code prefix to POSTCODE
by Yuchen He (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Eric Lai, Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Paul Menzel, Raul Rangel. Yuchen He has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76044?usp=email ) Change subject: src/*/post_code.h: Change post code prefix to POSTCODE ...................................................................... Patch Set 9: (1 comment) File src/include/cpu/intel/post_codes.h: https://review.coreboot.org/c/coreboot/+/76044/comment/f251024d_79874fa0 : PS8, Line 10: > Nit: alignment issues here as well. You can fix this in a follow-on commit if you'd like. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Gerrit-Change-Number: 76044 Gerrit-PatchSet: 9 Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Aug 2023 16:52:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: src/*/post_code.h: Change post code prefix to POSTCODE
by Yuchen He (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Eric Lai, Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Paul Menzel, Raul Rangel, Yuchen He. Hello Eric Lai, Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Raul Rangel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76044?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Code-Review+1 by Eric Lai, Code-Review+2 by Martin L Roth, Verified+1 by build bot (Jenkins) Change subject: src/*/post_code.h: Change post code prefix to POSTCODE ...................................................................... src/*/post_code.h: Change post code prefix to POSTCODE The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. header="src/soc/amd/common/block/include/amdblocks/post_codes.h \ src/include/cpu/intel/post_codes.h \ src/soc/intel/common/block/include/intelblocks/post_codes.h" array=`grep -r "#define POST_" $header | \ tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2` for str in $array; do splitstr=`echo $str | cut -d '_' -f2-` grep -r $str src | cut -d ':' -f 1 | \ xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g" done Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: Yuchen He <yuchenhe126(a)gmail.com> --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/drivers/amd/agesa/cache_as_ram.S M src/include/cpu/intel/post_codes.h M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/cpu/car/cache_as_ram.S M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/amd/common/block/include/amdblocks/post_codes.h M src/soc/amd/common/psp_verstage/include/psp_post_code.h M src/soc/amd/glinda/romstage.c M src/soc/amd/mendocino/romstage.c M src/soc/amd/phoenix/romstage.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/bootblock.c M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/post_codes.h 23 files changed, 159 insertions(+), 159 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/76044/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/76044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Gerrit-Change-Number: 76044 Gerrit-PatchSet: 9 Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: drivers/intel/gma/Kconfig: Add VBT compression configuration entry
by Jérémy Compostella (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Anil Kumar K, Arthur Heymans, Subrata Banik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76816?usp=email ) Change subject: drivers/intel/gma/Kconfig: Add VBT compression configuration entry ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76816/comment/f11d373f_bf456652 : PS7, Line 14: For instance, it can be set to `none' to allow the VBT binary to be : used in pre-memory stages such as romstage. > Why is that necessary? Compression does work pre-memory. […] I could not get it to work on x86 (cf. code below). Listing. src/lib/cbfs.c 448 } else if (!cbfs_cache.size) { 449 /* In order to use the cbfs_cache you need to add a CBFS_CACHE to your 450 * memlayout. For stages that don't have .data sections (x86 pre-RAM), 451 * it is not possible to add a CBFS_CACHE. */ 452 ERROR("Cannot map compressed file %s without cbfs_cache\n", mdata->h.filename); 453 return NULL; 454 } else { File src/drivers/intel/gma/Kconfig: https://review.coreboot.org/c/coreboot/+/76816/comment/e86c1299_5a3537fe : PS7, Line 69: > No input validation on the string? coreboot only has 2 supported compression mechanisms. […] To my knowledge coreboot supports `none`, `lzma` and `lz4` so it cannot be a boolean. -- To view, visit https://review.coreboot.org/c/coreboot/+/76816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1df6a96c2ec122f0ef8ee6a1e96ffbd621b14941 Gerrit-Change-Number: 76816 Gerrit-PatchSet: 8 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Aug 2023 16:45:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: device/dram: add DDR4 MRS commands
by Martin L Roth (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Andrey Petrov, David Hendricks, Matt DeVillier, Michał Żygowski, Paul Menzel, Sergii Dmytruk. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67059?usp=email ) Change subject: device/dram: add DDR4 MRS commands ...................................................................... Patch Set 11: Code-Review+2 (1 comment) File src/include/device/dram/ddr4.h: https://review.coreboot.org/c/coreboot/+/67059/comment/9af0b0c7_f0ceefb5 : PS11, Line 106: typedef u32 mrs_cmd_t; Nit: We prefer not to use typedefs unless there's a specific reason to. https://doc.coreboot.org/contributing/coding_style.html#typedefs I'll leave it up to you whether there's a specific reason here, but I didn't see a reason that u32 or uint32_t couldn't be used. Since this (at worst) is a minor coding style violation, so feel free to fix it in a follow-on patch as well if you desire. -- To view, visit https://review.coreboot.org/c/coreboot/+/67059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d4f048c859bc89897d50a5a07468c3375aa1dcf Gerrit-Change-Number: 67059 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 16:44:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: enable d3hot for storage devices
by Sukumar Ghorai (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Eran Mitrani, Eric Lai, Jakub Czapiga, Kangheui Won, Kapil Porwal, Paul Menzel, Sumeet R Pawnikar, Tarun Tuli. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76835?usp=email ) Change subject: mb/google/rex: enable d3hot for storage devices ...................................................................... Patch Set 3: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76835/comment/f1e49ee7_c485f321 : PS3, Line 9: is needed to set > needs to be set Acknowledged https://review.coreboot.org/c/coreboot/+/76835/comment/889f8aeb_4ad4bdca : PS3, Line 13: bypass > bypasses Acknowledged https://review.coreboot.org/c/coreboot/+/76835/comment/1813c4eb_a34b1eb9 : PS3, Line 13: requirenet > requirement Acknowledged https://review.coreboot.org/c/coreboot/+/76835/comment/ded54aa9_4e0e3162 : PS3, Line 13: This feature also bypass the low LTR requirenet from SSD that blocking S0i2.2 LTR soc requirement. > Please reflow for 72 characters per line. Acknowledged https://review.coreboot.org/c/coreboot/+/76835/comment/2093829c_698eb6c6 : PS3, Line 15: Name (_DSD, Package () { :         ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"), :            Package () { :                 Package (2) {"StorageD3Enable", 1}, : // 1 - Enable; 0 - Disable :             } :         } : ) > Please use either tabs or spaces for indentation. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/76835?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7 Gerrit-Change-Number: 76835 Gerrit-PatchSet: 3 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 16:43:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: enable d3hot for storage devices
by Sukumar Ghorai (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kangheui Won, Kapil Porwal, Sukumar Ghorai, Sumeet R Pawnikar, Tarun Tuli. Hello Jakub Czapiga, Kangheui Won, Kapil Porwal, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76835?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Kangheui Won, Code-Review+2 by Kapil Porwal, Code-Review+2 by Sumeet R Pawnikar, Verified+1 by build bot (Jenkins) Change subject: mb/google/rex: enable d3hot for storage devices ...................................................................... mb/google/rex: enable d3hot for storage devices _DSD "StorageD3Enable" property is needs to be set under the root port in the DSDT or SSDT. The ACPI _DSD method is the preferred way to opt D3hot support for storage devices. This also bypasses the low LTR from SSD that blocking S0i2.2 LTR/latency SoC requirement. Name (_DSD, Package () { ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"), Package () { Package (2) {"StorageD3Enable", 1}, // 1 - Enable; 0 - Disable } } ) BUG=b:289028958 TEST=Check code compiles & boot rex, and verify the "StorageD3Enable" SSDT entry. Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7 Signed-off-by: Kangheui Won <khwon(a)chromium.org> Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/76835/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/76835?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7 Gerrit-Change-Number: 76835 Gerrit-PatchSet: 4 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/{skl,kbl}: Use true/false keywords for non-array dt options
by Angel Pons (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Felix Singer, Frans Hendriks, Jeremy Soller, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Sean Rhodes, Tim Crawford. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75888?usp=email ) Change subject: mb/{skl,kbl}: Use true/false keywords for non-array dt options ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75888/comment/9340d804_5cb31564 : PS5, Line 13: While on it, remove the quotes from the option name and from the value. Huh, how does this work? Is there special support in SCONFIG? Currently, it looks rather odd because the other `register` lines still use quotes. -- To view, visit https://review.coreboot.org/c/coreboot/+/75888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff063c37a093e597c6b73a583903ce5e4f698856 Gerrit-Change-Number: 75888 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 16:36:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/pirrha: Generate SPD ID for supported memory part
by 9elements QA (Code Review) 03 Aug '23

03 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76881?usp=email ) Change subject: mb/google/nissa/var/pirrha: Generate SPD ID for supported memory part ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 6 / 8 / 14 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176296 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/176294 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/176293 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/176292 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/176291 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176290 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/176289 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/176288 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/176286 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/176284 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/176283 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/176282 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/176281 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/176280 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664 Gerrit-Change-Number: 76881 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Aug 2023 16:32:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: Makefile.inc: Fix typo in FILANAME in comment
by Jérémy Compostella (Code Review) 03 Aug '23

03 Aug '23

Attention is currently required from: Jérémy Compostella, Martin L Roth. Hello Elyes Haouas, Martin L Roth, Sridhar Siricilla, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76890?usp=email to look at the new patch set (#2). Change subject: Makefile.inc: Fix typo in FILANAME in comment ...................................................................... Makefile.inc: Fix typo in FILANAME in comment Change-Id: I96388245df406e6b4cb1cd3418f6a32d5b23499f Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/76890/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76890?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96388245df406e6b4cb1cd3418f6a32d5b23499f Gerrit-Change-Number: 76890 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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